drm/arm/hdlcd_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  ARM HDLCD Controller register definition
0004  */
0005
0006 #ifndef __HDLCD_DRV_H__
0007 #define __HDLCD_DRV_H__
0008
0009 struct hdlcd_drm_private {
0010     void __iomem            *mmio;
0011     struct clk          *clk;
0012     struct drm_crtc         crtc;
0013     struct drm_plane        *plane;
0014     unsigned int            irq;
0015 #ifdef CONFIG_DEBUG_FS
0016     atomic_t buffer_underrun_count;
0017     atomic_t bus_error_count;
0018     atomic_t vsync_count;
0019     atomic_t dma_end_count;
0020 #endif
0021 };
0022
0023 #define crtc_to_hdlcd_priv(x)   container_of(x, struct hdlcd_drm_private, crtc)
0024
0025 static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd,
0026                    unsigned int reg, u32 value)
0027 {
0028     writel(value, hdlcd->mmio + reg);
0029 }
0030
0031 static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg)
0032 {
0033     return readl(hdlcd->mmio + reg);
0034 }
0035
0036 int hdlcd_setup_crtc(struct drm_device *dev);
0037 void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
0038
0039 #endif /* __HDLCD_DRV_H__ */