drm/arm/hdlcd_drv.c

0001 /*
0002  * Copyright (C) 2013-2015 ARM Limited
0003  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
0004  *
0005  * This file is subject to the terms and conditions of the GNU General Public
0006  * License.  See the file COPYING in the main directory of this archive
0007  * for more details.
0008  *
0009  *  ARM HDLCD Driver
0010  */
0011
0012 #include <linux/module.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/clk.h>
0015 #include <linux/component.h>
0016 #include <linux/console.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/list.h>
0019 #include <linux/of_graph.h>
0020 #include <linux/of_reserved_mem.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023
0024 #include <drm/drm_atomic_helper.h>
0025 #include <drm/drm_crtc.h>
0026 #include <drm/drm_debugfs.h>
0027 #include <drm/drm_drv.h>
0028 #include <drm/drm_fb_cma_helper.h>
0029 #include <drm/drm_fb_helper.h>
0030 #include <drm/drm_gem_cma_helper.h>
0031 #include <drm/drm_gem_framebuffer_helper.h>
0032 #include <drm/drm_modeset_helper.h>
0033 #include <drm/drm_module.h>
0034 #include <drm/drm_of.h>
0035 #include <drm/drm_probe_helper.h>
0036 #include <drm/drm_vblank.h>
0037
0038 #include "hdlcd_drv.h"
0039 #include "hdlcd_regs.h"
0040
0041 static irqreturn_t hdlcd_irq(int irq, void *arg)
0042 {
0043     struct drm_device *drm = arg;
0044     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0045     unsigned long irq_status;
0046
0047     irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
0048
0049 #ifdef CONFIG_DEBUG_FS
0050     if (irq_status & HDLCD_INTERRUPT_UNDERRUN)
0051         atomic_inc(&hdlcd->buffer_underrun_count);
0052
0053     if (irq_status & HDLCD_INTERRUPT_DMA_END)
0054         atomic_inc(&hdlcd->dma_end_count);
0055
0056     if (irq_status & HDLCD_INTERRUPT_BUS_ERROR)
0057         atomic_inc(&hdlcd->bus_error_count);
0058
0059     if (irq_status & HDLCD_INTERRUPT_VSYNC)
0060         atomic_inc(&hdlcd->vsync_count);
0061
0062 #endif
0063     if (irq_status & HDLCD_INTERRUPT_VSYNC)
0064         drm_crtc_handle_vblank(&hdlcd->crtc);
0065
0066     /* acknowledge interrupt(s) */
0067     hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
0068
0069     return IRQ_HANDLED;
0070 }
0071
0072 static void hdlcd_irq_preinstall(struct drm_device *drm)
0073 {
0074     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0075     /* Ensure interrupts are disabled */
0076     hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
0077     hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
0078 }
0079
0080 static void hdlcd_irq_postinstall(struct drm_device *drm)
0081 {
0082 #ifdef CONFIG_DEBUG_FS
0083     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0084     unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
0085
0086     /* enable debug interrupts */
0087     irq_mask |= HDLCD_DEBUG_INT_MASK;
0088
0089     hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
0090 #endif
0091 }
0092
0093 static int hdlcd_irq_install(struct drm_device *drm, int irq)
0094 {
0095     int ret;
0096
0097     if (irq == IRQ_NOTCONNECTED)
0098         return -ENOTCONN;
0099
0100     hdlcd_irq_preinstall(drm);
0101
0102     ret = request_irq(irq, hdlcd_irq, 0, drm->driver->name, drm);
0103     if (ret)
0104         return ret;
0105
0106     hdlcd_irq_postinstall(drm);
0107
0108     return 0;
0109 }
0110
0111 static void hdlcd_irq_uninstall(struct drm_device *drm)
0112 {
0113     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0114     /* disable all the interrupts that we might have enabled */
0115     unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
0116
0117 #ifdef CONFIG_DEBUG_FS
0118     /* disable debug interrupts */
0119     irq_mask &= ~HDLCD_DEBUG_INT_MASK;
0120 #endif
0121
0122     /* disable vsync interrupts */
0123     irq_mask &= ~HDLCD_INTERRUPT_VSYNC;
0124     hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
0125
0126     free_irq(hdlcd->irq, drm);
0127 }
0128
0129 static int hdlcd_load(struct drm_device *drm, unsigned long flags)
0130 {
0131     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0132     struct platform_device *pdev = to_platform_device(drm->dev);
0133     struct resource *res;
0134     u32 version;
0135     int ret;
0136
0137     hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
0138     if (IS_ERR(hdlcd->clk))
0139         return PTR_ERR(hdlcd->clk);
0140
0141 #ifdef CONFIG_DEBUG_FS
0142     atomic_set(&hdlcd->buffer_underrun_count, 0);
0143     atomic_set(&hdlcd->bus_error_count, 0);
0144     atomic_set(&hdlcd->vsync_count, 0);
0145     atomic_set(&hdlcd->dma_end_count, 0);
0146 #endif
0147
0148     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0149     hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
0150     if (IS_ERR(hdlcd->mmio)) {
0151         DRM_ERROR("failed to map control registers area\n");
0152         ret = PTR_ERR(hdlcd->mmio);
0153         hdlcd->mmio = NULL;
0154         return ret;
0155     }
0156
0157     version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
0158     if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
0159         DRM_ERROR("unknown product id: 0x%x\n", version);
0160         return -EINVAL;
0161     }
0162     DRM_INFO("found ARM HDLCD version r%dp%d\n",
0163         (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
0164         version & HDLCD_VERSION_MINOR_MASK);
0165
0166     /* Get the optional framebuffer memory resource */
0167     ret = of_reserved_mem_device_init(drm->dev);
0168     if (ret && ret != -ENODEV)
0169         return ret;
0170
0171     ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
0172     if (ret)
0173         goto setup_fail;
0174
0175     ret = hdlcd_setup_crtc(drm);
0176     if (ret < 0) {
0177         DRM_ERROR("failed to create crtc\n");
0178         goto setup_fail;
0179     }
0180
0181     ret = platform_get_irq(pdev, 0);
0182     if (ret < 0)
0183         goto irq_fail;
0184     hdlcd->irq = ret;
0185
0186     ret = hdlcd_irq_install(drm, hdlcd->irq);
0187     if (ret < 0) {
0188         DRM_ERROR("failed to install IRQ handler\n");
0189         goto irq_fail;
0190     }
0191
0192     return 0;
0193
0194 irq_fail:
0195     drm_crtc_cleanup(&hdlcd->crtc);
0196 setup_fail:
0197     of_reserved_mem_device_release(drm->dev);
0198
0199     return ret;
0200 }
0201
0202 static const struct drm_mode_config_funcs hdlcd_mode_config_funcs = {
0203     .fb_create = drm_gem_fb_create,
0204     .atomic_check = drm_atomic_helper_check,
0205     .atomic_commit = drm_atomic_helper_commit,
0206 };
0207
0208 static void hdlcd_setup_mode_config(struct drm_device *drm)
0209 {
0210     drm_mode_config_init(drm);
0211     drm->mode_config.min_width = 0;
0212     drm->mode_config.min_height = 0;
0213     drm->mode_config.max_width = HDLCD_MAX_XRES;
0214     drm->mode_config.max_height = HDLCD_MAX_YRES;
0215     drm->mode_config.funcs = &hdlcd_mode_config_funcs;
0216 }
0217
0218 #ifdef CONFIG_DEBUG_FS
0219 static int hdlcd_show_underrun_count(struct seq_file *m, void *arg)
0220 {
0221     struct drm_info_node *node = (struct drm_info_node *)m->private;
0222     struct drm_device *drm = node->minor->dev;
0223     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0224
0225     seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
0226     seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
0227     seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
0228     seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
0229     return 0;
0230 }
0231
0232 static int hdlcd_show_pxlclock(struct seq_file *m, void *arg)
0233 {
0234     struct drm_info_node *node = (struct drm_info_node *)m->private;
0235     struct drm_device *drm = node->minor->dev;
0236     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0237     unsigned long clkrate = clk_get_rate(hdlcd->clk);
0238     unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
0239
0240     seq_printf(m, "hw  : %lu\n", clkrate);
0241     seq_printf(m, "mode: %lu\n", mode_clock);
0242     return 0;
0243 }
0244
0245 static struct drm_info_list hdlcd_debugfs_list[] = {
0246     { "interrupt_count", hdlcd_show_underrun_count, 0 },
0247     { "clocks", hdlcd_show_pxlclock, 0 },
0248 };
0249
0250 static void hdlcd_debugfs_init(struct drm_minor *minor)
0251 {
0252     drm_debugfs_create_files(hdlcd_debugfs_list,
0253                  ARRAY_SIZE(hdlcd_debugfs_list),
0254                  minor->debugfs_root, minor);
0255 }
0256 #endif
0257
0258 DEFINE_DRM_GEM_CMA_FOPS(fops);
0259
0260 static const struct drm_driver hdlcd_driver = {
0261     .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
0262     DRM_GEM_CMA_DRIVER_OPS,
0263 #ifdef CONFIG_DEBUG_FS
0264     .debugfs_init = hdlcd_debugfs_init,
0265 #endif
0266     .fops = &fops,
0267     .name = "hdlcd",
0268     .desc = "ARM HDLCD Controller DRM",
0269     .date = "20151021",
0270     .major = 1,
0271     .minor = 0,
0272 };
0273
0274 static int hdlcd_drm_bind(struct device *dev)
0275 {
0276     struct drm_device *drm;
0277     struct hdlcd_drm_private *hdlcd;
0278     int ret;
0279
0280     hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
0281     if (!hdlcd)
0282         return -ENOMEM;
0283
0284     drm = drm_dev_alloc(&hdlcd_driver, dev);
0285     if (IS_ERR(drm))
0286         return PTR_ERR(drm);
0287
0288     drm->dev_private = hdlcd;
0289     dev_set_drvdata(dev, drm);
0290
0291     hdlcd_setup_mode_config(drm);
0292     ret = hdlcd_load(drm, 0);
0293     if (ret)
0294         goto err_free;
0295
0296     /* Set the CRTC's port so that the encoder component can find it */
0297     hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
0298
0299     ret = component_bind_all(dev, drm);
0300     if (ret) {
0301         DRM_ERROR("Failed to bind all components\n");
0302         goto err_unload;
0303     }
0304
0305     ret = pm_runtime_set_active(dev);
0306     if (ret)
0307         goto err_pm_active;
0308
0309     pm_runtime_enable(dev);
0310
0311     ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
0312     if (ret < 0) {
0313         DRM_ERROR("failed to initialise vblank\n");
0314         goto err_vblank;
0315     }
0316
0317     drm_mode_config_reset(drm);
0318     drm_kms_helper_poll_init(drm);
0319
0320     ret = drm_dev_register(drm, 0);
0321     if (ret)
0322         goto err_register;
0323
0324     drm_fbdev_generic_setup(drm, 32);
0325
0326     return 0;
0327
0328 err_register:
0329     drm_kms_helper_poll_fini(drm);
0330 err_vblank:
0331     pm_runtime_disable(drm->dev);
0332 err_pm_active:
0333     drm_atomic_helper_shutdown(drm);
0334     component_unbind_all(dev, drm);
0335 err_unload:
0336     of_node_put(hdlcd->crtc.port);
0337     hdlcd->crtc.port = NULL;
0338     hdlcd_irq_uninstall(drm);
0339     of_reserved_mem_device_release(drm->dev);
0340 err_free:
0341     drm_mode_config_cleanup(drm);
0342     dev_set_drvdata(dev, NULL);
0343     drm_dev_put(drm);
0344
0345     return ret;
0346 }
0347
0348 static void hdlcd_drm_unbind(struct device *dev)
0349 {
0350     struct drm_device *drm = dev_get_drvdata(dev);
0351     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0352
0353     drm_dev_unregister(drm);
0354     drm_kms_helper_poll_fini(drm);
0355     component_unbind_all(dev, drm);
0356     of_node_put(hdlcd->crtc.port);
0357     hdlcd->crtc.port = NULL;
0358     pm_runtime_get_sync(dev);
0359     drm_atomic_helper_shutdown(drm);
0360     hdlcd_irq_uninstall(drm);
0361     pm_runtime_put(dev);
0362     if (pm_runtime_enabled(dev))
0363         pm_runtime_disable(dev);
0364     of_reserved_mem_device_release(dev);
0365     drm_mode_config_cleanup(drm);
0366     drm->dev_private = NULL;
0367     dev_set_drvdata(dev, NULL);
0368     drm_dev_put(drm);
0369 }
0370
0371 static const struct component_master_ops hdlcd_master_ops = {
0372     .bind       = hdlcd_drm_bind,
0373     .unbind     = hdlcd_drm_unbind,
0374 };
0375
0376 static int compare_dev(struct device *dev, void *data)
0377 {
0378     return dev->of_node == data;
0379 }
0380
0381 static int hdlcd_probe(struct platform_device *pdev)
0382 {
0383     struct device_node *port;
0384     struct component_match *match = NULL;
0385
0386     /* there is only one output port inside each device, find it */
0387     port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
0388     if (!port)
0389         return -ENODEV;
0390
0391     drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
0392     of_node_put(port);
0393
0394     return component_master_add_with_match(&pdev->dev, &hdlcd_master_ops,
0395                            match);
0396 }
0397
0398 static int hdlcd_remove(struct platform_device *pdev)
0399 {
0400     component_master_del(&pdev->dev, &hdlcd_master_ops);
0401     return 0;
0402 }
0403
0404 static const struct of_device_id  hdlcd_of_match[] = {
0405     { .compatible   = "arm,hdlcd" },
0406     {},
0407 };
0408 MODULE_DEVICE_TABLE(of, hdlcd_of_match);
0409
0410 static int __maybe_unused hdlcd_pm_suspend(struct device *dev)
0411 {
0412     struct drm_device *drm = dev_get_drvdata(dev);
0413
0414     return drm_mode_config_helper_suspend(drm);
0415 }
0416
0417 static int __maybe_unused hdlcd_pm_resume(struct device *dev)
0418 {
0419     struct drm_device *drm = dev_get_drvdata(dev);
0420
0421     drm_mode_config_helper_resume(drm);
0422
0423     return 0;
0424 }
0425
0426 static SIMPLE_DEV_PM_OPS(hdlcd_pm_ops, hdlcd_pm_suspend, hdlcd_pm_resume);
0427
0428 static struct platform_driver hdlcd_platform_driver = {
0429     .probe      = hdlcd_probe,
0430     .remove     = hdlcd_remove,
0431     .driver = {
0432         .name = "hdlcd",
0433         .pm = &hdlcd_pm_ops,
0434         .of_match_table = hdlcd_of_match,
0435     },
0436 };
0437
0438 drm_module_platform_driver(hdlcd_platform_driver);
0439
0440 MODULE_AUTHOR("Liviu Dudau");
0441 MODULE_DESCRIPTION("ARM HDLCD DRM driver");
0442 MODULE_LICENSE("GPL v2");