drm/arm/hdlcd_crtc.c

0001 /*
0002  * Copyright (C) 2013-2015 ARM Limited
0003  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
0004  *
0005  * This file is subject to the terms and conditions of the GNU General Public
0006  * License.  See the file COPYING in the main directory of this archive
0007  * for more details.
0008  *
0009  *  Implementation of a CRTC class for the HDLCD driver.
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/of_graph.h>
0014 #include <linux/platform_data/simplefb.h>
0015
0016 #include <video/videomode.h>
0017
0018 #include <drm/drm_atomic.h>
0019 #include <drm/drm_atomic_helper.h>
0020 #include <drm/drm_crtc.h>
0021 #include <drm/drm_fb_cma_helper.h>
0022 #include <drm/drm_fb_helper.h>
0023 #include <drm/drm_framebuffer.h>
0024 #include <drm/drm_gem_cma_helper.h>
0025 #include <drm/drm_of.h>
0026 #include <drm/drm_plane_helper.h>
0027 #include <drm/drm_probe_helper.h>
0028 #include <drm/drm_vblank.h>
0029
0030 #include "hdlcd_drv.h"
0031 #include "hdlcd_regs.h"
0032
0033 /*
0034  * The HDLCD controller is a dumb RGB streamer that gets connected to
0035  * a single HDMI transmitter or in the case of the ARM Models it gets
0036  * emulated by the software that does the actual rendering.
0037  *
0038  */
0039
0040 static void hdlcd_crtc_cleanup(struct drm_crtc *crtc)
0041 {
0042     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0043
0044     /* stop the controller on cleanup */
0045     hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
0046     drm_crtc_cleanup(crtc);
0047 }
0048
0049 static int hdlcd_crtc_enable_vblank(struct drm_crtc *crtc)
0050 {
0051     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0052     unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
0053
0054     hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
0055
0056     return 0;
0057 }
0058
0059 static void hdlcd_crtc_disable_vblank(struct drm_crtc *crtc)
0060 {
0061     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0062     unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
0063
0064     hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
0065 }
0066
0067 static const struct drm_crtc_funcs hdlcd_crtc_funcs = {
0068     .destroy = hdlcd_crtc_cleanup,
0069     .set_config = drm_atomic_helper_set_config,
0070     .page_flip = drm_atomic_helper_page_flip,
0071     .reset = drm_atomic_helper_crtc_reset,
0072     .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
0073     .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
0074     .enable_vblank = hdlcd_crtc_enable_vblank,
0075     .disable_vblank = hdlcd_crtc_disable_vblank,
0076 };
0077
0078 static struct simplefb_format supported_formats[] = SIMPLEFB_FORMATS;
0079
0080 /*
0081  * Setup the HDLCD registers for decoding the pixels out of the framebuffer
0082  */
0083 static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
0084 {
0085     unsigned int btpp;
0086     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0087     const struct drm_framebuffer *fb = crtc->primary->state->fb;
0088     uint32_t pixel_format;
0089     struct simplefb_format *format = NULL;
0090     int i;
0091
0092     pixel_format = fb->format->format;
0093
0094     for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
0095         if (supported_formats[i].fourcc == pixel_format)
0096             format = &supported_formats[i];
0097     }
0098
0099     if (WARN_ON(!format))
0100         return 0;
0101
0102     /* HDLCD uses 'bytes per pixel', zero means 1 byte */
0103     btpp = (format->bits_per_pixel + 7) / 8;
0104     hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
0105
0106     /*
0107      * The format of the HDLCD_REG_<color>_SELECT register is:
0108      *   - bits[23:16] - default value for that color component
0109      *   - bits[11:8]  - number of bits to extract for each color component
0110      *   - bits[4:0]   - index of the lowest bit to extract
0111      *
0112      * The default color value is used when bits[11:8] are zero, when the
0113      * pixel is outside the visible frame area or when there is a
0114      * buffer underrun.
0115      */
0116     hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
0117 #ifdef CONFIG_DRM_HDLCD_SHOW_UNDERRUN
0118             0x00ff0000 |    /* show underruns in red */
0119 #endif
0120             ((format->red.length & 0xf) << 8));
0121     hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
0122             ((format->green.length & 0xf) << 8));
0123     hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
0124             ((format->blue.length & 0xf) << 8));
0125
0126     return 0;
0127 }
0128
0129 static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
0130 {
0131     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0132     struct drm_display_mode *m = &crtc->state->adjusted_mode;
0133     struct videomode vm;
0134     unsigned int polarities, err;
0135
0136     vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
0137     vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
0138     vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
0139     vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
0140     vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
0141     vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
0142
0143     polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;
0144
0145     if (m->flags & DRM_MODE_FLAG_PHSYNC)
0146         polarities |= HDLCD_POLARITY_HSYNC;
0147     if (m->flags & DRM_MODE_FLAG_PVSYNC)
0148         polarities |= HDLCD_POLARITY_VSYNC;
0149
0150     /* Allow max number of outstanding requests and largest burst size */
0151     hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
0152             HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
0153
0154     hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
0155     hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
0156     hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
0157     hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
0158     hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
0159     hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
0160     hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
0161     hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
0162     hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
0163
0164     err = hdlcd_set_pxl_fmt(crtc);
0165     if (err)
0166         return;
0167
0168     clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
0169 }
0170
0171 static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
0172                      struct drm_atomic_state *state)
0173 {
0174     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0175
0176     clk_prepare_enable(hdlcd->clk);
0177     hdlcd_crtc_mode_set_nofb(crtc);
0178     hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
0179     drm_crtc_vblank_on(crtc);
0180 }
0181
0182 static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc,
0183                       struct drm_atomic_state *state)
0184 {
0185     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0186
0187     drm_crtc_vblank_off(crtc);
0188     hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
0189     clk_disable_unprepare(hdlcd->clk);
0190 }
0191
0192 static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc,
0193         const struct drm_display_mode *mode)
0194 {
0195     struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
0196     long rate, clk_rate = mode->clock * 1000;
0197
0198     rate = clk_round_rate(hdlcd->clk, clk_rate);
0199     /* 0.1% seems a close enough tolerance for the TDA19988 on Juno */
0200     if (abs(rate - clk_rate) * 1000 > clk_rate) {
0201         /* clock required by mode not supported by hardware */
0202         return MODE_NOCLOCK;
0203     }
0204
0205     return MODE_OK;
0206 }
0207
0208 static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc,
0209                     struct drm_atomic_state *state)
0210 {
0211     struct drm_pending_vblank_event *event = crtc->state->event;
0212
0213     if (event) {
0214         crtc->state->event = NULL;
0215
0216         spin_lock_irq(&crtc->dev->event_lock);
0217         if (drm_crtc_vblank_get(crtc) == 0)
0218             drm_crtc_arm_vblank_event(crtc, event);
0219         else
0220             drm_crtc_send_vblank_event(crtc, event);
0221         spin_unlock_irq(&crtc->dev->event_lock);
0222     }
0223 }
0224
0225 static const struct drm_crtc_helper_funcs hdlcd_crtc_helper_funcs = {
0226     .mode_valid = hdlcd_crtc_mode_valid,
0227     .atomic_begin   = hdlcd_crtc_atomic_begin,
0228     .atomic_enable  = hdlcd_crtc_atomic_enable,
0229     .atomic_disable = hdlcd_crtc_atomic_disable,
0230 };
0231
0232 static int hdlcd_plane_atomic_check(struct drm_plane *plane,
0233                     struct drm_atomic_state *state)
0234 {
0235     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0236                                          plane);
0237     int i;
0238     struct drm_crtc *crtc;
0239     struct drm_crtc_state *crtc_state;
0240     u32 src_h = new_plane_state->src_h >> 16;
0241
0242     /* only the HDLCD_REG_FB_LINE_COUNT register has a limit */
0243     if (src_h >= HDLCD_MAX_YRES) {
0244         DRM_DEBUG_KMS("Invalid source width: %d\n", src_h);
0245         return -EINVAL;
0246     }
0247
0248     for_each_new_crtc_in_state(state, crtc, crtc_state,
0249                    i) {
0250         /* we cannot disable the plane while the CRTC is active */
0251         if (!new_plane_state->fb && crtc_state->active)
0252             return -EINVAL;
0253         return drm_atomic_helper_check_plane_state(new_plane_state,
0254                                crtc_state,
0255                                DRM_PLANE_HELPER_NO_SCALING,
0256                                DRM_PLANE_HELPER_NO_SCALING,
0257                                false, true);
0258     }
0259
0260     return 0;
0261 }
0262
0263 static void hdlcd_plane_atomic_update(struct drm_plane *plane,
0264                       struct drm_atomic_state *state)
0265 {
0266     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0267                                          plane);
0268     struct drm_framebuffer *fb = new_plane_state->fb;
0269     struct hdlcd_drm_private *hdlcd;
0270     u32 dest_h;
0271     dma_addr_t scanout_start;
0272
0273     if (!fb)
0274         return;
0275
0276     dest_h = drm_rect_height(&new_plane_state->dst);
0277     scanout_start = drm_fb_cma_get_gem_addr(fb, new_plane_state, 0);
0278
0279     hdlcd = plane->dev->dev_private;
0280     hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
0281     hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
0282     hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
0283     hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
0284 }
0285
0286 static const struct drm_plane_helper_funcs hdlcd_plane_helper_funcs = {
0287     .atomic_check = hdlcd_plane_atomic_check,
0288     .atomic_update = hdlcd_plane_atomic_update,
0289 };
0290
0291 static const struct drm_plane_funcs hdlcd_plane_funcs = {
0292     .update_plane       = drm_atomic_helper_update_plane,
0293     .disable_plane      = drm_atomic_helper_disable_plane,
0294     .destroy        = drm_plane_cleanup,
0295     .reset          = drm_atomic_helper_plane_reset,
0296     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
0297     .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
0298 };
0299
0300 static struct drm_plane *hdlcd_plane_init(struct drm_device *drm)
0301 {
0302     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0303     struct drm_plane *plane = NULL;
0304     u32 formats[ARRAY_SIZE(supported_formats)], i;
0305     int ret;
0306
0307     plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
0308     if (!plane)
0309         return ERR_PTR(-ENOMEM);
0310
0311     for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
0312         formats[i] = supported_formats[i].fourcc;
0313
0314     ret = drm_universal_plane_init(drm, plane, 0xff, &hdlcd_plane_funcs,
0315                        formats, ARRAY_SIZE(formats),
0316                        NULL,
0317                        DRM_PLANE_TYPE_PRIMARY, NULL);
0318     if (ret)
0319         return ERR_PTR(ret);
0320
0321     drm_plane_helper_add(plane, &hdlcd_plane_helper_funcs);
0322     hdlcd->plane = plane;
0323
0324     return plane;
0325 }
0326
0327 int hdlcd_setup_crtc(struct drm_device *drm)
0328 {
0329     struct hdlcd_drm_private *hdlcd = drm->dev_private;
0330     struct drm_plane *primary;
0331     int ret;
0332
0333     primary = hdlcd_plane_init(drm);
0334     if (IS_ERR(primary))
0335         return PTR_ERR(primary);
0336
0337     ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
0338                     &hdlcd_crtc_funcs, NULL);
0339     if (ret)
0340         return ret;
0341
0342     drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
0343     return 0;
0344 }