display/komeda/komeda_pipeline.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
0004  * Author: James.Qian.Wang <james.qian.wang@arm.com>
0005  *
0006  */
0007 #ifndef _KOMEDA_PIPELINE_H_
0008 #define _KOMEDA_PIPELINE_H_
0009
0010 #include <linux/types.h>
0011 #include <drm/drm_atomic.h>
0012 #include <drm/drm_atomic_helper.h>
0013 #include "malidp_utils.h"
0014 #include "komeda_color_mgmt.h"
0015
0016 #define KOMEDA_MAX_PIPELINES        2
0017 #define KOMEDA_PIPELINE_MAX_LAYERS  4
0018 #define KOMEDA_PIPELINE_MAX_SCALERS 2
0019 #define KOMEDA_COMPONENT_N_INPUTS   5
0020
0021 /* pipeline component IDs */
0022 enum {
0023     KOMEDA_COMPONENT_LAYER0     = 0,
0024     KOMEDA_COMPONENT_LAYER1     = 1,
0025     KOMEDA_COMPONENT_LAYER2     = 2,
0026     KOMEDA_COMPONENT_LAYER3     = 3,
0027     KOMEDA_COMPONENT_WB_LAYER   = 7, /* write back layer */
0028     KOMEDA_COMPONENT_SCALER0    = 8,
0029     KOMEDA_COMPONENT_SCALER1    = 9,
0030     KOMEDA_COMPONENT_SPLITTER   = 12,
0031     KOMEDA_COMPONENT_MERGER     = 14,
0032     KOMEDA_COMPONENT_COMPIZ0    = 16, /* compositor */
0033     KOMEDA_COMPONENT_COMPIZ1    = 17,
0034     KOMEDA_COMPONENT_IPS0       = 20, /* post image processor */
0035     KOMEDA_COMPONENT_IPS1       = 21,
0036     KOMEDA_COMPONENT_TIMING_CTRLR   = 22, /* timing controller */
0037 };
0038
0039 #define KOMEDA_PIPELINE_LAYERS      (BIT(KOMEDA_COMPONENT_LAYER0) |\
0040                      BIT(KOMEDA_COMPONENT_LAYER1) |\
0041                      BIT(KOMEDA_COMPONENT_LAYER2) |\
0042                      BIT(KOMEDA_COMPONENT_LAYER3))
0043
0044 #define KOMEDA_PIPELINE_SCALERS     (BIT(KOMEDA_COMPONENT_SCALER0) |\
0045                      BIT(KOMEDA_COMPONENT_SCALER1))
0046
0047 #define KOMEDA_PIPELINE_COMPIZS     (BIT(KOMEDA_COMPONENT_COMPIZ0) |\
0048                      BIT(KOMEDA_COMPONENT_COMPIZ1))
0049
0050 #define KOMEDA_PIPELINE_IMPROCS     (BIT(KOMEDA_COMPONENT_IPS0) |\
0051                      BIT(KOMEDA_COMPONENT_IPS1))
0052 struct komeda_component;
0053 struct komeda_component_state;
0054
0055 /** komeda_component_funcs - component control functions */
0056 struct komeda_component_funcs {
0057     /** @validate: optional,
0058      * component may has special requirements or limitations, this function
0059      * supply HW the ability to do the further HW specific check.
0060      */
0061     int (*validate)(struct komeda_component *c,
0062             struct komeda_component_state *state);
0063     /** @update: update is a active update */
0064     void (*update)(struct komeda_component *c,
0065                struct komeda_component_state *state);
0066     /** @disable: disable component */
0067     void (*disable)(struct komeda_component *c);
0068     /** @dump_register: Optional, dump registers to seq_file */
0069     void (*dump_register)(struct komeda_component *c, struct seq_file *seq);
0070 };
0071
0072 /**
0073  * struct komeda_component
0074  *
0075  * struct komeda_component describe the data flow capabilities for how to link a
0076  * component into the display pipeline.
0077  * all specified components are subclass of this structure.
0078  */
0079 struct komeda_component {
0080     /** @obj: treat component as private obj */
0081     struct drm_private_obj obj;
0082     /** @pipeline: the komeda pipeline this component belongs to */
0083     struct komeda_pipeline *pipeline;
0084     /** @name: component name */
0085     char name[32];
0086     /**
0087      * @reg:
0088      * component register base,
0089      * which is initialized by chip and used by chip only
0090      */
0091     u32 __iomem *reg;
0092     /** @id: component id */
0093     u32 id;
0094     /**
0095      * @hw_id: component hw id,
0096      * which is initialized by chip and used by chip only
0097      */
0098     u32 hw_id;
0099
0100     /**
0101      * @max_active_inputs:
0102      * @max_active_outputs:
0103      *
0104      * maximum number of inputs/outputs that can be active at the same time
0105      * Note:
0106      * the number isn't the bit number of @supported_inputs or
0107      * @supported_outputs, but may be less than it, since component may not
0108      * support enabling all @supported_inputs/outputs at the same time.
0109      */
0110     u8 max_active_inputs;
0111     /** @max_active_outputs: maximum number of outputs */
0112     u8 max_active_outputs;
0113     /**
0114      * @supported_inputs:
0115      * @supported_outputs:
0116      *
0117      * bitmask of BIT(component->id) for the supported inputs/outputs,
0118      * describes the possibilities of how a component is linked into a
0119      * pipeline.
0120      */
0121     u32 supported_inputs;
0122     /** @supported_outputs: bitmask of supported output componenet ids */
0123     u32 supported_outputs;
0124
0125     /**
0126      * @funcs: chip functions to access HW
0127      */
0128     const struct komeda_component_funcs *funcs;
0129 };
0130
0131 /**
0132  * struct komeda_component_output
0133  *
0134  * a component has multiple outputs, if want to know where the data
0135  * comes from, only know the component is not enough, we still need to know
0136  * its output port
0137  */
0138 struct komeda_component_output {
0139     /** @component: indicate which component the data comes from */
0140     struct komeda_component *component;
0141     /**
0142      * @output_port:
0143      * the output port of the &komeda_component_output.component
0144      */
0145     u8 output_port;
0146 };
0147
0148 /**
0149  * struct komeda_component_state
0150  *
0151  * component_state is the data flow configuration of the component, and it's
0152  * the superclass of all specific component_state like @komeda_layer_state,
0153  * @komeda_scaler_state
0154  */
0155 struct komeda_component_state {
0156     /** @obj: tracking component_state by drm_atomic_state */
0157     struct drm_private_state obj;
0158     /** @component: backpointer to the component */
0159     struct komeda_component *component;
0160     /**
0161      * @binding_user:
0162      * currently bound user, the user can be @crtc, @plane or @wb_conn,
0163      * which is valid decided by @component and @inputs
0164      *
0165      * -  Layer: its user always is plane.
0166      * -  compiz/improc/timing_ctrlr: the user is crtc.
0167      * -  wb_layer: wb_conn;
0168      * -  scaler: plane when input is layer, wb_conn if input is compiz.
0169      */
0170     union {
0171         /** @crtc: backpointer for user crtc */
0172         struct drm_crtc *crtc;
0173         /** @plane: backpointer for user plane */
0174         struct drm_plane *plane;
0175         /** @wb_conn: backpointer for user wb_connector  */
0176         struct drm_connector *wb_conn;
0177         void *binding_user;
0178     };
0179
0180     /**
0181      * @active_inputs:
0182      *
0183      * active_inputs is bitmask of @inputs index
0184      *
0185      * -  active_inputs = changed_active_inputs | unchanged_active_inputs
0186      * -  affected_inputs = old->active_inputs | new->active_inputs;
0187      * -  disabling_inputs = affected_inputs ^ active_inputs;
0188      * -  changed_inputs = disabling_inputs | changed_active_inputs;
0189      *
0190      * NOTE:
0191      * changed_inputs doesn't include all active_input but only
0192      * @changed_active_inputs, and this bitmask can be used in chip
0193      * level for dirty update.
0194      */
0195     u16 active_inputs;
0196     /** @changed_active_inputs: bitmask of the changed @active_inputs */
0197     u16 changed_active_inputs;
0198     /** @affected_inputs: bitmask for affected @inputs */
0199     u16 affected_inputs;
0200     /**
0201      * @inputs:
0202      *
0203      * the specific inputs[i] only valid on BIT(i) has been set in
0204      * @active_inputs, if not the inputs[i] is undefined.
0205      */
0206     struct komeda_component_output inputs[KOMEDA_COMPONENT_N_INPUTS];
0207 };
0208
0209 static inline u16 component_disabling_inputs(struct komeda_component_state *st)
0210 {
0211     return st->affected_inputs ^ st->active_inputs;
0212 }
0213
0214 static inline u16 component_changed_inputs(struct komeda_component_state *st)
0215 {
0216     return component_disabling_inputs(st) | st->changed_active_inputs;
0217 }
0218
0219 #define for_each_changed_input(st, i)   \
0220     for ((i) = 0; (i) < (st)->component->max_active_inputs; (i)++)  \
0221         if (has_bit((i), component_changed_inputs(st)))
0222
0223 #define to_comp(__c)    (((__c) == NULL) ? NULL : &((__c)->base))
0224 #define to_cpos(__c)    ((struct komeda_component **)&(__c))
0225
0226 struct komeda_layer {
0227     struct komeda_component base;
0228     /* accepted h/v input range before rotation */
0229     struct malidp_range hsize_in, vsize_in;
0230     u32 layer_type; /* RICH, SIMPLE or WB */
0231     u32 line_sz;
0232     u32 yuv_line_sz; /* maximum line size for YUV422 and YUV420 */
0233     u32 supported_rots;
0234     /* komeda supports layer split which splits a whole image to two parts
0235      * left and right and handle them by two individual layer processors
0236      * Note: left/right are always according to the final display rect,
0237      * not the source buffer.
0238      */
0239     struct komeda_layer *right;
0240 };
0241
0242 struct komeda_layer_state {
0243     struct komeda_component_state base;
0244     /* layer specific configuration state */
0245     u16 hsize, vsize;
0246     u32 rot;
0247     u16 afbc_crop_l;
0248     u16 afbc_crop_r;
0249     u16 afbc_crop_t;
0250     u16 afbc_crop_b;
0251     dma_addr_t addr[3];
0252 };
0253
0254 struct komeda_scaler {
0255     struct komeda_component base;
0256     struct malidp_range hsize, vsize;
0257     u32 max_upscaling;
0258     u32 max_downscaling;
0259     u8 scaling_split_overlap; /* split overlap for scaling */
0260     u8 enh_split_overlap; /* split overlap for image enhancement */
0261 };
0262
0263 struct komeda_scaler_state {
0264     struct komeda_component_state base;
0265     u16 hsize_in, vsize_in;
0266     u16 hsize_out, vsize_out;
0267     u16 total_hsize_in, total_vsize_in;
0268     u16 total_hsize_out; /* total_xxxx are size before split */
0269     u16 left_crop, right_crop;
0270     u8 en_scaling : 1,
0271        en_alpha : 1, /* enable alpha processing */
0272        en_img_enhancement : 1,
0273        en_split : 1,
0274        right_part : 1; /* right part of split image */
0275 };
0276
0277 struct komeda_compiz {
0278     struct komeda_component base;
0279     struct malidp_range hsize, vsize;
0280 };
0281
0282 struct komeda_compiz_input_cfg {
0283     u16 hsize, vsize;
0284     u16 hoffset, voffset;
0285     u8 pixel_blend_mode, layer_alpha;
0286 };
0287
0288 struct komeda_compiz_state {
0289     struct komeda_component_state base;
0290     /* composition size */
0291     u16 hsize, vsize;
0292     struct komeda_compiz_input_cfg cins[KOMEDA_COMPONENT_N_INPUTS];
0293 };
0294
0295 struct komeda_merger {
0296     struct komeda_component base;
0297     struct malidp_range hsize_merged;
0298     struct malidp_range vsize_merged;
0299 };
0300
0301 struct komeda_merger_state {
0302     struct komeda_component_state base;
0303     u16 hsize_merged;
0304     u16 vsize_merged;
0305 };
0306
0307 struct komeda_splitter {
0308     struct komeda_component base;
0309     struct malidp_range hsize, vsize;
0310 };
0311
0312 struct komeda_splitter_state {
0313     struct komeda_component_state base;
0314     u16 hsize, vsize;
0315     u16 overlap;
0316 };
0317
0318 struct komeda_improc {
0319     struct komeda_component base;
0320     u32 supported_color_formats;  /* DRM_RGB/YUV444/YUV420*/
0321     u32 supported_color_depths; /* BIT(8) | BIT(10)*/
0322     u8 supports_degamma : 1;
0323     u8 supports_csc : 1;
0324     u8 supports_gamma : 1;
0325 };
0326
0327 struct komeda_improc_state {
0328     struct komeda_component_state base;
0329     u8 color_format, color_depth;
0330     u16 hsize, vsize;
0331     u32 fgamma_coeffs[KOMEDA_N_GAMMA_COEFFS];
0332     u32 ctm_coeffs[KOMEDA_N_CTM_COEFFS];
0333 };
0334
0335 /* display timing controller */
0336 struct komeda_timing_ctrlr {
0337     struct komeda_component base;
0338     u8 supports_dual_link : 1;
0339 };
0340
0341 struct komeda_timing_ctrlr_state {
0342     struct komeda_component_state base;
0343 };
0344
0345 /* Why define A separated structure but not use plane_state directly ?
0346  * 1. Komeda supports layer_split which means a plane_state can be split and
0347  *    handled by two layers, one layer only handle half of plane image.
0348  * 2. Fix up the user properties according to HW's capabilities, like user
0349  *    set rotation to R180, but HW only supports REFLECT_X+Y. the rot here is
0350  *    after drm_rotation_simplify()
0351  */
0352 struct komeda_data_flow_cfg {
0353     struct komeda_component_output input;
0354     u16 in_x, in_y, in_w, in_h;
0355     u32 out_x, out_y, out_w, out_h;
0356     u16 total_in_h, total_in_w;
0357     u16 total_out_w;
0358     u16 left_crop, right_crop, overlap;
0359     u32 rot;
0360     int blending_zorder;
0361     u8 pixel_blend_mode, layer_alpha;
0362     u8 en_scaling : 1,
0363        en_img_enhancement : 1,
0364        en_split : 1,
0365        is_yuv : 1,
0366        right_part : 1; /* right part of display image if split enabled */
0367 };
0368
0369 struct komeda_pipeline_funcs {
0370     /* check if the aclk (main engine clock) can satisfy the clock
0371      * requirements of the downscaling that specified by dflow
0372      */
0373     int (*downscaling_clk_check)(struct komeda_pipeline *pipe,
0374                      struct drm_display_mode *mode,
0375                      unsigned long aclk_rate,
0376                      struct komeda_data_flow_cfg *dflow);
0377     /* dump_register: Optional, dump registers to seq_file */
0378     void (*dump_register)(struct komeda_pipeline *pipe,
0379                   struct seq_file *sf);
0380 };
0381
0382 /**
0383  * struct komeda_pipeline
0384  *
0385  * Represent a complete display pipeline and hold all functional components.
0386  */
0387 struct komeda_pipeline {
0388     /** @obj: link pipeline as private obj of drm_atomic_state */
0389     struct drm_private_obj obj;
0390     /** @mdev: the parent komeda_dev */
0391     struct komeda_dev *mdev;
0392     /** @pxlclk: pixel clock */
0393     struct clk *pxlclk;
0394     /** @id: pipeline id */
0395     int id;
0396     /** @avail_comps: available components mask of pipeline */
0397     u32 avail_comps;
0398     /**
0399      * @standalone_disabled_comps:
0400      *
0401      * When disable the pipeline, some components can not be disabled
0402      * together with others, but need a sparated and standalone disable.
0403      * The standalone_disabled_comps are the components which need to be
0404      * disabled standalone, and this concept also introduce concept of
0405      * two phase.
0406      * phase 1: for disabling the common components.
0407      * phase 2: for disabling the standalong_disabled_comps.
0408      */
0409     u32 standalone_disabled_comps;
0410     /** @n_layers: the number of layer on @layers */
0411     int n_layers;
0412     /** @layers: the pipeline layers */
0413     struct komeda_layer *layers[KOMEDA_PIPELINE_MAX_LAYERS];
0414     /** @n_scalers: the number of scaler on @scalers */
0415     int n_scalers;
0416     /** @scalers: the pipeline scalers */
0417     struct komeda_scaler *scalers[KOMEDA_PIPELINE_MAX_SCALERS];
0418     /** @compiz: compositor */
0419     struct komeda_compiz *compiz;
0420     /** @splitter: for split the compiz output to two half data flows */
0421     struct komeda_splitter *splitter;
0422     /** @merger: merger */
0423     struct komeda_merger *merger;
0424     /** @wb_layer: writeback layer */
0425     struct komeda_layer  *wb_layer;
0426     /** @improc: post image processor */
0427     struct komeda_improc *improc;
0428     /** @ctrlr: timing controller */
0429     struct komeda_timing_ctrlr *ctrlr;
0430     /** @funcs: chip private pipeline functions */
0431     const struct komeda_pipeline_funcs *funcs;
0432
0433     /** @of_node: pipeline dt node */
0434     struct device_node *of_node;
0435     /** @of_output_port: pipeline output port */
0436     struct device_node *of_output_port;
0437     /** @of_output_links: output connector device nodes */
0438     struct device_node *of_output_links[2];
0439     /** @dual_link: true if of_output_links[0] and [1] are both valid */
0440     bool dual_link;
0441 };
0442
0443 /**
0444  * struct komeda_pipeline_state
0445  *
0446  * NOTE:
0447  * Unlike the pipeline, pipeline_state doesn’t gather any component_state
0448  * into it. It because all component will be managed by drm_atomic_state.
0449  */
0450 struct komeda_pipeline_state {
0451     /** @obj: tracking pipeline_state by drm_atomic_state */
0452     struct drm_private_state obj;
0453     /** @pipe: backpointer to the pipeline */
0454     struct komeda_pipeline *pipe;
0455     /** @crtc: currently bound crtc */
0456     struct drm_crtc *crtc;
0457     /**
0458      * @active_comps:
0459      *
0460      * bitmask - BIT(component->id) of active components
0461      */
0462     u32 active_comps;
0463 };
0464
0465 #define to_layer(c) container_of(c, struct komeda_layer, base)
0466 #define to_compiz(c)    container_of(c, struct komeda_compiz, base)
0467 #define to_scaler(c)    container_of(c, struct komeda_scaler, base)
0468 #define to_splitter(c)  container_of(c, struct komeda_splitter, base)
0469 #define to_merger(c)    container_of(c, struct komeda_merger, base)
0470 #define to_improc(c)    container_of(c, struct komeda_improc, base)
0471 #define to_ctrlr(c) container_of(c, struct komeda_timing_ctrlr, base)
0472
0473 #define to_layer_st(c)  container_of(c, struct komeda_layer_state, base)
0474 #define to_compiz_st(c) container_of(c, struct komeda_compiz_state, base)
0475 #define to_scaler_st(c) container_of(c, struct komeda_scaler_state, base)
0476 #define to_splitter_st(c) container_of(c, struct komeda_splitter_state, base)
0477 #define to_merger_st(c) container_of(c, struct komeda_merger_state, base)
0478 #define to_improc_st(c) container_of(c, struct komeda_improc_state, base)
0479 #define to_ctrlr_st(c)  container_of(c, struct komeda_timing_ctrlr_state, base)
0480
0481 #define priv_to_comp_st(o) container_of(o, struct komeda_component_state, obj)
0482 #define priv_to_pipe_st(o) container_of(o, struct komeda_pipeline_state, obj)
0483
0484 /* pipeline APIs */
0485 struct komeda_pipeline *
0486 komeda_pipeline_add(struct komeda_dev *mdev, size_t size,
0487             const struct komeda_pipeline_funcs *funcs);
0488 void komeda_pipeline_destroy(struct komeda_dev *mdev,
0489                  struct komeda_pipeline *pipe);
0490 struct komeda_pipeline *
0491 komeda_pipeline_get_slave(struct komeda_pipeline *master);
0492 int komeda_assemble_pipelines(struct komeda_dev *mdev);
0493 struct komeda_component *
0494 komeda_pipeline_get_component(struct komeda_pipeline *pipe, int id);
0495 struct komeda_component *
0496 komeda_pipeline_get_first_component(struct komeda_pipeline *pipe,
0497                     u32 comp_mask);
0498
0499 void komeda_pipeline_dump_register(struct komeda_pipeline *pipe,
0500                    struct seq_file *sf);
0501
0502 /* component APIs */
0503 extern __printf(10, 11)
0504 struct komeda_component *
0505 komeda_component_add(struct komeda_pipeline *pipe,
0506              size_t comp_sz, u32 id, u32 hw_id,
0507              const struct komeda_component_funcs *funcs,
0508              u8 max_active_inputs, u32 supported_inputs,
0509              u8 max_active_outputs, u32 __iomem *reg,
0510              const char *name_fmt, ...);
0511
0512 void komeda_component_destroy(struct komeda_dev *mdev,
0513                   struct komeda_component *c);
0514
0515 static inline struct komeda_component *
0516 komeda_component_pickup_output(struct komeda_component *c, u32 avail_comps)
0517 {
0518     u32 avail_inputs = c->supported_outputs & (avail_comps);
0519
0520     return komeda_pipeline_get_first_component(c->pipeline, avail_inputs);
0521 }
0522
0523 struct komeda_plane_state;
0524 struct komeda_crtc_state;
0525 struct komeda_crtc;
0526
0527 void pipeline_composition_size(struct komeda_crtc_state *kcrtc_st,
0528                    u16 *hsize, u16 *vsize);
0529
0530 int komeda_build_layer_data_flow(struct komeda_layer *layer,
0531                  struct komeda_plane_state *kplane_st,
0532                  struct komeda_crtc_state *kcrtc_st,
0533                  struct komeda_data_flow_cfg *dflow);
0534 int komeda_build_wb_data_flow(struct komeda_layer *wb_layer,
0535                   struct drm_connector_state *conn_st,
0536                   struct komeda_crtc_state *kcrtc_st,
0537                   struct komeda_data_flow_cfg *dflow);
0538 int komeda_build_display_data_flow(struct komeda_crtc *kcrtc,
0539                    struct komeda_crtc_state *kcrtc_st);
0540
0541 int komeda_build_layer_split_data_flow(struct komeda_layer *left,
0542                        struct komeda_plane_state *kplane_st,
0543                        struct komeda_crtc_state *kcrtc_st,
0544                        struct komeda_data_flow_cfg *dflow);
0545 int komeda_build_wb_split_data_flow(struct komeda_layer *wb_layer,
0546                     struct drm_connector_state *conn_st,
0547                     struct komeda_crtc_state *kcrtc_st,
0548                     struct komeda_data_flow_cfg *dflow);
0549
0550 int komeda_release_unclaimed_resources(struct komeda_pipeline *pipe,
0551                        struct komeda_crtc_state *kcrtc_st);
0552
0553 struct komeda_pipeline_state *
0554 komeda_pipeline_get_old_state(struct komeda_pipeline *pipe,
0555                   struct drm_atomic_state *state);
0556 bool komeda_pipeline_disable(struct komeda_pipeline *pipe,
0557                  struct drm_atomic_state *old_state);
0558 void komeda_pipeline_update(struct komeda_pipeline *pipe,
0559                 struct drm_atomic_state *old_state);
0560
0561 void komeda_complete_data_flow_cfg(struct komeda_layer *layer,
0562                    struct komeda_data_flow_cfg *dflow,
0563                    struct drm_framebuffer *fb);
0564
0565 #endif /* _KOMEDA_PIPELINE_H_*/