display/komeda/komeda_dev.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
0004  * Author: James.Qian.Wang <james.qian.wang@arm.com>
0005  *
0006  */
0007 #ifndef _KOMEDA_DEV_H_
0008 #define _KOMEDA_DEV_H_
0009
0010 #include <linux/device.h>
0011 #include <linux/clk.h>
0012 #include "komeda_pipeline.h"
0013 #include "malidp_product.h"
0014 #include "komeda_format_caps.h"
0015
0016 #define KOMEDA_EVENT_VSYNC      BIT_ULL(0)
0017 #define KOMEDA_EVENT_FLIP       BIT_ULL(1)
0018 #define KOMEDA_EVENT_URUN       BIT_ULL(2)
0019 #define KOMEDA_EVENT_IBSY       BIT_ULL(3)
0020 #define KOMEDA_EVENT_OVR        BIT_ULL(4)
0021 #define KOMEDA_EVENT_EOW        BIT_ULL(5)
0022 #define KOMEDA_EVENT_MODE       BIT_ULL(6)
0023 #define KOMEDA_EVENT_FULL       BIT_ULL(7)
0024 #define KOMEDA_EVENT_EMPTY      BIT_ULL(8)
0025
0026 #define KOMEDA_ERR_TETO         BIT_ULL(14)
0027 #define KOMEDA_ERR_TEMR         BIT_ULL(15)
0028 #define KOMEDA_ERR_TITR         BIT_ULL(16)
0029 #define KOMEDA_ERR_CPE          BIT_ULL(17)
0030 #define KOMEDA_ERR_CFGE         BIT_ULL(18)
0031 #define KOMEDA_ERR_AXIE         BIT_ULL(19)
0032 #define KOMEDA_ERR_ACE0         BIT_ULL(20)
0033 #define KOMEDA_ERR_ACE1         BIT_ULL(21)
0034 #define KOMEDA_ERR_ACE2         BIT_ULL(22)
0035 #define KOMEDA_ERR_ACE3         BIT_ULL(23)
0036 #define KOMEDA_ERR_DRIFTTO      BIT_ULL(24)
0037 #define KOMEDA_ERR_FRAMETO      BIT_ULL(25)
0038 #define KOMEDA_ERR_CSCE         BIT_ULL(26)
0039 #define KOMEDA_ERR_ZME          BIT_ULL(27)
0040 #define KOMEDA_ERR_MERR         BIT_ULL(28)
0041 #define KOMEDA_ERR_TCF          BIT_ULL(29)
0042 #define KOMEDA_ERR_TTNG         BIT_ULL(30)
0043 #define KOMEDA_ERR_TTF          BIT_ULL(31)
0044
0045 #define KOMEDA_ERR_EVENTS   \
0046     (KOMEDA_EVENT_URUN  | KOMEDA_EVENT_IBSY | KOMEDA_EVENT_OVR |\
0047     KOMEDA_ERR_TETO     | KOMEDA_ERR_TEMR   | KOMEDA_ERR_TITR |\
0048     KOMEDA_ERR_CPE      | KOMEDA_ERR_CFGE   | KOMEDA_ERR_AXIE |\
0049     KOMEDA_ERR_ACE0     | KOMEDA_ERR_ACE1   | KOMEDA_ERR_ACE2 |\
0050     KOMEDA_ERR_ACE3     | KOMEDA_ERR_DRIFTTO    | KOMEDA_ERR_FRAMETO |\
0051     KOMEDA_ERR_ZME      | KOMEDA_ERR_MERR   | KOMEDA_ERR_TCF |\
0052     KOMEDA_ERR_TTNG     | KOMEDA_ERR_TTF)
0053
0054 #define KOMEDA_WARN_EVENTS  \
0055     (KOMEDA_ERR_CSCE | KOMEDA_EVENT_FULL | KOMEDA_EVENT_EMPTY)
0056
0057 #define KOMEDA_INFO_EVENTS (0 \
0058                 | KOMEDA_EVENT_VSYNC \
0059                 | KOMEDA_EVENT_FLIP \
0060                 | KOMEDA_EVENT_EOW \
0061                 | KOMEDA_EVENT_MODE \
0062                 )
0063
0064 /* pipeline DT ports */
0065 enum {
0066     KOMEDA_OF_PORT_OUTPUT       = 0,
0067     KOMEDA_OF_PORT_COPROC       = 1,
0068 };
0069
0070 struct komeda_chip_info {
0071     u32 arch_id;
0072     u32 core_id;
0073     u32 core_info;
0074     u32 bus_width;
0075 };
0076
0077 struct komeda_dev;
0078
0079 struct komeda_events {
0080     u64 global;
0081     u64 pipes[KOMEDA_MAX_PIPELINES];
0082 };
0083
0084 /**
0085  * struct komeda_dev_funcs
0086  *
0087  * Supplied by chip level and returned by the chip entry function xxx_identify,
0088  */
0089 struct komeda_dev_funcs {
0090     /**
0091      * @init_format_table:
0092      *
0093      * initialize &komeda_dev->format_table, this function should be called
0094      * before the &enum_resource
0095      */
0096     void (*init_format_table)(struct komeda_dev *mdev);
0097     /**
0098      * @enum_resources:
0099      *
0100      * for CHIP to report or add pipeline and component resources to CORE
0101      */
0102     int (*enum_resources)(struct komeda_dev *mdev);
0103     /** @cleanup: call to chip to cleanup komeda_dev->chip data */
0104     void (*cleanup)(struct komeda_dev *mdev);
0105     /** @connect_iommu: Optional, connect to external iommu */
0106     int (*connect_iommu)(struct komeda_dev *mdev);
0107     /** @disconnect_iommu: Optional, disconnect to external iommu */
0108     int (*disconnect_iommu)(struct komeda_dev *mdev);
0109     /**
0110      * @irq_handler:
0111      *
0112      * for CORE to get the HW event from the CHIP when interrupt happened.
0113      */
0114     irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
0115                    struct komeda_events *events);
0116     /** @enable_irq: enable irq */
0117     int (*enable_irq)(struct komeda_dev *mdev);
0118     /** @disable_irq: disable irq */
0119     int (*disable_irq)(struct komeda_dev *mdev);
0120     /** @on_off_vblank: notify HW to on/off vblank */
0121     void (*on_off_vblank)(struct komeda_dev *mdev,
0122                   int master_pipe, bool on);
0123
0124     /** @dump_register: Optional, dump registers to seq_file */
0125     void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
0126     /**
0127      * @change_opmode:
0128      *
0129      * Notify HW to switch to a new display operation mode.
0130      */
0131     int (*change_opmode)(struct komeda_dev *mdev, int new_mode);
0132     /** @flush: Notify the HW to flush or kickoff the update */
0133     void (*flush)(struct komeda_dev *mdev,
0134               int master_pipe, u32 active_pipes);
0135 };
0136
0137 /*
0138  * DISPLAY_MODE describes how many display been enabled, and which will be
0139  * passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
0140  * pipeline resources assignment according to this usage hint.
0141  * -   KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
0142  * -   KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
0143  * -   KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
0144  * And D71 supports assign two pipelines to one single display on mode
0145  * KOMEDA_MODE_DISP0/DISP1
0146  */
0147 enum {
0148     KOMEDA_MODE_INACTIVE    = 0,
0149     KOMEDA_MODE_DISP0   = BIT(0),
0150     KOMEDA_MODE_DISP1   = BIT(1),
0151     KOMEDA_MODE_DUAL_DISP   = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,
0152 };
0153
0154 /**
0155  * struct komeda_dev
0156  *
0157  * Pipeline and component are used to describe how to handle the pixel data.
0158  * komeda_device is for describing the whole view of the device, and the
0159  * control-abilites of device.
0160  */
0161 struct komeda_dev {
0162     /** @dev: the base device structure */
0163     struct device *dev;
0164     /** @reg_base: the base address of komeda io space */
0165     u32 __iomem   *reg_base;
0166
0167     /** @chip: the basic chip information */
0168     struct komeda_chip_info chip;
0169     /** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
0170     struct komeda_format_caps_table fmt_tbl;
0171     /** @aclk: HW main engine clk */
0172     struct clk *aclk;
0173
0174     /** @irq: irq number */
0175     int irq;
0176
0177     /** @lock: used to protect dpmode */
0178     struct mutex lock;
0179     /** @dpmode: current display mode */
0180     u32 dpmode;
0181
0182     /** @n_pipelines: the number of pipe in @pipelines */
0183     int n_pipelines;
0184     /** @pipelines: the komeda pipelines */
0185     struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
0186
0187     /** @funcs: chip funcs to access to HW */
0188     const struct komeda_dev_funcs *funcs;
0189     /**
0190      * @chip_data:
0191      *
0192      * chip data will be added by &komeda_dev_funcs.enum_resources() and
0193      * destroyed by &komeda_dev_funcs.cleanup()
0194      */
0195     void *chip_data;
0196
0197     /** @iommu: iommu domain */
0198     struct iommu_domain *iommu;
0199
0200     /** @debugfs_root: root directory of komeda debugfs */
0201     struct dentry *debugfs_root;
0202     /**
0203      * @err_verbosity: bitmask for how much extra info to print on error
0204      *
0205      * See KOMEDA_DEV_* macros for details. Low byte contains the debug
0206      * level categories, the high byte contains extra debug options.
0207      */
0208     u16 err_verbosity;
0209     /* Print a single line per error per frame with error events. */
0210 #define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0)
0211     /* Print a single line per warning per frame with error events. */
0212 #define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1)
0213     /* Print a single line per info event per frame with error events. */
0214 #define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2)
0215     /* Dump DRM state on an error or warning event. */
0216 #define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8)
0217     /* Disable rate limiting of event prints (normally one per commit) */
0218 #define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12)
0219 };
0220
0221 static inline bool
0222 komeda_product_match(struct komeda_dev *mdev, u32 target)
0223 {
0224     return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
0225 }
0226
0227 typedef const struct komeda_dev_funcs *
0228 (*komeda_identify_func)(u32 __iomem *reg, struct komeda_chip_info *chip);
0229
0230 const struct komeda_dev_funcs *
0231 d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
0232
0233 struct komeda_dev *komeda_dev_create(struct device *dev);
0234 void komeda_dev_destroy(struct komeda_dev *mdev);
0235
0236 struct komeda_dev *dev_to_mdev(struct device *dev);
0237
0238 void komeda_print_events(struct komeda_events *evts, struct drm_device *dev);
0239
0240 int komeda_dev_resume(struct komeda_dev *mdev);
0241 int komeda_dev_suspend(struct komeda_dev *mdev);
0242
0243 #endif /*_KOMEDA_DEV_H_*/