display/komeda/komeda_crtc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
0004  * Author: James.Qian.Wang <james.qian.wang@arm.com>
0005  *
0006  */
0007 #include <linux/clk.h>
0008 #include <linux/pm_runtime.h>
0009 #include <linux/spinlock.h>
0010
0011 #include <drm/drm_atomic.h>
0012 #include <drm/drm_atomic_helper.h>
0013 #include <drm/drm_crtc_helper.h>
0014 #include <drm/drm_plane_helper.h>
0015 #include <drm/drm_print.h>
0016 #include <drm/drm_vblank.h>
0017
0018 #include "komeda_dev.h"
0019 #include "komeda_kms.h"
0020
0021 void komeda_crtc_get_color_config(struct drm_crtc_state *crtc_st,
0022                   u32 *color_depths, u32 *color_formats)
0023 {
0024     struct drm_connector *conn;
0025     struct drm_connector_state *conn_st;
0026     u32 conn_color_formats = ~0u;
0027     int i, min_bpc = 31, conn_bpc = 0;
0028
0029     for_each_new_connector_in_state(crtc_st->state, conn, conn_st, i) {
0030         if (conn_st->crtc != crtc_st->crtc)
0031             continue;
0032
0033         conn_bpc = conn->display_info.bpc ? conn->display_info.bpc : 8;
0034         conn_color_formats &= conn->display_info.color_formats;
0035
0036         if (conn_bpc < min_bpc)
0037             min_bpc = conn_bpc;
0038     }
0039
0040     /* connector doesn't config any color_format, use RGB444 as default */
0041     if (!conn_color_formats)
0042         conn_color_formats = DRM_COLOR_FORMAT_RGB444;
0043
0044     *color_depths = GENMASK(min_bpc, 0);
0045     *color_formats = conn_color_formats;
0046 }
0047
0048 static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st)
0049 {
0050     u64 pxlclk, aclk;
0051
0052     if (!kcrtc_st->base.active) {
0053         kcrtc_st->clock_ratio = 0;
0054         return;
0055     }
0056
0057     pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL;
0058     aclk = komeda_crtc_get_aclk(kcrtc_st);
0059
0060     kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk);
0061 }
0062
0063 /**
0064  * komeda_crtc_atomic_check - build display output data flow
0065  * @crtc: DRM crtc
0066  * @state: the crtc state object
0067  *
0068  * crtc_atomic_check is the final check stage, so beside build a display data
0069  * pipeline according to the crtc_state, but still needs to release or disable
0070  * the unclaimed pipeline resources.
0071  *
0072  * RETURNS:
0073  * Zero for success or -errno
0074  */
0075 static int
0076 komeda_crtc_atomic_check(struct drm_crtc *crtc,
0077              struct drm_atomic_state *state)
0078 {
0079     struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
0080                                       crtc);
0081     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0082     struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_state);
0083     int err;
0084
0085     if (drm_atomic_crtc_needs_modeset(crtc_state))
0086         komeda_crtc_update_clock_ratio(kcrtc_st);
0087
0088     if (crtc_state->active) {
0089         err = komeda_build_display_data_flow(kcrtc, kcrtc_st);
0090         if (err)
0091             return err;
0092     }
0093
0094     /* release unclaimed pipeline resources */
0095     err = komeda_release_unclaimed_resources(kcrtc->slave, kcrtc_st);
0096     if (err)
0097         return err;
0098
0099     err = komeda_release_unclaimed_resources(kcrtc->master, kcrtc_st);
0100     if (err)
0101         return err;
0102
0103     return 0;
0104 }
0105
0106 /* For active a crtc, mainly need two parts of preparation
0107  * 1. adjust display operation mode.
0108  * 2. enable needed clk
0109  */
0110 static int
0111 komeda_crtc_prepare(struct komeda_crtc *kcrtc)
0112 {
0113     struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
0114     struct komeda_pipeline *master = kcrtc->master;
0115     struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(kcrtc->base.state);
0116     struct drm_display_mode *mode = &kcrtc_st->base.adjusted_mode;
0117     u32 new_mode;
0118     int err;
0119
0120     mutex_lock(&mdev->lock);
0121
0122     new_mode = mdev->dpmode | BIT(master->id);
0123     if (WARN_ON(new_mode == mdev->dpmode)) {
0124         err = 0;
0125         goto unlock;
0126     }
0127
0128     err = mdev->funcs->change_opmode(mdev, new_mode);
0129     if (err) {
0130         DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,",
0131               mdev->dpmode, new_mode);
0132         goto unlock;
0133     }
0134
0135     mdev->dpmode = new_mode;
0136     /* Only need to enable aclk on single display mode, but no need to
0137      * enable aclk it on dual display mode, since the dual mode always
0138      * switch from single display mode, the aclk already enabled, no need
0139      * to enable it again.
0140      */
0141     if (new_mode != KOMEDA_MODE_DUAL_DISP) {
0142         err = clk_set_rate(mdev->aclk, komeda_crtc_get_aclk(kcrtc_st));
0143         if (err)
0144             DRM_ERROR("failed to set aclk.\n");
0145         err = clk_prepare_enable(mdev->aclk);
0146         if (err)
0147             DRM_ERROR("failed to enable aclk.\n");
0148     }
0149
0150     err = clk_set_rate(master->pxlclk, mode->crtc_clock * 1000);
0151     if (err)
0152         DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id);
0153     err = clk_prepare_enable(master->pxlclk);
0154     if (err)
0155         DRM_ERROR("failed to enable pxl clk for pipe%d.\n", master->id);
0156
0157 unlock:
0158     mutex_unlock(&mdev->lock);
0159
0160     return err;
0161 }
0162
0163 static int
0164 komeda_crtc_unprepare(struct komeda_crtc *kcrtc)
0165 {
0166     struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
0167     struct komeda_pipeline *master = kcrtc->master;
0168     u32 new_mode;
0169     int err;
0170
0171     mutex_lock(&mdev->lock);
0172
0173     new_mode = mdev->dpmode & (~BIT(master->id));
0174
0175     if (WARN_ON(new_mode == mdev->dpmode)) {
0176         err = 0;
0177         goto unlock;
0178     }
0179
0180     err = mdev->funcs->change_opmode(mdev, new_mode);
0181     if (err) {
0182         DRM_ERROR("failed to change opmode: 0x%x -> 0x%x.\n,",
0183               mdev->dpmode, new_mode);
0184         goto unlock;
0185     }
0186
0187     mdev->dpmode = new_mode;
0188
0189     clk_disable_unprepare(master->pxlclk);
0190     if (new_mode == KOMEDA_MODE_INACTIVE)
0191         clk_disable_unprepare(mdev->aclk);
0192
0193 unlock:
0194     mutex_unlock(&mdev->lock);
0195
0196     return err;
0197 }
0198
0199 void komeda_crtc_handle_event(struct komeda_crtc   *kcrtc,
0200                   struct komeda_events *evts)
0201 {
0202     struct drm_crtc *crtc = &kcrtc->base;
0203     u32 events = evts->pipes[kcrtc->master->id];
0204
0205     if (events & KOMEDA_EVENT_VSYNC)
0206         drm_crtc_handle_vblank(crtc);
0207
0208     if (events & KOMEDA_EVENT_EOW) {
0209         struct komeda_wb_connector *wb_conn = kcrtc->wb_conn;
0210
0211         if (wb_conn)
0212             drm_writeback_signal_completion(&wb_conn->base, 0);
0213         else
0214             DRM_WARN("CRTC[%d]: EOW happen but no wb_connector.\n",
0215                  drm_crtc_index(&kcrtc->base));
0216     }
0217     /* will handle it together with the write back support */
0218     if (events & KOMEDA_EVENT_EOW)
0219         DRM_DEBUG("EOW.\n");
0220
0221     if (events & KOMEDA_EVENT_FLIP) {
0222         unsigned long flags;
0223         struct drm_pending_vblank_event *event;
0224
0225         spin_lock_irqsave(&crtc->dev->event_lock, flags);
0226         if (kcrtc->disable_done) {
0227             complete_all(kcrtc->disable_done);
0228             kcrtc->disable_done = NULL;
0229         } else if (crtc->state->event) {
0230             event = crtc->state->event;
0231             /*
0232              * Consume event before notifying drm core that flip
0233              * happened.
0234              */
0235             crtc->state->event = NULL;
0236             drm_crtc_send_vblank_event(crtc, event);
0237         } else {
0238             DRM_WARN("CRTC[%d]: FLIP happen but no pending commit.\n",
0239                  drm_crtc_index(&kcrtc->base));
0240         }
0241         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
0242     }
0243 }
0244
0245 static void
0246 komeda_crtc_do_flush(struct drm_crtc *crtc,
0247              struct drm_crtc_state *old)
0248 {
0249     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0250     struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc->state);
0251     struct komeda_dev *mdev = kcrtc->base.dev->dev_private;
0252     struct komeda_pipeline *master = kcrtc->master;
0253     struct komeda_pipeline *slave = kcrtc->slave;
0254     struct komeda_wb_connector *wb_conn = kcrtc->wb_conn;
0255     struct drm_connector_state *conn_st;
0256
0257     DRM_DEBUG_ATOMIC("CRTC%d_FLUSH: active_pipes: 0x%x, affected: 0x%x.\n",
0258              drm_crtc_index(crtc),
0259              kcrtc_st->active_pipes, kcrtc_st->affected_pipes);
0260
0261     /* step 1: update the pipeline/component state to HW */
0262     if (has_bit(master->id, kcrtc_st->affected_pipes))
0263         komeda_pipeline_update(master, old->state);
0264
0265     if (slave && has_bit(slave->id, kcrtc_st->affected_pipes))
0266         komeda_pipeline_update(slave, old->state);
0267
0268     conn_st = wb_conn ? wb_conn->base.base.state : NULL;
0269     if (conn_st && conn_st->writeback_job)
0270         drm_writeback_queue_job(&wb_conn->base, conn_st);
0271
0272     /* step 2: notify the HW to kickoff the update */
0273     mdev->funcs->flush(mdev, master->id, kcrtc_st->active_pipes);
0274 }
0275
0276 static void
0277 komeda_crtc_atomic_enable(struct drm_crtc *crtc,
0278               struct drm_atomic_state *state)
0279 {
0280     struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state,
0281                                    crtc);
0282     pm_runtime_get_sync(crtc->dev->dev);
0283     komeda_crtc_prepare(to_kcrtc(crtc));
0284     drm_crtc_vblank_on(crtc);
0285     WARN_ON(drm_crtc_vblank_get(crtc));
0286     komeda_crtc_do_flush(crtc, old);
0287 }
0288
0289 static void
0290 komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc,
0291                      struct completion *input_flip_done)
0292 {
0293     struct drm_device *drm = kcrtc->base.dev;
0294     struct komeda_dev *mdev = kcrtc->master->mdev;
0295     struct completion *flip_done;
0296     struct completion temp;
0297     int timeout;
0298
0299     /* if caller doesn't send a flip_done, use a private flip_done */
0300     if (input_flip_done) {
0301         flip_done = input_flip_done;
0302     } else {
0303         init_completion(&temp);
0304         kcrtc->disable_done = &temp;
0305         flip_done = &temp;
0306     }
0307
0308     mdev->funcs->flush(mdev, kcrtc->master->id, 0);
0309
0310     /* wait the flip take affect.*/
0311     timeout = wait_for_completion_timeout(flip_done, HZ);
0312     if (timeout == 0) {
0313         DRM_ERROR("wait pipe%d flip done timeout\n", kcrtc->master->id);
0314         if (!input_flip_done) {
0315             unsigned long flags;
0316
0317             spin_lock_irqsave(&drm->event_lock, flags);
0318             kcrtc->disable_done = NULL;
0319             spin_unlock_irqrestore(&drm->event_lock, flags);
0320         }
0321     }
0322 }
0323
0324 static void
0325 komeda_crtc_atomic_disable(struct drm_crtc *crtc,
0326                struct drm_atomic_state *state)
0327 {
0328     struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state,
0329                                    crtc);
0330     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0331     struct komeda_crtc_state *old_st = to_kcrtc_st(old);
0332     struct komeda_pipeline *master = kcrtc->master;
0333     struct komeda_pipeline *slave  = kcrtc->slave;
0334     struct completion *disable_done;
0335     bool needs_phase2 = false;
0336
0337     DRM_DEBUG_ATOMIC("CRTC%d_DISABLE: active_pipes: 0x%x, affected: 0x%x\n",
0338              drm_crtc_index(crtc),
0339              old_st->active_pipes, old_st->affected_pipes);
0340
0341     if (slave && has_bit(slave->id, old_st->active_pipes))
0342         komeda_pipeline_disable(slave, old->state);
0343
0344     if (has_bit(master->id, old_st->active_pipes))
0345         needs_phase2 = komeda_pipeline_disable(master, old->state);
0346
0347     /* crtc_disable has two scenarios according to the state->active switch.
0348      * 1. active -> inactive
0349      *    this commit is a disable commit. and the commit will be finished
0350      *    or done after the disable operation. on this case we can directly
0351      *    use the crtc->state->event to tracking the HW disable operation.
0352      * 2. active -> active
0353      *    the crtc->commit is not for disable, but a modeset operation when
0354      *    crtc is active, such commit actually has been completed by 3
0355      *    DRM operations:
0356      *    crtc_disable, update_planes(crtc_flush), crtc_enable
0357      *    so on this case the crtc->commit is for the whole process.
0358      *    we can not use it for tracing the disable, we need a temporary
0359      *    flip_done for tracing the disable. and crtc->state->event for
0360      *    the crtc_enable operation.
0361      *    That's also the reason why skip modeset commit in
0362      *    komeda_crtc_atomic_flush()
0363      */
0364     disable_done = (needs_phase2 || crtc->state->active) ?
0365                NULL : &crtc->state->commit->flip_done;
0366
0367     /* wait phase 1 disable done */
0368     komeda_crtc_flush_and_wait_for_flip_done(kcrtc, disable_done);
0369
0370     /* phase 2 */
0371     if (needs_phase2) {
0372         komeda_pipeline_disable(kcrtc->master, old->state);
0373
0374         disable_done = crtc->state->active ?
0375                    NULL : &crtc->state->commit->flip_done;
0376
0377         komeda_crtc_flush_and_wait_for_flip_done(kcrtc, disable_done);
0378     }
0379
0380     drm_crtc_vblank_put(crtc);
0381     drm_crtc_vblank_off(crtc);
0382     komeda_crtc_unprepare(kcrtc);
0383     pm_runtime_put(crtc->dev->dev);
0384 }
0385
0386 static void
0387 komeda_crtc_atomic_flush(struct drm_crtc *crtc,
0388              struct drm_atomic_state *state)
0389 {
0390     struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
0391                                       crtc);
0392     struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state,
0393                                    crtc);
0394     /* commit with modeset will be handled in enable/disable */
0395     if (drm_atomic_crtc_needs_modeset(crtc_state))
0396         return;
0397
0398     komeda_crtc_do_flush(crtc, old);
0399 }
0400
0401 /* Returns the minimum frequency of the aclk rate (main engine clock) in Hz */
0402 static unsigned long
0403 komeda_calc_min_aclk_rate(struct komeda_crtc *kcrtc,
0404               unsigned long pxlclk)
0405 {
0406     /* Once dual-link one display pipeline drives two display outputs,
0407      * the aclk needs run on the double rate of pxlclk
0408      */
0409     if (kcrtc->master->dual_link)
0410         return pxlclk * 2;
0411     else
0412         return pxlclk;
0413 }
0414
0415 /* Get current aclk rate that specified by state */
0416 unsigned long komeda_crtc_get_aclk(struct komeda_crtc_state *kcrtc_st)
0417 {
0418     struct drm_crtc *crtc = kcrtc_st->base.crtc;
0419     struct komeda_dev *mdev = crtc->dev->dev_private;
0420     unsigned long pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000;
0421     unsigned long min_aclk;
0422
0423     min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), pxlclk);
0424
0425     return clk_round_rate(mdev->aclk, min_aclk);
0426 }
0427
0428 static enum drm_mode_status
0429 komeda_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *m)
0430 {
0431     struct komeda_dev *mdev = crtc->dev->dev_private;
0432     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0433     struct komeda_pipeline *master = kcrtc->master;
0434     unsigned long min_pxlclk, min_aclk;
0435
0436     if (m->flags & DRM_MODE_FLAG_INTERLACE)
0437         return MODE_NO_INTERLACE;
0438
0439     min_pxlclk = m->clock * 1000;
0440     if (master->dual_link)
0441         min_pxlclk /= 2;
0442
0443     if (min_pxlclk != clk_round_rate(master->pxlclk, min_pxlclk)) {
0444         DRM_DEBUG_ATOMIC("pxlclk doesn't support %lu Hz\n", min_pxlclk);
0445
0446         return MODE_NOCLOCK;
0447     }
0448
0449     min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), min_pxlclk);
0450     if (clk_round_rate(mdev->aclk, min_aclk) < min_aclk) {
0451         DRM_DEBUG_ATOMIC("engine clk can't satisfy the requirement of %s-clk: %lu.\n",
0452                  m->name, min_pxlclk);
0453
0454         return MODE_CLOCK_HIGH;
0455     }
0456
0457     return MODE_OK;
0458 }
0459
0460 static bool komeda_crtc_mode_fixup(struct drm_crtc *crtc,
0461                    const struct drm_display_mode *m,
0462                    struct drm_display_mode *adjusted_mode)
0463 {
0464     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0465     unsigned long clk_rate;
0466
0467     drm_mode_set_crtcinfo(adjusted_mode, 0);
0468     /* In dual link half the horizontal settings */
0469     if (kcrtc->master->dual_link) {
0470         adjusted_mode->crtc_clock /= 2;
0471         adjusted_mode->crtc_hdisplay /= 2;
0472         adjusted_mode->crtc_hsync_start /= 2;
0473         adjusted_mode->crtc_hsync_end /= 2;
0474         adjusted_mode->crtc_htotal /= 2;
0475     }
0476
0477     clk_rate = adjusted_mode->crtc_clock * 1000;
0478     /* crtc_clock will be used as the komeda output pixel clock */
0479     adjusted_mode->crtc_clock = clk_round_rate(kcrtc->master->pxlclk,
0480                            clk_rate) / 1000;
0481
0482     return true;
0483 }
0484
0485 static const struct drm_crtc_helper_funcs komeda_crtc_helper_funcs = {
0486     .atomic_check   = komeda_crtc_atomic_check,
0487     .atomic_flush   = komeda_crtc_atomic_flush,
0488     .atomic_enable  = komeda_crtc_atomic_enable,
0489     .atomic_disable = komeda_crtc_atomic_disable,
0490     .mode_valid = komeda_crtc_mode_valid,
0491     .mode_fixup = komeda_crtc_mode_fixup,
0492 };
0493
0494 static void komeda_crtc_reset(struct drm_crtc *crtc)
0495 {
0496     struct komeda_crtc_state *state;
0497
0498     if (crtc->state)
0499         __drm_atomic_helper_crtc_destroy_state(crtc->state);
0500
0501     kfree(to_kcrtc_st(crtc->state));
0502     crtc->state = NULL;
0503
0504     state = kzalloc(sizeof(*state), GFP_KERNEL);
0505     if (state)
0506         __drm_atomic_helper_crtc_reset(crtc, &state->base);
0507 }
0508
0509 static struct drm_crtc_state *
0510 komeda_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
0511 {
0512     struct komeda_crtc_state *old = to_kcrtc_st(crtc->state);
0513     struct komeda_crtc_state *new;
0514
0515     new = kzalloc(sizeof(*new), GFP_KERNEL);
0516     if (!new)
0517         return NULL;
0518
0519     __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base);
0520
0521     new->affected_pipes = old->active_pipes;
0522     new->clock_ratio = old->clock_ratio;
0523     new->max_slave_zorder = old->max_slave_zorder;
0524
0525     return &new->base;
0526 }
0527
0528 static void komeda_crtc_atomic_destroy_state(struct drm_crtc *crtc,
0529                          struct drm_crtc_state *state)
0530 {
0531     __drm_atomic_helper_crtc_destroy_state(state);
0532     kfree(to_kcrtc_st(state));
0533 }
0534
0535 static int komeda_crtc_vblank_enable(struct drm_crtc *crtc)
0536 {
0537     struct komeda_dev *mdev = crtc->dev->dev_private;
0538     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0539
0540     mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, true);
0541     return 0;
0542 }
0543
0544 static void komeda_crtc_vblank_disable(struct drm_crtc *crtc)
0545 {
0546     struct komeda_dev *mdev = crtc->dev->dev_private;
0547     struct komeda_crtc *kcrtc = to_kcrtc(crtc);
0548
0549     mdev->funcs->on_off_vblank(mdev, kcrtc->master->id, false);
0550 }
0551
0552 static const struct drm_crtc_funcs komeda_crtc_funcs = {
0553     .destroy        = drm_crtc_cleanup,
0554     .set_config     = drm_atomic_helper_set_config,
0555     .page_flip      = drm_atomic_helper_page_flip,
0556     .reset          = komeda_crtc_reset,
0557     .atomic_duplicate_state = komeda_crtc_atomic_duplicate_state,
0558     .atomic_destroy_state   = komeda_crtc_atomic_destroy_state,
0559     .enable_vblank      = komeda_crtc_vblank_enable,
0560     .disable_vblank     = komeda_crtc_vblank_disable,
0561 };
0562
0563 int komeda_kms_setup_crtcs(struct komeda_kms_dev *kms,
0564                struct komeda_dev *mdev)
0565 {
0566     struct komeda_crtc *crtc;
0567     struct komeda_pipeline *master;
0568     char str[16];
0569     int i;
0570
0571     kms->n_crtcs = 0;
0572
0573     for (i = 0; i < mdev->n_pipelines; i++) {
0574         crtc = &kms->crtcs[kms->n_crtcs];
0575         master = mdev->pipelines[i];
0576
0577         crtc->master = master;
0578         crtc->slave  = komeda_pipeline_get_slave(master);
0579
0580         if (crtc->slave)
0581             sprintf(str, "pipe-%d", crtc->slave->id);
0582         else
0583             sprintf(str, "None");
0584
0585         DRM_INFO("CRTC-%d: master(pipe-%d) slave(%s).\n",
0586              kms->n_crtcs, master->id, str);
0587
0588         kms->n_crtcs++;
0589     }
0590
0591     return 0;
0592 }
0593
0594 static struct drm_plane *
0595 get_crtc_primary(struct komeda_kms_dev *kms, struct komeda_crtc *crtc)
0596 {
0597     struct komeda_plane *kplane;
0598     struct drm_plane *plane;
0599
0600     drm_for_each_plane(plane, &kms->base) {
0601         if (plane->type != DRM_PLANE_TYPE_PRIMARY)
0602             continue;
0603
0604         kplane = to_kplane(plane);
0605         /* only master can be primary */
0606         if (kplane->layer->base.pipeline == crtc->master)
0607             return plane;
0608     }
0609
0610     return NULL;
0611 }
0612
0613 static int komeda_crtc_add(struct komeda_kms_dev *kms,
0614                struct komeda_crtc *kcrtc)
0615 {
0616     struct drm_crtc *crtc = &kcrtc->base;
0617     int err;
0618
0619     err = drm_crtc_init_with_planes(&kms->base, crtc,
0620                     get_crtc_primary(kms, kcrtc), NULL,
0621                     &komeda_crtc_funcs, NULL);
0622     if (err)
0623         return err;
0624
0625     drm_crtc_helper_add(crtc, &komeda_crtc_helper_funcs);
0626
0627     crtc->port = kcrtc->master->of_output_port;
0628
0629     drm_crtc_enable_color_mgmt(crtc, 0, true, KOMEDA_COLOR_LUT_SIZE);
0630
0631     return err;
0632 }
0633
0634 int komeda_kms_add_crtcs(struct komeda_kms_dev *kms, struct komeda_dev *mdev)
0635 {
0636     int i, err;
0637
0638     for (i = 0; i < kms->n_crtcs; i++) {
0639         err = komeda_crtc_add(kms, &kms->crtcs[i]);
0640         if (err)
0641             return err;
0642     }
0643
0644     return 0;
0645 }