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0023 #ifndef __SMU_CMN_H__
0024 #define __SMU_CMN_H__
0025
0026 #include "amdgpu_smu.h"
0027
0028 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
0029
0030 #define FDO_PWM_MODE_STATIC 1
0031 #define FDO_PWM_MODE_STATIC_RPM 5
0032
0033 int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
0034 uint16_t msg_index,
0035 uint32_t param);
0036 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
0037 enum smu_message_type msg,
0038 uint32_t param,
0039 uint32_t *read_arg);
0040
0041 int smu_cmn_send_smc_msg(struct smu_context *smu,
0042 enum smu_message_type msg,
0043 uint32_t *read_arg);
0044
0045 int smu_cmn_wait_for_response(struct smu_context *smu);
0046
0047 int smu_cmn_to_asic_specific_index(struct smu_context *smu,
0048 enum smu_cmn2asic_mapping_type type,
0049 uint32_t index);
0050
0051 int smu_cmn_feature_is_supported(struct smu_context *smu,
0052 enum smu_feature_mask mask);
0053
0054 int smu_cmn_feature_is_enabled(struct smu_context *smu,
0055 enum smu_feature_mask mask);
0056
0057 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
0058 enum smu_clk_type clk_type);
0059
0060 int smu_cmn_get_enabled_mask(struct smu_context *smu,
0061 uint64_t *feature_mask);
0062
0063 uint64_t smu_cmn_get_indep_throttler_status(
0064 const unsigned long dep_status,
0065 const uint8_t *throttler_map);
0066
0067 int smu_cmn_feature_update_enable_state(struct smu_context *smu,
0068 uint64_t feature_mask,
0069 bool enabled);
0070
0071 int smu_cmn_feature_set_enabled(struct smu_context *smu,
0072 enum smu_feature_mask mask,
0073 bool enable);
0074
0075 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
0076 char *buf);
0077
0078 int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
0079 uint64_t new_mask);
0080
0081 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
0082 enum smu_feature_mask mask);
0083
0084 int smu_cmn_get_smc_version(struct smu_context *smu,
0085 uint32_t *if_version,
0086 uint32_t *smu_version);
0087
0088 int smu_cmn_update_table(struct smu_context *smu,
0089 enum smu_table_id table_index,
0090 int argument,
0091 void *table_data,
0092 bool drv2smu);
0093
0094 int smu_cmn_write_watermarks_table(struct smu_context *smu);
0095
0096 int smu_cmn_write_pptable(struct smu_context *smu);
0097
0098 int smu_cmn_get_metrics_table(struct smu_context *smu,
0099 void *metrics_table,
0100 bool bypass_cache);
0101
0102 int smu_cmn_get_combo_pptable(struct smu_context *smu);
0103
0104 void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev);
0105
0106 int smu_cmn_set_mp1_state(struct smu_context *smu,
0107 enum pp_mp1_state mp1_state);
0108
0109
0110
0111
0112
0113 static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset)
0114 {
0115 if (!*buf || !offset)
0116 return;
0117
0118 *offset = offset_in_page(*buf);
0119 *buf -= *offset;
0120 }
0121
0122 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev);
0123
0124 #endif
0125 #endif