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0023 #ifndef __ALDEBARAN_PPT_H__
0024 #define __ALDEBARAN_PPT_H__
0025
0026 #define ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL 0x3
0027 #define ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL 0x3
0028 #define ALDEBARAN_UMD_PSTATE_MCLK_LEVEL 0x2
0029
0030 #define MAX_DPM_NUMBER 16
0031 #define ALDEBARAN_MAX_PCIE_CONF 2
0032
0033 struct aldebaran_dpm_level {
0034 bool enabled;
0035 uint32_t value;
0036 uint32_t param1;
0037 };
0038
0039 struct aldebaran_dpm_state {
0040 uint32_t soft_min_level;
0041 uint32_t soft_max_level;
0042 uint32_t hard_min_level;
0043 uint32_t hard_max_level;
0044 };
0045
0046 struct aldebaran_single_dpm_table {
0047 uint32_t count;
0048 struct aldebaran_dpm_state dpm_state;
0049 struct aldebaran_dpm_level dpm_levels[MAX_DPM_NUMBER];
0050 };
0051
0052 struct aldebaran_pcie_table {
0053 uint16_t count;
0054 uint8_t pcie_gen[ALDEBARAN_MAX_PCIE_CONF];
0055 uint8_t pcie_lane[ALDEBARAN_MAX_PCIE_CONF];
0056 uint32_t lclk[ALDEBARAN_MAX_PCIE_CONF];
0057 };
0058
0059 struct aldebaran_dpm_table {
0060 struct aldebaran_single_dpm_table soc_table;
0061 struct aldebaran_single_dpm_table gfx_table;
0062 struct aldebaran_single_dpm_table mem_table;
0063 struct aldebaran_single_dpm_table eclk_table;
0064 struct aldebaran_single_dpm_table vclk_table;
0065 struct aldebaran_single_dpm_table dclk_table;
0066 struct aldebaran_single_dpm_table fclk_table;
0067 struct aldebaran_pcie_table pcie_table;
0068 };
0069
0070 extern void aldebaran_set_ppt_funcs(struct smu_context *smu);
0071
0072 #endif