swsmu/smu11/sienna_cichlid_ppt.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #define SWSMU_CODE_LAYER_L2
0025
0026 #include <linux/firmware.h>
0027 #include <linux/pci.h>
0028 #include <linux/i2c.h>
0029 #include "amdgpu.h"
0030 #include "amdgpu_dpm.h"
0031 #include "amdgpu_smu.h"
0032 #include "atomfirmware.h"
0033 #include "amdgpu_atomfirmware.h"
0034 #include "amdgpu_atombios.h"
0035 #include "smu_v11_0.h"
0036 #include "smu11_driver_if_sienna_cichlid.h"
0037 #include "soc15_common.h"
0038 #include "atom.h"
0039 #include "sienna_cichlid_ppt.h"
0040 #include "smu_v11_0_7_pptable.h"
0041 #include "smu_v11_0_7_ppsmc.h"
0042 #include "nbio/nbio_2_3_offset.h"
0043 #include "nbio/nbio_2_3_sh_mask.h"
0044 #include "thm/thm_11_0_2_offset.h"
0045 #include "thm/thm_11_0_2_sh_mask.h"
0046 #include "mp/mp_11_0_offset.h"
0047 #include "mp/mp_11_0_sh_mask.h"
0048
0049 #include "asic_reg/mp/mp_11_0_sh_mask.h"
0050 #include "amdgpu_ras.h"
0051 #include "smu_cmn.h"
0052
0053 /*
0054  * DO NOT use these for err/warn/info/debug messages.
0055  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
0056  * They are more MGPU friendly.
0057  */
0058 #undef pr_err
0059 #undef pr_warn
0060 #undef pr_info
0061 #undef pr_debug
0062
0063 #define FEATURE_MASK(feature) (1ULL << feature)
0064 #define SMC_DPM_FEATURE ( \
0065     FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
0066     FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
0067     FEATURE_MASK(FEATURE_DPM_UCLK_BIT)   | \
0068     FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
0069     FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
0070     FEATURE_MASK(FEATURE_DPM_FCLK_BIT)   | \
0071     FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
0072     FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
0073
0074 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
0075
0076 #define GET_PPTABLE_MEMBER(field, member) do {\
0077     if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))\
0078         (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
0079     else\
0080         (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
0081 } while(0)
0082
0083 /* STB FIFO depth is in 64bit units */
0084 #define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES 8
0085
0086 /*
0087  * SMU support ECCTABLE since version 58.70.0,
0088  * use this to check whether ECCTABLE feature is supported.
0089  */
0090 #define SUPPORT_ECCTABLE_SMU_VERSION 0x003a4600
0091
0092 static int get_table_size(struct smu_context *smu)
0093 {
0094     if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
0095         return sizeof(PPTable_beige_goby_t);
0096     else
0097         return sizeof(PPTable_t);
0098 }
0099
0100 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
0101     MSG_MAP(TestMessage,            PPSMC_MSG_TestMessage,                 1),
0102     MSG_MAP(GetSmuVersion,          PPSMC_MSG_GetSmuVersion,               1),
0103     MSG_MAP(GetDriverIfVersion,     PPSMC_MSG_GetDriverIfVersion,          1),
0104     MSG_MAP(SetAllowedFeaturesMaskLow,  PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
0105     MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
0106     MSG_MAP(EnableAllSmuFeatures,       PPSMC_MSG_EnableAllSmuFeatures,        0),
0107     MSG_MAP(DisableAllSmuFeatures,      PPSMC_MSG_DisableAllSmuFeatures,       0),
0108     MSG_MAP(EnableSmuFeaturesLow,       PPSMC_MSG_EnableSmuFeaturesLow,        1),
0109     MSG_MAP(EnableSmuFeaturesHigh,      PPSMC_MSG_EnableSmuFeaturesHigh,       1),
0110     MSG_MAP(DisableSmuFeaturesLow,      PPSMC_MSG_DisableSmuFeaturesLow,       1),
0111     MSG_MAP(DisableSmuFeaturesHigh,     PPSMC_MSG_DisableSmuFeaturesHigh,      1),
0112     MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
0113     MSG_MAP(GetEnabledSmuFeaturesHigh,  PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
0114     MSG_MAP(SetWorkloadMask,        PPSMC_MSG_SetWorkloadMask,             1),
0115     MSG_MAP(SetPptLimit,            PPSMC_MSG_SetPptLimit,                 0),
0116     MSG_MAP(SetDriverDramAddrHigh,      PPSMC_MSG_SetDriverDramAddrHigh,       1),
0117     MSG_MAP(SetDriverDramAddrLow,       PPSMC_MSG_SetDriverDramAddrLow,        1),
0118     MSG_MAP(SetToolsDramAddrHigh,       PPSMC_MSG_SetToolsDramAddrHigh,        0),
0119     MSG_MAP(SetToolsDramAddrLow,        PPSMC_MSG_SetToolsDramAddrLow,         0),
0120     MSG_MAP(TransferTableSmu2Dram,      PPSMC_MSG_TransferTableSmu2Dram,       1),
0121     MSG_MAP(TransferTableDram2Smu,      PPSMC_MSG_TransferTableDram2Smu,       0),
0122     MSG_MAP(UseDefaultPPTable,      PPSMC_MSG_UseDefaultPPTable,           0),
0123     MSG_MAP(RunDcBtc,           PPSMC_MSG_RunDcBtc,                    0),
0124     MSG_MAP(EnterBaco,          PPSMC_MSG_EnterBaco,                   0),
0125     MSG_MAP(SetSoftMinByFreq,       PPSMC_MSG_SetSoftMinByFreq,            1),
0126     MSG_MAP(SetSoftMaxByFreq,       PPSMC_MSG_SetSoftMaxByFreq,            1),
0127     MSG_MAP(SetHardMinByFreq,       PPSMC_MSG_SetHardMinByFreq,            1),
0128     MSG_MAP(SetHardMaxByFreq,       PPSMC_MSG_SetHardMaxByFreq,            0),
0129     MSG_MAP(GetMinDpmFreq,          PPSMC_MSG_GetMinDpmFreq,               1),
0130     MSG_MAP(GetMaxDpmFreq,          PPSMC_MSG_GetMaxDpmFreq,               1),
0131     MSG_MAP(GetDpmFreqByIndex,      PPSMC_MSG_GetDpmFreqByIndex,           1),
0132     MSG_MAP(SetGeminiMode,          PPSMC_MSG_SetGeminiMode,               0),
0133     MSG_MAP(SetGeminiApertureHigh,      PPSMC_MSG_SetGeminiApertureHigh,       0),
0134     MSG_MAP(SetGeminiApertureLow,       PPSMC_MSG_SetGeminiApertureLow,        0),
0135     MSG_MAP(OverridePcieParameters,     PPSMC_MSG_OverridePcieParameters,      0),
0136     MSG_MAP(ReenableAcDcInterrupt,      PPSMC_MSG_ReenableAcDcInterrupt,       0),
0137     MSG_MAP(NotifyPowerSource,      PPSMC_MSG_NotifyPowerSource,           0),
0138     MSG_MAP(SetUclkFastSwitch,      PPSMC_MSG_SetUclkFastSwitch,           0),
0139     MSG_MAP(SetVideoFps,            PPSMC_MSG_SetVideoFps,                 0),
0140     MSG_MAP(PrepareMp1ForUnload,        PPSMC_MSG_PrepareMp1ForUnload,         1),
0141     MSG_MAP(AllowGfxOff,            PPSMC_MSG_AllowGfxOff,                 0),
0142     MSG_MAP(DisallowGfxOff,         PPSMC_MSG_DisallowGfxOff,              0),
0143     MSG_MAP(GetPptLimit,            PPSMC_MSG_GetPptLimit,                 0),
0144     MSG_MAP(GetDcModeMaxDpmFreq,        PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
0145     MSG_MAP(ExitBaco,           PPSMC_MSG_ExitBaco,                    0),
0146     MSG_MAP(PowerUpVcn,         PPSMC_MSG_PowerUpVcn,                  0),
0147     MSG_MAP(PowerDownVcn,           PPSMC_MSG_PowerDownVcn,                0),
0148     MSG_MAP(PowerUpJpeg,            PPSMC_MSG_PowerUpJpeg,                 0),
0149     MSG_MAP(PowerDownJpeg,          PPSMC_MSG_PowerDownJpeg,               0),
0150     MSG_MAP(BacoAudioD3PME,         PPSMC_MSG_BacoAudioD3PME,              0),
0151     MSG_MAP(ArmD3,              PPSMC_MSG_ArmD3,                       0),
0152     MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,              0),
0153     MSG_MAP(SetMGpuFanBoostLimitRpm,    PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
0154     MSG_MAP(SetGpoFeaturePMask,     PPSMC_MSG_SetGpoFeaturePMask,          0),
0155     MSG_MAP(DisallowGpo,            PPSMC_MSG_DisallowGpo,                 0),
0156     MSG_MAP(Enable2ndUSB20Port,     PPSMC_MSG_Enable2ndUSB20Port,          0),
0157 };
0158
0159 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
0160     CLK_MAP(GFXCLK,     PPCLK_GFXCLK),
0161     CLK_MAP(SCLK,       PPCLK_GFXCLK),
0162     CLK_MAP(SOCCLK,     PPCLK_SOCCLK),
0163     CLK_MAP(FCLK,       PPCLK_FCLK),
0164     CLK_MAP(UCLK,       PPCLK_UCLK),
0165     CLK_MAP(MCLK,       PPCLK_UCLK),
0166     CLK_MAP(DCLK,       PPCLK_DCLK_0),
0167     CLK_MAP(DCLK1,      PPCLK_DCLK_1),
0168     CLK_MAP(VCLK,       PPCLK_VCLK_0),
0169     CLK_MAP(VCLK1,      PPCLK_VCLK_1),
0170     CLK_MAP(DCEFCLK,    PPCLK_DCEFCLK),
0171     CLK_MAP(DISPCLK,    PPCLK_DISPCLK),
0172     CLK_MAP(PIXCLK,     PPCLK_PIXCLK),
0173     CLK_MAP(PHYCLK,     PPCLK_PHYCLK),
0174 };
0175
0176 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
0177     FEA_MAP(DPM_PREFETCHER),
0178     FEA_MAP(DPM_GFXCLK),
0179     FEA_MAP(DPM_GFX_GPO),
0180     FEA_MAP(DPM_UCLK),
0181     FEA_MAP(DPM_FCLK),
0182     FEA_MAP(DPM_SOCCLK),
0183     FEA_MAP(DPM_MP0CLK),
0184     FEA_MAP(DPM_LINK),
0185     FEA_MAP(DPM_DCEFCLK),
0186     FEA_MAP(DPM_XGMI),
0187     FEA_MAP(MEM_VDDCI_SCALING),
0188     FEA_MAP(MEM_MVDD_SCALING),
0189     FEA_MAP(DS_GFXCLK),
0190     FEA_MAP(DS_SOCCLK),
0191     FEA_MAP(DS_FCLK),
0192     FEA_MAP(DS_LCLK),
0193     FEA_MAP(DS_DCEFCLK),
0194     FEA_MAP(DS_UCLK),
0195     FEA_MAP(GFX_ULV),
0196     FEA_MAP(FW_DSTATE),
0197     FEA_MAP(GFXOFF),
0198     FEA_MAP(BACO),
0199     FEA_MAP(MM_DPM_PG),
0200     FEA_MAP(RSMU_SMN_CG),
0201     FEA_MAP(PPT),
0202     FEA_MAP(TDC),
0203     FEA_MAP(APCC_PLUS),
0204     FEA_MAP(GTHR),
0205     FEA_MAP(ACDC),
0206     FEA_MAP(VR0HOT),
0207     FEA_MAP(VR1HOT),
0208     FEA_MAP(FW_CTF),
0209     FEA_MAP(FAN_CONTROL),
0210     FEA_MAP(THERMAL),
0211     FEA_MAP(GFX_DCS),
0212     FEA_MAP(RM),
0213     FEA_MAP(LED_DISPLAY),
0214     FEA_MAP(GFX_SS),
0215     FEA_MAP(OUT_OF_BAND_MONITOR),
0216     FEA_MAP(TEMP_DEPENDENT_VMIN),
0217     FEA_MAP(MMHUB_PG),
0218     FEA_MAP(ATHUB_PG),
0219     FEA_MAP(APCC_DFLL),
0220 };
0221
0222 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
0223     TAB_MAP(PPTABLE),
0224     TAB_MAP(WATERMARKS),
0225     TAB_MAP(AVFS_PSM_DEBUG),
0226     TAB_MAP(AVFS_FUSE_OVERRIDE),
0227     TAB_MAP(PMSTATUSLOG),
0228     TAB_MAP(SMU_METRICS),
0229     TAB_MAP(DRIVER_SMU_CONFIG),
0230     TAB_MAP(ACTIVITY_MONITOR_COEFF),
0231     TAB_MAP(OVERDRIVE),
0232     TAB_MAP(I2C_COMMANDS),
0233     TAB_MAP(PACE),
0234     TAB_MAP(ECCINFO),
0235 };
0236
0237 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
0238     PWR_MAP(AC),
0239     PWR_MAP(DC),
0240 };
0241
0242 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
0243     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,   WORKLOAD_PPLIB_DEFAULT_BIT),
0244     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,     WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
0245     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,      WORKLOAD_PPLIB_POWER_SAVING_BIT),
0246     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,        WORKLOAD_PPLIB_VIDEO_BIT),
0247     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,           WORKLOAD_PPLIB_VR_BIT),
0248     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,      WORKLOAD_PPLIB_COMPUTE_BIT),
0249     WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,       WORKLOAD_PPLIB_CUSTOM_BIT),
0250 };
0251
0252 static const uint8_t sienna_cichlid_throttler_map[] = {
0253     [THROTTLER_TEMP_EDGE_BIT]   = (SMU_THROTTLER_TEMP_EDGE_BIT),
0254     [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
0255     [THROTTLER_TEMP_MEM_BIT]    = (SMU_THROTTLER_TEMP_MEM_BIT),
0256     [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
0257     [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
0258     [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
0259     [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
0260     [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
0261     [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
0262     [THROTTLER_TDC_GFX_BIT]     = (SMU_THROTTLER_TDC_GFX_BIT),
0263     [THROTTLER_TDC_SOC_BIT]     = (SMU_THROTTLER_TDC_SOC_BIT),
0264     [THROTTLER_PPT0_BIT]        = (SMU_THROTTLER_PPT0_BIT),
0265     [THROTTLER_PPT1_BIT]        = (SMU_THROTTLER_PPT1_BIT),
0266     [THROTTLER_PPT2_BIT]        = (SMU_THROTTLER_PPT2_BIT),
0267     [THROTTLER_PPT3_BIT]        = (SMU_THROTTLER_PPT3_BIT),
0268     [THROTTLER_FIT_BIT]     = (SMU_THROTTLER_FIT_BIT),
0269     [THROTTLER_PPM_BIT]     = (SMU_THROTTLER_PPM_BIT),
0270     [THROTTLER_APCC_BIT]        = (SMU_THROTTLER_APCC_BIT),
0271 };
0272
0273 static int
0274 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
0275                   uint32_t *feature_mask, uint32_t num)
0276 {
0277     struct amdgpu_device *adev = smu->adev;
0278
0279     if (num > 2)
0280         return -EINVAL;
0281
0282     memset(feature_mask, 0, sizeof(uint32_t) * num);
0283
0284     *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
0285                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
0286                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
0287                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
0288                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
0289                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
0290                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
0291                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
0292                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
0293                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
0294                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
0295                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
0296                 | FEATURE_MASK(FEATURE_PPT_BIT)
0297                 | FEATURE_MASK(FEATURE_TDC_BIT)
0298                 | FEATURE_MASK(FEATURE_BACO_BIT)
0299                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
0300                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
0301                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
0302                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
0303                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
0304
0305     if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
0306         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
0307         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
0308     }
0309
0310     if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
0311         (adev->ip_versions[MP1_HWIP][0] > IP_VERSION(11, 0, 7)) &&
0312         !(adev->flags & AMD_IS_APU))
0313         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
0314
0315     if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
0316         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
0317                     | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
0318                     | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
0319
0320     if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
0321         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
0322
0323     if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
0324         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
0325
0326     if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
0327         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
0328
0329     if (adev->pm.pp_feature & PP_ULV_MASK)
0330         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
0331
0332     if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
0333         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
0334
0335     if (adev->pm.pp_feature & PP_GFXOFF_MASK)
0336         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
0337
0338     if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
0339         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
0340
0341     if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
0342         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
0343
0344     if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
0345         smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
0346         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
0347
0348     if (smu->dc_controlled_by_gpio)
0349        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
0350
0351     if (amdgpu_device_should_use_aspm(adev))
0352         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
0353
0354     return 0;
0355 }
0356
0357 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
0358 {
0359     struct smu_table_context *table_context = &smu->smu_table;
0360     struct smu_11_0_7_powerplay_table *powerplay_table =
0361         table_context->power_play_table;
0362     struct smu_baco_context *smu_baco = &smu->smu_baco;
0363     struct amdgpu_device *adev = smu->adev;
0364     uint32_t val;
0365
0366     if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
0367         val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
0368         smu_baco->platform_support =
0369             (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
0370                                     false;
0371
0372         /*
0373          * Disable BACO entry/exit completely on below SKUs to
0374          * avoid hardware intermittent failures.
0375          */
0376         if (((adev->pdev->device == 0x73A1) &&
0377             (adev->pdev->revision == 0x00)) ||
0378             ((adev->pdev->device == 0x73BF) &&
0379             (adev->pdev->revision == 0xCF)))
0380             smu_baco->platform_support = false;
0381
0382     }
0383 }
0384
0385 static void sienna_cichlid_check_fan_support(struct smu_context *smu)
0386 {
0387     struct smu_table_context *table_context = &smu->smu_table;
0388     PPTable_t *pptable = table_context->driver_pptable;
0389     uint64_t features = *(uint64_t *) pptable->FeaturesToRun;
0390
0391     /* Fan control is not possible if PPTable has it disabled */
0392     smu->adev->pm.no_fan =
0393         !(features & (1ULL << FEATURE_FAN_CONTROL_BIT));
0394     if (smu->adev->pm.no_fan)
0395         dev_info_once(smu->adev->dev,
0396                   "PMFW based fan control disabled");
0397 }
0398
0399 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
0400 {
0401     struct smu_table_context *table_context = &smu->smu_table;
0402     struct smu_11_0_7_powerplay_table *powerplay_table =
0403         table_context->power_play_table;
0404
0405     if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
0406         smu->dc_controlled_by_gpio = true;
0407
0408     sienna_cichlid_check_bxco_support(smu);
0409     sienna_cichlid_check_fan_support(smu);
0410
0411     table_context->thermal_controller_type =
0412         powerplay_table->thermal_controller_type;
0413
0414     /*
0415      * Instead of having its own buffer space and get overdrive_table copied,
0416      * smu->od_settings just points to the actual overdrive_table
0417      */
0418     smu->od_settings = &powerplay_table->overdrive_table;
0419
0420     return 0;
0421 }
0422
0423 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
0424 {
0425     struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
0426     int index, ret;
0427     I2cControllerConfig_t *table_member;
0428
0429     index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
0430                         smc_dpm_info);
0431
0432     ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
0433                       (uint8_t **)&smc_dpm_table);
0434     if (ret)
0435         return ret;
0436     GET_PPTABLE_MEMBER(I2cControllers, &table_member);
0437     memcpy(table_member, smc_dpm_table->I2cControllers,
0438             sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
0439
0440     return 0;
0441 }
0442
0443 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
0444 {
0445     struct smu_table_context *table_context = &smu->smu_table;
0446     struct smu_11_0_7_powerplay_table *powerplay_table =
0447         table_context->power_play_table;
0448     int table_size;
0449
0450     table_size = get_table_size(smu);
0451     memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
0452            table_size);
0453
0454     return 0;
0455 }
0456
0457 static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
0458 {
0459     struct amdgpu_device *adev = smu->adev;
0460     uint32_t *board_reserved;
0461     uint16_t *freq_table_gfx;
0462     uint32_t i;
0463
0464     /* Fix some OEM SKU specific stability issues */
0465     GET_PPTABLE_MEMBER(BoardReserved, &board_reserved);
0466     if ((adev->pdev->device == 0x73DF) &&
0467         (adev->pdev->revision == 0XC3) &&
0468         (adev->pdev->subsystem_device == 0x16C2) &&
0469         (adev->pdev->subsystem_vendor == 0x1043))
0470         board_reserved[0] = 1387;
0471
0472     GET_PPTABLE_MEMBER(FreqTableGfx, &freq_table_gfx);
0473     if ((adev->pdev->device == 0x73DF) &&
0474         (adev->pdev->revision == 0XC3) &&
0475         ((adev->pdev->subsystem_device == 0x16C2) ||
0476         (adev->pdev->subsystem_device == 0x133C)) &&
0477         (adev->pdev->subsystem_vendor == 0x1043)) {
0478         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) {
0479             if (freq_table_gfx[i] > 2500)
0480                 freq_table_gfx[i] = 2500;
0481         }
0482     }
0483
0484     return 0;
0485 }
0486
0487 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
0488 {
0489     int ret = 0;
0490
0491     ret = smu_v11_0_setup_pptable(smu);
0492     if (ret)
0493         return ret;
0494
0495     ret = sienna_cichlid_store_powerplay_table(smu);
0496     if (ret)
0497         return ret;
0498
0499     ret = sienna_cichlid_append_powerplay_table(smu);
0500     if (ret)
0501         return ret;
0502
0503     ret = sienna_cichlid_check_powerplay_table(smu);
0504     if (ret)
0505         return ret;
0506
0507     return sienna_cichlid_patch_pptable_quirk(smu);
0508 }
0509
0510 static int sienna_cichlid_tables_init(struct smu_context *smu)
0511 {
0512     struct smu_table_context *smu_table = &smu->smu_table;
0513     struct smu_table *tables = smu_table->tables;
0514     int table_size;
0515
0516     table_size = get_table_size(smu);
0517     SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
0518                    PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0519     SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
0520                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0521     SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
0522                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0523     SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
0524                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0525     SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
0526                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0527     SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
0528                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0529     SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
0530                sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
0531                    AMDGPU_GEM_DOMAIN_VRAM);
0532     SMU_TABLE_INIT(tables, SMU_TABLE_ECCINFO, sizeof(EccInfoTable_t),
0533             PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0534     SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfigExternal_t),
0535                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
0536
0537     smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
0538     if (!smu_table->metrics_table)
0539         goto err0_out;
0540     smu_table->metrics_time = 0;
0541
0542     smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
0543     smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
0544     if (!smu_table->gpu_metrics_table)
0545         goto err1_out;
0546
0547     smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
0548     if (!smu_table->watermarks_table)
0549         goto err2_out;
0550
0551     smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL);
0552     if (!smu_table->ecc_table)
0553         goto err3_out;
0554
0555     smu_table->driver_smu_config_table =
0556         kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
0557     if (!smu_table->driver_smu_config_table)
0558         goto err4_out;
0559
0560     return 0;
0561
0562 err4_out:
0563     kfree(smu_table->ecc_table);
0564 err3_out:
0565     kfree(smu_table->watermarks_table);
0566 err2_out:
0567     kfree(smu_table->gpu_metrics_table);
0568 err1_out:
0569     kfree(smu_table->metrics_table);
0570 err0_out:
0571     return -ENOMEM;
0572 }
0573
0574 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
0575 {
0576     struct smu_table_context *smu_table= &smu->smu_table;
0577     SmuMetricsExternal_t *metrics_ext =
0578         (SmuMetricsExternal_t *)(smu_table->metrics_table);
0579     uint32_t throttler_status = 0;
0580     int i;
0581
0582     if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
0583          (smu->smc_fw_version >= 0x3A4900)) {
0584         for (i = 0; i < THROTTLER_COUNT; i++)
0585             throttler_status |=
0586                 (metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
0587     } else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
0588          (smu->smc_fw_version >= 0x3A4300)) {
0589         for (i = 0; i < THROTTLER_COUNT; i++)
0590             throttler_status |=
0591                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
0592     } else {
0593         throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
0594     }
0595
0596     return throttler_status;
0597 }
0598
0599 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
0600                       uint32_t *current_power_limit,
0601                       uint32_t *default_power_limit,
0602                       uint32_t *max_power_limit)
0603 {
0604     struct smu_11_0_7_powerplay_table *powerplay_table =
0605         (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
0606     uint32_t power_limit, od_percent;
0607     uint16_t *table_member;
0608
0609     GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
0610
0611     if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
0612         power_limit =
0613             table_member[PPT_THROTTLER_PPT0];
0614     }
0615
0616     if (current_power_limit)
0617         *current_power_limit = power_limit;
0618     if (default_power_limit)
0619         *default_power_limit = power_limit;
0620
0621     if (max_power_limit) {
0622         if (smu->od_enabled) {
0623             od_percent =
0624                 le32_to_cpu(powerplay_table->overdrive_table.max[
0625                             SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
0626
0627             dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n",
0628                     od_percent, power_limit);
0629
0630             power_limit *= (100 + od_percent);
0631             power_limit /= 100;
0632         }
0633         *max_power_limit = power_limit;
0634     }
0635
0636     return 0;
0637 }
0638
0639 static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
0640                     uint32_t *apu_percent,
0641                     uint32_t *dgpu_percent)
0642 {
0643     struct smu_table_context *smu_table = &smu->smu_table;
0644     SmuMetrics_V4_t *metrics_v4 =
0645         &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V4);
0646     uint16_t powerRatio = 0;
0647     uint16_t apu_power_limit = 0;
0648     uint16_t dgpu_power_limit = 0;
0649     uint32_t apu_boost = 0;
0650     uint32_t dgpu_boost = 0;
0651     uint32_t cur_power_limit;
0652
0653     if (metrics_v4->ApuSTAPMSmartShiftLimit != 0) {
0654         sienna_cichlid_get_power_limit(smu, &cur_power_limit, NULL, NULL);
0655         apu_power_limit = metrics_v4->ApuSTAPMLimit;
0656         dgpu_power_limit = cur_power_limit;
0657         powerRatio = (((apu_power_limit +
0658                           dgpu_power_limit) * 100) /
0659                           metrics_v4->ApuSTAPMSmartShiftLimit);
0660         if (powerRatio > 100) {
0661             apu_power_limit = (apu_power_limit * 100) /
0662                                      powerRatio;
0663             dgpu_power_limit = (dgpu_power_limit * 100) /
0664                                       powerRatio;
0665         }
0666         if (metrics_v4->AverageApuSocketPower > apu_power_limit &&
0667              apu_power_limit != 0) {
0668             apu_boost = ((metrics_v4->AverageApuSocketPower -
0669                             apu_power_limit) * 100) /
0670                             apu_power_limit;
0671             if (apu_boost > 100)
0672                 apu_boost = 100;
0673         }
0674
0675         if (metrics_v4->AverageSocketPower > dgpu_power_limit &&
0676              dgpu_power_limit != 0) {
0677             dgpu_boost = ((metrics_v4->AverageSocketPower -
0678                              dgpu_power_limit) * 100) /
0679                              dgpu_power_limit;
0680             if (dgpu_boost > 100)
0681                 dgpu_boost = 100;
0682         }
0683
0684         if (dgpu_boost >= apu_boost)
0685             apu_boost = 0;
0686         else
0687             dgpu_boost = 0;
0688     }
0689     *apu_percent = apu_boost;
0690     *dgpu_percent = dgpu_boost;
0691 }
0692
0693 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
0694                            MetricsMember_t member,
0695                            uint32_t *value)
0696 {
0697     struct smu_table_context *smu_table= &smu->smu_table;
0698     SmuMetrics_t *metrics =
0699         &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
0700     SmuMetrics_V2_t *metrics_v2 =
0701         &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
0702     SmuMetrics_V3_t *metrics_v3 =
0703         &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V3);
0704     bool use_metrics_v2 = false;
0705     bool use_metrics_v3 = false;
0706     uint16_t average_gfx_activity;
0707     int ret = 0;
0708     uint32_t apu_percent = 0;
0709     uint32_t dgpu_percent = 0;
0710
0711     switch (smu->adev->ip_versions[MP1_HWIP][0]) {
0712     case IP_VERSION(11, 0, 7):
0713         if (smu->smc_fw_version >= 0x3A4900)
0714             use_metrics_v3 = true;
0715         else if (smu->smc_fw_version >= 0x3A4300)
0716             use_metrics_v2 = true;
0717         break;
0718     case IP_VERSION(11, 0, 11):
0719         if (smu->smc_fw_version >= 0x412D00)
0720             use_metrics_v2 = true;
0721         break;
0722     case IP_VERSION(11, 0, 12):
0723         if (smu->smc_fw_version >= 0x3B2300)
0724             use_metrics_v2 = true;
0725         break;
0726     case IP_VERSION(11, 0, 13):
0727         if (smu->smc_fw_version >= 0x491100)
0728             use_metrics_v2 = true;
0729         break;
0730     default:
0731         break;
0732     }
0733
0734     ret = smu_cmn_get_metrics_table(smu,
0735                     NULL,
0736                     false);
0737     if (ret)
0738         return ret;
0739
0740     switch (member) {
0741     case METRICS_CURR_GFXCLK:
0742         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
0743             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
0744             metrics->CurrClock[PPCLK_GFXCLK];
0745         break;
0746     case METRICS_CURR_SOCCLK:
0747         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
0748             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
0749             metrics->CurrClock[PPCLK_SOCCLK];
0750         break;
0751     case METRICS_CURR_UCLK:
0752         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
0753             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
0754             metrics->CurrClock[PPCLK_UCLK];
0755         break;
0756     case METRICS_CURR_VCLK:
0757         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
0758             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
0759             metrics->CurrClock[PPCLK_VCLK_0];
0760         break;
0761     case METRICS_CURR_VCLK1:
0762         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
0763             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
0764             metrics->CurrClock[PPCLK_VCLK_1];
0765         break;
0766     case METRICS_CURR_DCLK:
0767         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
0768             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
0769             metrics->CurrClock[PPCLK_DCLK_0];
0770         break;
0771     case METRICS_CURR_DCLK1:
0772         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
0773             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
0774             metrics->CurrClock[PPCLK_DCLK_1];
0775         break;
0776     case METRICS_CURR_DCEFCLK:
0777         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCEFCLK] :
0778             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
0779             metrics->CurrClock[PPCLK_DCEFCLK];
0780         break;
0781     case METRICS_CURR_FCLK:
0782         *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_FCLK] :
0783             use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
0784             metrics->CurrClock[PPCLK_FCLK];
0785         break;
0786     case METRICS_AVERAGE_GFXCLK:
0787         average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
0788             use_metrics_v2 ? metrics_v2->AverageGfxActivity :
0789             metrics->AverageGfxActivity;
0790         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
0791             *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
0792                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
0793                 metrics->AverageGfxclkFrequencyPostDs;
0794         else
0795             *value = use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
0796                 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
0797                 metrics->AverageGfxclkFrequencyPreDs;
0798         break;
0799     case METRICS_AVERAGE_FCLK:
0800         *value = use_metrics_v3 ? metrics_v3->AverageFclkFrequencyPostDs :
0801             use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
0802             metrics->AverageFclkFrequencyPostDs;
0803         break;
0804     case METRICS_AVERAGE_UCLK:
0805         *value = use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
0806             use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
0807             metrics->AverageUclkFrequencyPostDs;
0808         break;
0809     case METRICS_AVERAGE_GFXACTIVITY:
0810         *value = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
0811             use_metrics_v2 ? metrics_v2->AverageGfxActivity :
0812             metrics->AverageGfxActivity;
0813         break;
0814     case METRICS_AVERAGE_MEMACTIVITY:
0815         *value = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
0816             use_metrics_v2 ? metrics_v2->AverageUclkActivity :
0817             metrics->AverageUclkActivity;
0818         break;
0819     case METRICS_AVERAGE_SOCKETPOWER:
0820         *value = use_metrics_v3 ? metrics_v3->AverageSocketPower << 8 :
0821             use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
0822             metrics->AverageSocketPower << 8;
0823         break;
0824     case METRICS_TEMPERATURE_EDGE:
0825         *value = (use_metrics_v3 ? metrics_v3->TemperatureEdge :
0826             use_metrics_v2 ? metrics_v2->TemperatureEdge :
0827             metrics->TemperatureEdge) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
0828         break;
0829     case METRICS_TEMPERATURE_HOTSPOT:
0830         *value = (use_metrics_v3 ? metrics_v3->TemperatureHotspot :
0831             use_metrics_v2 ? metrics_v2->TemperatureHotspot :
0832             metrics->TemperatureHotspot) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
0833         break;
0834     case METRICS_TEMPERATURE_MEM:
0835         *value = (use_metrics_v3 ? metrics_v3->TemperatureMem :
0836             use_metrics_v2 ? metrics_v2->TemperatureMem :
0837             metrics->TemperatureMem) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
0838         break;
0839     case METRICS_TEMPERATURE_VRGFX:
0840         *value = (use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
0841             use_metrics_v2 ? metrics_v2->TemperatureVrGfx :
0842             metrics->TemperatureVrGfx) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
0843         break;
0844     case METRICS_TEMPERATURE_VRSOC:
0845         *value = (use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
0846             use_metrics_v2 ? metrics_v2->TemperatureVrSoc :
0847             metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
0848         break;
0849     case METRICS_THROTTLER_STATUS:
0850         *value = sienna_cichlid_get_throttler_status_locked(smu);
0851         break;
0852     case METRICS_CURR_FANSPEED:
0853         *value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
0854             use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
0855         break;
0856     case METRICS_UNIQUE_ID_UPPER32:
0857         /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
0858         *value = use_metrics_v3 ? metrics_v3->PublicSerialNumUpper32 : 0;
0859         break;
0860     case METRICS_UNIQUE_ID_LOWER32:
0861         /* Only supported in 0x3A5300+, metrics_v3 requires 0x3A4900+ */
0862         *value = use_metrics_v3 ? metrics_v3->PublicSerialNumLower32 : 0;
0863         break;
0864     case METRICS_SS_APU_SHARE:
0865         sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
0866         *value = apu_percent;
0867         break;
0868     case METRICS_SS_DGPU_SHARE:
0869         sienna_cichlid_get_smartshift_power_percentage(smu, &apu_percent, &dgpu_percent);
0870         *value = dgpu_percent;
0871         break;
0872
0873     default:
0874         *value = UINT_MAX;
0875         break;
0876     }
0877
0878     return ret;
0879
0880 }
0881
0882 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
0883 {
0884     struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
0885
0886     smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
0887                        GFP_KERNEL);
0888     if (!smu_dpm->dpm_context)
0889         return -ENOMEM;
0890
0891     smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
0892
0893     return 0;
0894 }
0895
0896 static void sienna_cichlid_stb_init(struct smu_context *smu);
0897
0898 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
0899 {
0900     struct amdgpu_device *adev = smu->adev;
0901     int ret = 0;
0902
0903     ret = sienna_cichlid_tables_init(smu);
0904     if (ret)
0905         return ret;
0906
0907     ret = sienna_cichlid_allocate_dpm_context(smu);
0908     if (ret)
0909         return ret;
0910
0911     if (!amdgpu_sriov_vf(adev))
0912         sienna_cichlid_stb_init(smu);
0913
0914     return smu_v11_0_init_smc_tables(smu);
0915 }
0916
0917 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
0918 {
0919     struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
0920     struct smu_11_0_dpm_table *dpm_table;
0921     struct amdgpu_device *adev = smu->adev;
0922     int i, ret = 0;
0923     DpmDescriptor_t *table_member;
0924
0925     /* socclk dpm table setup */
0926     dpm_table = &dpm_context->dpm_tables.soc_table;
0927     GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
0928     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
0929         ret = smu_v11_0_set_single_dpm_table(smu,
0930                              SMU_SOCCLK,
0931                              dpm_table);
0932         if (ret)
0933             return ret;
0934         dpm_table->is_fine_grained =
0935             !table_member[PPCLK_SOCCLK].SnapToDiscrete;
0936     } else {
0937         dpm_table->count = 1;
0938         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
0939         dpm_table->dpm_levels[0].enabled = true;
0940         dpm_table->min = dpm_table->dpm_levels[0].value;
0941         dpm_table->max = dpm_table->dpm_levels[0].value;
0942     }
0943
0944     /* gfxclk dpm table setup */
0945     dpm_table = &dpm_context->dpm_tables.gfx_table;
0946     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
0947         ret = smu_v11_0_set_single_dpm_table(smu,
0948                              SMU_GFXCLK,
0949                              dpm_table);
0950         if (ret)
0951             return ret;
0952         dpm_table->is_fine_grained =
0953             !table_member[PPCLK_GFXCLK].SnapToDiscrete;
0954     } else {
0955         dpm_table->count = 1;
0956         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
0957         dpm_table->dpm_levels[0].enabled = true;
0958         dpm_table->min = dpm_table->dpm_levels[0].value;
0959         dpm_table->max = dpm_table->dpm_levels[0].value;
0960     }
0961
0962     /* uclk dpm table setup */
0963     dpm_table = &dpm_context->dpm_tables.uclk_table;
0964     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
0965         ret = smu_v11_0_set_single_dpm_table(smu,
0966                              SMU_UCLK,
0967                              dpm_table);
0968         if (ret)
0969             return ret;
0970         dpm_table->is_fine_grained =
0971             !table_member[PPCLK_UCLK].SnapToDiscrete;
0972     } else {
0973         dpm_table->count = 1;
0974         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
0975         dpm_table->dpm_levels[0].enabled = true;
0976         dpm_table->min = dpm_table->dpm_levels[0].value;
0977         dpm_table->max = dpm_table->dpm_levels[0].value;
0978     }
0979
0980     /* fclk dpm table setup */
0981     dpm_table = &dpm_context->dpm_tables.fclk_table;
0982     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
0983         ret = smu_v11_0_set_single_dpm_table(smu,
0984                              SMU_FCLK,
0985                              dpm_table);
0986         if (ret)
0987             return ret;
0988         dpm_table->is_fine_grained =
0989             !table_member[PPCLK_FCLK].SnapToDiscrete;
0990     } else {
0991         dpm_table->count = 1;
0992         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
0993         dpm_table->dpm_levels[0].enabled = true;
0994         dpm_table->min = dpm_table->dpm_levels[0].value;
0995         dpm_table->max = dpm_table->dpm_levels[0].value;
0996     }
0997
0998     /* vclk0/1 dpm table setup */
0999     for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1000         if (adev->vcn.harvest_config & (1 << i))
1001             continue;
1002
1003         dpm_table = &dpm_context->dpm_tables.vclk_table;
1004         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1005             ret = smu_v11_0_set_single_dpm_table(smu,
1006                                  i ? SMU_VCLK1 : SMU_VCLK,
1007                                  dpm_table);
1008             if (ret)
1009                 return ret;
1010             dpm_table->is_fine_grained =
1011                 !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete;
1012         } else {
1013             dpm_table->count = 1;
1014             dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1015             dpm_table->dpm_levels[0].enabled = true;
1016             dpm_table->min = dpm_table->dpm_levels[0].value;
1017             dpm_table->max = dpm_table->dpm_levels[0].value;
1018         }
1019     }
1020
1021     /* dclk0/1 dpm table setup */
1022     for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1023         if (adev->vcn.harvest_config & (1 << i))
1024             continue;
1025         dpm_table = &dpm_context->dpm_tables.dclk_table;
1026         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1027             ret = smu_v11_0_set_single_dpm_table(smu,
1028                                  i ? SMU_DCLK1 : SMU_DCLK,
1029                                  dpm_table);
1030             if (ret)
1031                 return ret;
1032             dpm_table->is_fine_grained =
1033                 !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete;
1034         } else {
1035             dpm_table->count = 1;
1036             dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1037             dpm_table->dpm_levels[0].enabled = true;
1038             dpm_table->min = dpm_table->dpm_levels[0].value;
1039             dpm_table->max = dpm_table->dpm_levels[0].value;
1040         }
1041     }
1042
1043     /* dcefclk dpm table setup */
1044     dpm_table = &dpm_context->dpm_tables.dcef_table;
1045     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1046         ret = smu_v11_0_set_single_dpm_table(smu,
1047                              SMU_DCEFCLK,
1048                              dpm_table);
1049         if (ret)
1050             return ret;
1051         dpm_table->is_fine_grained =
1052             !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
1053     } else {
1054         dpm_table->count = 1;
1055         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1056         dpm_table->dpm_levels[0].enabled = true;
1057         dpm_table->min = dpm_table->dpm_levels[0].value;
1058         dpm_table->max = dpm_table->dpm_levels[0].value;
1059     }
1060
1061     /* pixelclk dpm table setup */
1062     dpm_table = &dpm_context->dpm_tables.pixel_table;
1063     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1064         ret = smu_v11_0_set_single_dpm_table(smu,
1065                              SMU_PIXCLK,
1066                              dpm_table);
1067         if (ret)
1068             return ret;
1069         dpm_table->is_fine_grained =
1070             !table_member[PPCLK_PIXCLK].SnapToDiscrete;
1071     } else {
1072         dpm_table->count = 1;
1073         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1074         dpm_table->dpm_levels[0].enabled = true;
1075         dpm_table->min = dpm_table->dpm_levels[0].value;
1076         dpm_table->max = dpm_table->dpm_levels[0].value;
1077     }
1078
1079     /* displayclk dpm table setup */
1080     dpm_table = &dpm_context->dpm_tables.display_table;
1081     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1082         ret = smu_v11_0_set_single_dpm_table(smu,
1083                              SMU_DISPCLK,
1084                              dpm_table);
1085         if (ret)
1086             return ret;
1087         dpm_table->is_fine_grained =
1088             !table_member[PPCLK_DISPCLK].SnapToDiscrete;
1089     } else {
1090         dpm_table->count = 1;
1091         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1092         dpm_table->dpm_levels[0].enabled = true;
1093         dpm_table->min = dpm_table->dpm_levels[0].value;
1094         dpm_table->max = dpm_table->dpm_levels[0].value;
1095     }
1096
1097     /* phyclk dpm table setup */
1098     dpm_table = &dpm_context->dpm_tables.phy_table;
1099     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1100         ret = smu_v11_0_set_single_dpm_table(smu,
1101                              SMU_PHYCLK,
1102                              dpm_table);
1103         if (ret)
1104             return ret;
1105         dpm_table->is_fine_grained =
1106             !table_member[PPCLK_PHYCLK].SnapToDiscrete;
1107     } else {
1108         dpm_table->count = 1;
1109         dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1110         dpm_table->dpm_levels[0].enabled = true;
1111         dpm_table->min = dpm_table->dpm_levels[0].value;
1112         dpm_table->max = dpm_table->dpm_levels[0].value;
1113     }
1114
1115     return 0;
1116 }
1117
1118 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1119 {
1120     struct amdgpu_device *adev = smu->adev;
1121     int i, ret = 0;
1122
1123     for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1124         if (adev->vcn.harvest_config & (1 << i))
1125             continue;
1126         /* vcn dpm on is a prerequisite for vcn power gate messages */
1127         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1128             ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
1129                                   SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn,
1130                                   0x10000 * i, NULL);
1131             if (ret)
1132                 return ret;
1133         }
1134     }
1135
1136     return ret;
1137 }
1138
1139 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1140 {
1141     int ret = 0;
1142
1143     if (enable) {
1144         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1145             ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
1146             if (ret)
1147                 return ret;
1148         }
1149     } else {
1150         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
1151             ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
1152             if (ret)
1153                 return ret;
1154         }
1155     }
1156
1157     return ret;
1158 }
1159
1160 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
1161                        enum smu_clk_type clk_type,
1162                        uint32_t *value)
1163 {
1164     MetricsMember_t member_type;
1165     int clk_id = 0;
1166
1167     clk_id = smu_cmn_to_asic_specific_index(smu,
1168                         CMN2ASIC_MAPPING_CLK,
1169                         clk_type);
1170     if (clk_id < 0)
1171         return clk_id;
1172
1173     switch (clk_id) {
1174     case PPCLK_GFXCLK:
1175         member_type = METRICS_CURR_GFXCLK;
1176         break;
1177     case PPCLK_UCLK:
1178         member_type = METRICS_CURR_UCLK;
1179         break;
1180     case PPCLK_SOCCLK:
1181         member_type = METRICS_CURR_SOCCLK;
1182         break;
1183     case PPCLK_FCLK:
1184         member_type = METRICS_CURR_FCLK;
1185         break;
1186     case PPCLK_VCLK_0:
1187         member_type = METRICS_CURR_VCLK;
1188         break;
1189     case PPCLK_VCLK_1:
1190         member_type = METRICS_CURR_VCLK1;
1191         break;
1192     case PPCLK_DCLK_0:
1193         member_type = METRICS_CURR_DCLK;
1194         break;
1195     case PPCLK_DCLK_1:
1196         member_type = METRICS_CURR_DCLK1;
1197         break;
1198     case PPCLK_DCEFCLK:
1199         member_type = METRICS_CURR_DCEFCLK;
1200         break;
1201     default:
1202         return -EINVAL;
1203     }
1204
1205     return sienna_cichlid_get_smu_metrics_data(smu,
1206                            member_type,
1207                            value);
1208
1209 }
1210
1211 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1212 {
1213     DpmDescriptor_t *dpm_desc = NULL;
1214     DpmDescriptor_t *table_member;
1215     uint32_t clk_index = 0;
1216
1217     GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1218     clk_index = smu_cmn_to_asic_specific_index(smu,
1219                            CMN2ASIC_MAPPING_CLK,
1220                            clk_type);
1221     dpm_desc = &table_member[clk_index];
1222
1223     /* 0 - Fine grained DPM, 1 - Discrete DPM */
1224     return dpm_desc->SnapToDiscrete == 0;
1225 }
1226
1227 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1228                            enum SMU_11_0_7_ODFEATURE_CAP cap)
1229 {
1230     return od_table->cap[cap];
1231 }
1232
1233 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1234                         enum SMU_11_0_7_ODSETTING_ID setting,
1235                         uint32_t *min, uint32_t *max)
1236 {
1237     if (min)
1238         *min = od_table->min[setting];
1239     if (max)
1240         *max = od_table->max[setting];
1241 }
1242
1243 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1244             enum smu_clk_type clk_type, char *buf)
1245 {
1246     struct amdgpu_device *adev = smu->adev;
1247     struct smu_table_context *table_context = &smu->smu_table;
1248     struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1249     struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1250     uint16_t *table_member;
1251
1252     struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1253     OverDriveTable_t *od_table =
1254         (OverDriveTable_t *)table_context->overdrive_table;
1255     int i, size = 0, ret = 0;
1256     uint32_t cur_value = 0, value = 0, count = 0;
1257     uint32_t freq_values[3] = {0};
1258     uint32_t mark_index = 0;
1259     uint32_t gen_speed, lane_width;
1260     uint32_t min_value, max_value;
1261     uint32_t smu_version;
1262
1263     smu_cmn_get_sysfs_buf(&buf, &size);
1264
1265     switch (clk_type) {
1266     case SMU_GFXCLK:
1267     case SMU_SCLK:
1268     case SMU_SOCCLK:
1269     case SMU_MCLK:
1270     case SMU_UCLK:
1271     case SMU_FCLK:
1272     case SMU_VCLK:
1273     case SMU_VCLK1:
1274     case SMU_DCLK:
1275     case SMU_DCLK1:
1276     case SMU_DCEFCLK:
1277         ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1278         if (ret)
1279             goto print_clk_out;
1280
1281         ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1282         if (ret)
1283             goto print_clk_out;
1284
1285         if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1286             for (i = 0; i < count; i++) {
1287                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1288                 if (ret)
1289                     goto print_clk_out;
1290
1291                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1292                         cur_value == value ? "*" : "");
1293             }
1294         } else {
1295             ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1296             if (ret)
1297                 goto print_clk_out;
1298             ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1299             if (ret)
1300                 goto print_clk_out;
1301
1302             freq_values[1] = cur_value;
1303             mark_index = cur_value == freq_values[0] ? 0 :
1304                      cur_value == freq_values[2] ? 2 : 1;
1305
1306             count = 3;
1307             if (mark_index != 1) {
1308                 count = 2;
1309                 freq_values[1] = freq_values[2];
1310             }
1311
1312             for (i = 0; i < count; i++) {
1313                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1314                         cur_value  == freq_values[i] ? "*" : "");
1315             }
1316
1317         }
1318         break;
1319     case SMU_PCIE:
1320         gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1321         lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1322         GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1323         for (i = 0; i < NUM_LINK_LEVELS; i++)
1324             size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1325                     (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1326                     (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1327                     (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1328                     (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1329                     (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1330                     (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1331                     (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1332                     (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1333                     (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1334                     (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1335                     table_member[i],
1336                     (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1337                     (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1338                     "*" : "");
1339         break;
1340     case SMU_OD_SCLK:
1341         if (!smu->od_enabled || !od_table || !od_settings)
1342             break;
1343
1344         if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1345             break;
1346
1347         size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1348         size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1349         break;
1350
1351     case SMU_OD_MCLK:
1352         if (!smu->od_enabled || !od_table || !od_settings)
1353             break;
1354
1355         if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1356             break;
1357
1358         size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1359         size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1360         break;
1361
1362     case SMU_OD_VDDGFX_OFFSET:
1363         if (!smu->od_enabled || !od_table || !od_settings)
1364             break;
1365
1366         /*
1367          * OD GFX Voltage Offset functionality is supported only by 58.41.0
1368          * and onwards SMU firmwares.
1369          */
1370         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1371         if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
1372              (smu_version < 0x003a2900))
1373             break;
1374
1375         size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1376         size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1377         break;
1378
1379     case SMU_OD_RANGE:
1380         if (!smu->od_enabled || !od_table || !od_settings)
1381             break;
1382
1383         size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1384
1385         if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1386             sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1387                                 &min_value, NULL);
1388             sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1389                                 NULL, &max_value);
1390             size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1391                     min_value, max_value);
1392         }
1393
1394         if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1395             sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1396                                 &min_value, NULL);
1397             sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1398                                 NULL, &max_value);
1399             size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1400                     min_value, max_value);
1401         }
1402         break;
1403
1404     default:
1405         break;
1406     }
1407
1408 print_clk_out:
1409     return size;
1410 }
1411
1412 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1413                    enum smu_clk_type clk_type, uint32_t mask)
1414 {
1415     int ret = 0;
1416     uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1417
1418     soft_min_level = mask ? (ffs(mask) - 1) : 0;
1419     soft_max_level = mask ? (fls(mask) - 1) : 0;
1420
1421     switch (clk_type) {
1422     case SMU_GFXCLK:
1423     case SMU_SCLK:
1424     case SMU_SOCCLK:
1425     case SMU_MCLK:
1426     case SMU_UCLK:
1427     case SMU_FCLK:
1428         /* There is only 2 levels for fine grained DPM */
1429         if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1430             soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1431             soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1432         }
1433
1434         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1435         if (ret)
1436             goto forec_level_out;
1437
1438         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1439         if (ret)
1440             goto forec_level_out;
1441
1442         ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1443         if (ret)
1444             goto forec_level_out;
1445         break;
1446     case SMU_DCEFCLK:
1447         dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1448         break;
1449     default:
1450         break;
1451     }
1452
1453 forec_level_out:
1454     return 0;
1455 }
1456
1457 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1458 {
1459     struct smu_11_0_dpm_context *dpm_context =
1460                 smu->smu_dpm.dpm_context;
1461     struct smu_11_0_dpm_table *gfx_table =
1462                 &dpm_context->dpm_tables.gfx_table;
1463     struct smu_11_0_dpm_table *mem_table =
1464                 &dpm_context->dpm_tables.uclk_table;
1465     struct smu_11_0_dpm_table *soc_table =
1466                 &dpm_context->dpm_tables.soc_table;
1467     struct smu_umd_pstate_table *pstate_table =
1468                 &smu->pstate_table;
1469     struct amdgpu_device *adev = smu->adev;
1470
1471     pstate_table->gfxclk_pstate.min = gfx_table->min;
1472     pstate_table->gfxclk_pstate.peak = gfx_table->max;
1473
1474     pstate_table->uclk_pstate.min = mem_table->min;
1475     pstate_table->uclk_pstate.peak = mem_table->max;
1476
1477     pstate_table->socclk_pstate.min = soc_table->min;
1478     pstate_table->socclk_pstate.peak = soc_table->max;
1479
1480     switch (adev->ip_versions[MP1_HWIP][0]) {
1481     case IP_VERSION(11, 0, 7):
1482     case IP_VERSION(11, 0, 11):
1483         pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1484         pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1485         pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1486         break;
1487     case IP_VERSION(11, 0, 12):
1488         pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;
1489         pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;
1490         pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;
1491         break;
1492     case IP_VERSION(11, 0, 13):
1493         pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;
1494         pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;
1495         pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;
1496         break;
1497     default:
1498         break;
1499     }
1500
1501     return 0;
1502 }
1503
1504 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1505 {
1506     int ret = 0;
1507     uint32_t max_freq = 0;
1508
1509     /* Sienna_Cichlid do not support to change display num currently */
1510     return 0;
1511 #if 0
1512     ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1513     if (ret)
1514         return ret;
1515 #endif
1516
1517     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1518         ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1519         if (ret)
1520             return ret;
1521         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1522         if (ret)
1523             return ret;
1524     }
1525
1526     return ret;
1527 }
1528
1529 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1530 {
1531     int ret = 0;
1532
1533     if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1534         smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1535         smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1536 #if 0
1537         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1538                           smu->display_config->num_display,
1539                           NULL);
1540 #endif
1541         if (ret)
1542             return ret;
1543     }
1544
1545     return ret;
1546 }
1547
1548 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1549 {
1550     int ret = 0;
1551     uint64_t feature_enabled;
1552
1553     ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1554     if (ret)
1555         return false;
1556
1557     return !!(feature_enabled & SMC_DPM_FEATURE);
1558 }
1559
1560 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1561                         uint32_t *speed)
1562 {
1563     if (!speed)
1564         return -EINVAL;
1565
1566     /*
1567      * For Sienna_Cichlid and later, the fan speed(rpm) reported
1568      * by pmfw is always trustable(even when the fan control feature
1569      * disabled or 0 RPM kicked in).
1570      */
1571     return sienna_cichlid_get_smu_metrics_data(smu,
1572                            METRICS_CURR_FANSPEED,
1573                            speed);
1574 }
1575
1576 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1577 {
1578     uint16_t *table_member;
1579
1580     GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1581     smu->fan_max_rpm = *table_member;
1582
1583     return 0;
1584 }
1585
1586 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1587 {
1588     DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1589     DpmActivityMonitorCoeffInt_t *activity_monitor =
1590         &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1591     uint32_t i, size = 0;
1592     int16_t workload_type = 0;
1593     static const char *title[] = {
1594             "PROFILE_INDEX(NAME)",
1595             "CLOCK_TYPE(NAME)",
1596             "FPS",
1597             "MinFreqType",
1598             "MinActiveFreqType",
1599             "MinActiveFreq",
1600             "BoosterFreqType",
1601             "BoosterFreq",
1602             "PD_Data_limit_c",
1603             "PD_Data_error_coeff",
1604             "PD_Data_error_rate_coeff"};
1605     int result = 0;
1606
1607     if (!buf)
1608         return -EINVAL;
1609
1610     size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1611             title[0], title[1], title[2], title[3], title[4], title[5],
1612             title[6], title[7], title[8], title[9], title[10]);
1613
1614     for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1615         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1616         workload_type = smu_cmn_to_asic_specific_index(smu,
1617                                    CMN2ASIC_MAPPING_WORKLOAD,
1618                                    i);
1619         if (workload_type < 0)
1620             return -EINVAL;
1621
1622         result = smu_cmn_update_table(smu,
1623                       SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1624                       (void *)(&activity_monitor_external), false);
1625         if (result) {
1626             dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1627             return result;
1628         }
1629
1630         size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1631             i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1632
1633         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1634             " ",
1635             0,
1636             "GFXCLK",
1637             activity_monitor->Gfx_FPS,
1638             activity_monitor->Gfx_MinFreqStep,
1639             activity_monitor->Gfx_MinActiveFreqType,
1640             activity_monitor->Gfx_MinActiveFreq,
1641             activity_monitor->Gfx_BoosterFreqType,
1642             activity_monitor->Gfx_BoosterFreq,
1643             activity_monitor->Gfx_PD_Data_limit_c,
1644             activity_monitor->Gfx_PD_Data_error_coeff,
1645             activity_monitor->Gfx_PD_Data_error_rate_coeff);
1646
1647         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1648             " ",
1649             1,
1650             "SOCCLK",
1651             activity_monitor->Fclk_FPS,
1652             activity_monitor->Fclk_MinFreqStep,
1653             activity_monitor->Fclk_MinActiveFreqType,
1654             activity_monitor->Fclk_MinActiveFreq,
1655             activity_monitor->Fclk_BoosterFreqType,
1656             activity_monitor->Fclk_BoosterFreq,
1657             activity_monitor->Fclk_PD_Data_limit_c,
1658             activity_monitor->Fclk_PD_Data_error_coeff,
1659             activity_monitor->Fclk_PD_Data_error_rate_coeff);
1660
1661         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1662             " ",
1663             2,
1664             "MEMLK",
1665             activity_monitor->Mem_FPS,
1666             activity_monitor->Mem_MinFreqStep,
1667             activity_monitor->Mem_MinActiveFreqType,
1668             activity_monitor->Mem_MinActiveFreq,
1669             activity_monitor->Mem_BoosterFreqType,
1670             activity_monitor->Mem_BoosterFreq,
1671             activity_monitor->Mem_PD_Data_limit_c,
1672             activity_monitor->Mem_PD_Data_error_coeff,
1673             activity_monitor->Mem_PD_Data_error_rate_coeff);
1674     }
1675
1676     return size;
1677 }
1678
1679 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1680 {
1681
1682     DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1683     DpmActivityMonitorCoeffInt_t *activity_monitor =
1684         &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1685     int workload_type, ret = 0;
1686
1687     smu->power_profile_mode = input[size];
1688
1689     if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1690         dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1691         return -EINVAL;
1692     }
1693
1694     if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1695
1696         ret = smu_cmn_update_table(smu,
1697                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1698                        (void *)(&activity_monitor_external), false);
1699         if (ret) {
1700             dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1701             return ret;
1702         }
1703
1704         switch (input[0]) {
1705         case 0: /* Gfxclk */
1706             activity_monitor->Gfx_FPS = input[1];
1707             activity_monitor->Gfx_MinFreqStep = input[2];
1708             activity_monitor->Gfx_MinActiveFreqType = input[3];
1709             activity_monitor->Gfx_MinActiveFreq = input[4];
1710             activity_monitor->Gfx_BoosterFreqType = input[5];
1711             activity_monitor->Gfx_BoosterFreq = input[6];
1712             activity_monitor->Gfx_PD_Data_limit_c = input[7];
1713             activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1714             activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1715             break;
1716         case 1: /* Socclk */
1717             activity_monitor->Fclk_FPS = input[1];
1718             activity_monitor->Fclk_MinFreqStep = input[2];
1719             activity_monitor->Fclk_MinActiveFreqType = input[3];
1720             activity_monitor->Fclk_MinActiveFreq = input[4];
1721             activity_monitor->Fclk_BoosterFreqType = input[5];
1722             activity_monitor->Fclk_BoosterFreq = input[6];
1723             activity_monitor->Fclk_PD_Data_limit_c = input[7];
1724             activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1725             activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1726             break;
1727         case 2: /* Memlk */
1728             activity_monitor->Mem_FPS = input[1];
1729             activity_monitor->Mem_MinFreqStep = input[2];
1730             activity_monitor->Mem_MinActiveFreqType = input[3];
1731             activity_monitor->Mem_MinActiveFreq = input[4];
1732             activity_monitor->Mem_BoosterFreqType = input[5];
1733             activity_monitor->Mem_BoosterFreq = input[6];
1734             activity_monitor->Mem_PD_Data_limit_c = input[7];
1735             activity_monitor->Mem_PD_Data_error_coeff = input[8];
1736             activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1737             break;
1738         }
1739
1740         ret = smu_cmn_update_table(smu,
1741                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1742                        (void *)(&activity_monitor_external), true);
1743         if (ret) {
1744             dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1745             return ret;
1746         }
1747     }
1748
1749     /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1750     workload_type = smu_cmn_to_asic_specific_index(smu,
1751                                CMN2ASIC_MAPPING_WORKLOAD,
1752                                smu->power_profile_mode);
1753     if (workload_type < 0)
1754         return -EINVAL;
1755     smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1756                     1 << workload_type, NULL);
1757
1758     return ret;
1759 }
1760
1761 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1762 {
1763     struct smu_clocks min_clocks = {0};
1764     struct pp_display_clock_request clock_req;
1765     int ret = 0;
1766
1767     min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1768     min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1769     min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1770
1771     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1772         clock_req.clock_type = amd_pp_dcef_clock;
1773         clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1774
1775         ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1776         if (!ret) {
1777             if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1778                 ret = smu_cmn_send_smc_msg_with_param(smu,
1779                                   SMU_MSG_SetMinDeepSleepDcefclk,
1780                                   min_clocks.dcef_clock_in_sr/100,
1781                                   NULL);
1782                 if (ret) {
1783                     dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1784                     return ret;
1785                 }
1786             }
1787         } else {
1788             dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1789         }
1790     }
1791
1792     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1793         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1794         if (ret) {
1795             dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1796             return ret;
1797         }
1798     }
1799
1800     return 0;
1801 }
1802
1803 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1804                            struct pp_smu_wm_range_sets *clock_ranges)
1805 {
1806     Watermarks_t *table = smu->smu_table.watermarks_table;
1807     int ret = 0;
1808     int i;
1809
1810     if (clock_ranges) {
1811         if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1812             clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1813             return -EINVAL;
1814
1815         for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1816             table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1817                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1818             table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1819                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1820             table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1821                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1822             table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1823                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1824
1825             table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1826                 clock_ranges->reader_wm_sets[i].wm_inst;
1827         }
1828
1829         for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1830             table->WatermarkRow[WM_SOCCLK][i].MinClock =
1831                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1832             table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1833                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1834             table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1835                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1836             table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1837                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1838
1839             table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1840                 clock_ranges->writer_wm_sets[i].wm_inst;
1841         }
1842
1843         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1844     }
1845
1846     if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1847          !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1848         ret = smu_cmn_write_watermarks_table(smu);
1849         if (ret) {
1850             dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1851             return ret;
1852         }
1853         smu->watermarks_bitmap |= WATERMARKS_LOADED;
1854     }
1855
1856     return 0;
1857 }
1858
1859 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1860                  enum amd_pp_sensors sensor,
1861                  void *data, uint32_t *size)
1862 {
1863     int ret = 0;
1864     uint16_t *temp;
1865     struct amdgpu_device *adev = smu->adev;
1866
1867     if(!data || !size)
1868         return -EINVAL;
1869
1870     switch (sensor) {
1871     case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1872         GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1873         *(uint16_t *)data = *temp;
1874         *size = 4;
1875         break;
1876     case AMDGPU_PP_SENSOR_MEM_LOAD:
1877         ret = sienna_cichlid_get_smu_metrics_data(smu,
1878                               METRICS_AVERAGE_MEMACTIVITY,
1879                               (uint32_t *)data);
1880         *size = 4;
1881         break;
1882     case AMDGPU_PP_SENSOR_GPU_LOAD:
1883         ret = sienna_cichlid_get_smu_metrics_data(smu,
1884                               METRICS_AVERAGE_GFXACTIVITY,
1885                               (uint32_t *)data);
1886         *size = 4;
1887         break;
1888     case AMDGPU_PP_SENSOR_GPU_POWER:
1889         ret = sienna_cichlid_get_smu_metrics_data(smu,
1890                               METRICS_AVERAGE_SOCKETPOWER,
1891                               (uint32_t *)data);
1892         *size = 4;
1893         break;
1894     case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1895         ret = sienna_cichlid_get_smu_metrics_data(smu,
1896                               METRICS_TEMPERATURE_HOTSPOT,
1897                               (uint32_t *)data);
1898         *size = 4;
1899         break;
1900     case AMDGPU_PP_SENSOR_EDGE_TEMP:
1901         ret = sienna_cichlid_get_smu_metrics_data(smu,
1902                               METRICS_TEMPERATURE_EDGE,
1903                               (uint32_t *)data);
1904         *size = 4;
1905         break;
1906     case AMDGPU_PP_SENSOR_MEM_TEMP:
1907         ret = sienna_cichlid_get_smu_metrics_data(smu,
1908                               METRICS_TEMPERATURE_MEM,
1909                               (uint32_t *)data);
1910         *size = 4;
1911         break;
1912     case AMDGPU_PP_SENSOR_GFX_MCLK:
1913         ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1914         *(uint32_t *)data *= 100;
1915         *size = 4;
1916         break;
1917     case AMDGPU_PP_SENSOR_GFX_SCLK:
1918         ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1919         *(uint32_t *)data *= 100;
1920         *size = 4;
1921         break;
1922     case AMDGPU_PP_SENSOR_VDDGFX:
1923         ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1924         *size = 4;
1925         break;
1926     case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1927         if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1928             ret = sienna_cichlid_get_smu_metrics_data(smu,
1929                         METRICS_SS_APU_SHARE, (uint32_t *)data);
1930             *size = 4;
1931         } else {
1932             ret = -EOPNOTSUPP;
1933         }
1934         break;
1935     case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1936         if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7)) {
1937             ret = sienna_cichlid_get_smu_metrics_data(smu,
1938                         METRICS_SS_DGPU_SHARE, (uint32_t *)data);
1939             *size = 4;
1940         } else {
1941             ret = -EOPNOTSUPP;
1942         }
1943         break;
1944     default:
1945         ret = -EOPNOTSUPP;
1946         break;
1947     }
1948
1949     return ret;
1950 }
1951
1952 static void sienna_cichlid_get_unique_id(struct smu_context *smu)
1953 {
1954     struct amdgpu_device *adev = smu->adev;
1955     uint32_t upper32 = 0, lower32 = 0;
1956
1957     /* Only supported as of version 0.58.83.0 and only on Sienna Cichlid */
1958     if (smu->smc_fw_version < 0x3A5300 ||
1959         smu->adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
1960         return;
1961
1962     if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_UPPER32, &upper32))
1963         goto out;
1964     if (sienna_cichlid_get_smu_metrics_data(smu, METRICS_UNIQUE_ID_LOWER32, &lower32))
1965         goto out;
1966
1967 out:
1968
1969     adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1970     if (adev->serial[0] == '\0')
1971         sprintf(adev->serial, "%016llx", adev->unique_id);
1972 }
1973
1974 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1975 {
1976     uint32_t num_discrete_levels = 0;
1977     uint16_t *dpm_levels = NULL;
1978     uint16_t i = 0;
1979     struct smu_table_context *table_context = &smu->smu_table;
1980     DpmDescriptor_t *table_member1;
1981     uint16_t *table_member2;
1982
1983     if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1984         return -EINVAL;
1985
1986     GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1987     num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1988     GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1989     dpm_levels = table_member2;
1990
1991     if (num_discrete_levels == 0 || dpm_levels == NULL)
1992         return -EINVAL;
1993
1994     *num_states = num_discrete_levels;
1995     for (i = 0; i < num_discrete_levels; i++) {
1996         /* convert to khz */
1997         *clocks_in_khz = (*dpm_levels) * 1000;
1998         clocks_in_khz++;
1999         dpm_levels++;
2000     }
2001
2002     return 0;
2003 }
2004
2005 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
2006                         struct smu_temperature_range *range)
2007 {
2008     struct smu_table_context *table_context = &smu->smu_table;
2009     struct smu_11_0_7_powerplay_table *powerplay_table =
2010                 table_context->power_play_table;
2011     uint16_t *table_member;
2012     uint16_t temp_edge, temp_hotspot, temp_mem;
2013
2014     if (!range)
2015         return -EINVAL;
2016
2017     memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2018
2019     GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
2020     temp_edge = table_member[TEMP_EDGE];
2021     temp_hotspot = table_member[TEMP_HOTSPOT];
2022     temp_mem = table_member[TEMP_MEM];
2023
2024     range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2025     range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
2026         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2027     range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2028     range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
2029         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2030     range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2031     range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
2032         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2033
2034     range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2035
2036     return 0;
2037 }
2038
2039 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
2040                         bool disable_memory_clock_switch)
2041 {
2042     int ret = 0;
2043     struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2044         (struct smu_11_0_max_sustainable_clocks *)
2045             smu->smu_table.max_sustainable_clocks;
2046     uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2047     uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2048
2049     if(smu->disable_uclk_switch == disable_memory_clock_switch)
2050         return 0;
2051
2052     if(disable_memory_clock_switch)
2053         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2054     else
2055         ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2056
2057     if(!ret)
2058         smu->disable_uclk_switch = disable_memory_clock_switch;
2059
2060     return ret;
2061 }
2062
2063 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
2064                      uint32_t pcie_gen_cap,
2065                      uint32_t pcie_width_cap)
2066 {
2067     struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2068
2069     uint32_t smu_pcie_arg;
2070     uint8_t *table_member1, *table_member2;
2071     int ret, i;
2072
2073     GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
2074     GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
2075
2076     /* lclk dpm table setup */
2077     for (i = 0; i < MAX_PCIE_CONF; i++) {
2078         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
2079         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
2080     }
2081
2082     for (i = 0; i < NUM_LINK_LEVELS; i++) {
2083         smu_pcie_arg = (i << 16) |
2084             ((table_member1[i] <= pcie_gen_cap) ?
2085              (table_member1[i] << 8) :
2086              (pcie_gen_cap << 8)) |
2087             ((table_member2[i] <= pcie_width_cap) ?
2088              table_member2[i] :
2089              pcie_width_cap);
2090
2091         ret = smu_cmn_send_smc_msg_with_param(smu,
2092                 SMU_MSG_OverridePcieParameters,
2093                 smu_pcie_arg,
2094                 NULL);
2095         if (ret)
2096             return ret;
2097
2098         if (table_member1[i] > pcie_gen_cap)
2099             dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2100         if (table_member2[i] > pcie_width_cap)
2101             dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2102     }
2103
2104     return 0;
2105 }
2106
2107 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
2108                 enum smu_clk_type clk_type,
2109                 uint32_t *min, uint32_t *max)
2110 {
2111     return smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
2112 }
2113
2114 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
2115                      OverDriveTable_t *od_table)
2116 {
2117     struct amdgpu_device *adev = smu->adev;
2118     uint32_t smu_version;
2119
2120     dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
2121                               od_table->GfxclkFmax);
2122     dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
2123                             od_table->UclkFmax);
2124
2125     smu_cmn_get_smc_version(smu, NULL, &smu_version);
2126     if (!((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2127            (smu_version < 0x003a2900)))
2128         dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
2129 }
2130
2131 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
2132 {
2133     OverDriveTable_t *od_table =
2134         (OverDriveTable_t *)smu->smu_table.overdrive_table;
2135     OverDriveTable_t *boot_od_table =
2136         (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2137     OverDriveTable_t *user_od_table =
2138         (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2139     int ret = 0;
2140
2141     /*
2142      * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2143      *   - either they already have the default OD settings got during cold bootup
2144      *   - or they have some user customized OD settings which cannot be overwritten
2145      */
2146     if (smu->adev->in_suspend)
2147         return 0;
2148
2149     ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
2150                    0, (void *)boot_od_table, false);
2151     if (ret) {
2152         dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2153         return ret;
2154     }
2155
2156     sienna_cichlid_dump_od_table(smu, boot_od_table);
2157
2158     memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2159     memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2160
2161     return 0;
2162 }
2163
2164 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
2165                          struct smu_11_0_7_overdrive_table *od_table,
2166                          enum SMU_11_0_7_ODSETTING_ID setting,
2167                          uint32_t value)
2168 {
2169     if (value < od_table->min[setting]) {
2170         dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
2171                       setting, value, od_table->min[setting]);
2172         return -EINVAL;
2173     }
2174     if (value > od_table->max[setting]) {
2175         dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
2176                       setting, value, od_table->max[setting]);
2177         return -EINVAL;
2178     }
2179
2180     return 0;
2181 }
2182
2183 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2184                         enum PP_OD_DPM_TABLE_COMMAND type,
2185                         long input[], uint32_t size)
2186 {
2187     struct smu_table_context *table_context = &smu->smu_table;
2188     OverDriveTable_t *od_table =
2189         (OverDriveTable_t *)table_context->overdrive_table;
2190     struct smu_11_0_7_overdrive_table *od_settings =
2191         (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2192     struct amdgpu_device *adev = smu->adev;
2193     enum SMU_11_0_7_ODSETTING_ID freq_setting;
2194     uint16_t *freq_ptr;
2195     int i, ret = 0;
2196     uint32_t smu_version;
2197
2198     if (!smu->od_enabled) {
2199         dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2200         return -EINVAL;
2201     }
2202
2203     if (!smu->od_settings) {
2204         dev_err(smu->adev->dev, "OD board limits are not set!\n");
2205         return -ENOENT;
2206     }
2207
2208     if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2209         dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2210         return -EINVAL;
2211     }
2212
2213     switch (type) {
2214     case PP_OD_EDIT_SCLK_VDDC_TABLE:
2215         if (!sienna_cichlid_is_od_feature_supported(od_settings,
2216                                 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2217             dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2218             return -ENOTSUPP;
2219         }
2220
2221         for (i = 0; i < size; i += 2) {
2222             if (i + 2 > size) {
2223                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2224                 return -EINVAL;
2225             }
2226
2227             switch (input[i]) {
2228             case 0:
2229                 if (input[i + 1] > od_table->GfxclkFmax) {
2230                     dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2231                         input[i + 1], od_table->GfxclkFmax);
2232                     return -EINVAL;
2233                 }
2234
2235                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2236                 freq_ptr = &od_table->GfxclkFmin;
2237                 break;
2238
2239             case 1:
2240                 if (input[i + 1] < od_table->GfxclkFmin) {
2241                     dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2242                         input[i + 1], od_table->GfxclkFmin);
2243                     return -EINVAL;
2244                 }
2245
2246                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2247                 freq_ptr = &od_table->GfxclkFmax;
2248                 break;
2249
2250             default:
2251                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2252                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2253                 return -EINVAL;
2254             }
2255
2256             ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2257                                     freq_setting, input[i + 1]);
2258             if (ret)
2259                 return ret;
2260
2261             *freq_ptr = (uint16_t)input[i + 1];
2262         }
2263         break;
2264
2265     case PP_OD_EDIT_MCLK_VDDC_TABLE:
2266         if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2267             dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2268             return -ENOTSUPP;
2269         }
2270
2271         for (i = 0; i < size; i += 2) {
2272             if (i + 2 > size) {
2273                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2274                 return -EINVAL;
2275             }
2276
2277             switch (input[i]) {
2278             case 0:
2279                 if (input[i + 1] > od_table->UclkFmax) {
2280                     dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2281                         input[i + 1], od_table->UclkFmax);
2282                     return -EINVAL;
2283                 }
2284
2285                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2286                 freq_ptr = &od_table->UclkFmin;
2287                 break;
2288
2289             case 1:
2290                 if (input[i + 1] < od_table->UclkFmin) {
2291                     dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2292                         input[i + 1], od_table->UclkFmin);
2293                     return -EINVAL;
2294                 }
2295
2296                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2297                 freq_ptr = &od_table->UclkFmax;
2298                 break;
2299
2300             default:
2301                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2302                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2303                 return -EINVAL;
2304             }
2305
2306             ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2307                                     freq_setting, input[i + 1]);
2308             if (ret)
2309                 return ret;
2310
2311             *freq_ptr = (uint16_t)input[i + 1];
2312         }
2313         break;
2314
2315     case PP_OD_RESTORE_DEFAULT_TABLE:
2316         memcpy(table_context->overdrive_table,
2317                 table_context->boot_overdrive_table,
2318                 sizeof(OverDriveTable_t));
2319         fallthrough;
2320
2321     case PP_OD_COMMIT_DPM_TABLE:
2322         if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2323             sienna_cichlid_dump_od_table(smu, od_table);
2324             ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2325             if (ret) {
2326                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2327                 return ret;
2328             }
2329             memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2330             smu->user_dpm_profile.user_od = true;
2331
2332             if (!memcmp(table_context->user_overdrive_table,
2333                     table_context->boot_overdrive_table,
2334                     sizeof(OverDriveTable_t)))
2335                 smu->user_dpm_profile.user_od = false;
2336         }
2337         break;
2338
2339     case PP_OD_EDIT_VDDGFX_OFFSET:
2340         if (size != 1) {
2341             dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2342             return -EINVAL;
2343         }
2344
2345         /*
2346          * OD GFX Voltage Offset functionality is supported only by 58.41.0
2347          * and onwards SMU firmwares.
2348          */
2349         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2350         if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
2351              (smu_version < 0x003a2900)) {
2352             dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2353                         "only by 58.41.0 and onwards SMU firmwares!\n");
2354             return -EOPNOTSUPP;
2355         }
2356
2357         od_table->VddGfxOffset = (int16_t)input[0];
2358
2359         sienna_cichlid_dump_od_table(smu, od_table);
2360         break;
2361
2362     default:
2363         return -ENOSYS;
2364     }
2365
2366     return ret;
2367 }
2368
2369 static int sienna_cichlid_run_btc(struct smu_context *smu)
2370 {
2371     int res;
2372
2373     res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2374     if (res)
2375         dev_err(smu->adev->dev, "RunDcBtc failed!\n");
2376
2377     return res;
2378 }
2379
2380 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2381 {
2382     struct amdgpu_device *adev = smu->adev;
2383
2384     if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2385         return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2386     else
2387         return smu_v11_0_baco_enter(smu);
2388 }
2389
2390 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2391 {
2392     struct amdgpu_device *adev = smu->adev;
2393
2394     if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2395         /* Wait for PMFW handling for the Dstate change */
2396         msleep(10);
2397         return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2398     } else {
2399         return smu_v11_0_baco_exit(smu);
2400     }
2401 }
2402
2403 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2404 {
2405     struct amdgpu_device *adev = smu->adev;
2406     uint32_t val;
2407     u32 smu_version;
2408
2409     /**
2410      * SRIOV env will not support SMU mode1 reset
2411      * PM FW support mode1 reset from 58.26
2412      */
2413     smu_cmn_get_smc_version(smu, NULL, &smu_version);
2414     if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2415         return false;
2416
2417     /**
2418      * mode1 reset relies on PSP, so we should check if
2419      * PSP is alive.
2420      */
2421     val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2422     return val != 0x0;
2423 }
2424
2425 static void beige_goby_dump_pptable(struct smu_context *smu)
2426 {
2427     struct smu_table_context *table_context = &smu->smu_table;
2428     PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2429     int i;
2430
2431     dev_info(smu->adev->dev, "Dumped PPTable:\n");
2432
2433     dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2434     dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2435     dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2436
2437     for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2438         dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2439         dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2440         dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2441         dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2442     }
2443
2444     for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2445         dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2446         dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2447     }
2448
2449     for (i = 0; i < TEMP_COUNT; i++) {
2450         dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2451     }
2452
2453     dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2454     dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2455     dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2456     dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2457     dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2458
2459     dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2460     for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2461         dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2462         dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2463     }
2464     dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2465
2466     dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2467
2468     dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2469     dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2470     dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2471     dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2472
2473     dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2474
2475     dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2476
2477     dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2478     dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2479     dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2480     dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2481
2482     dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2483     dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2484
2485     dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2486     dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2487     dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2488     dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2489     dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2490     dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2491     dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2492     dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2493
2494     dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2495             "  .VoltageMode          = 0x%02x\n"
2496             "  .SnapToDiscrete       = 0x%02x\n"
2497             "  .NumDiscreteLevels    = 0x%02x\n"
2498             "  .padding              = 0x%02x\n"
2499             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2500             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2501             "  .SsFmin               = 0x%04x\n"
2502             "  .Padding_16           = 0x%04x\n",
2503             pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2504             pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2505             pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2506             pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2507             pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2508             pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2509             pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2510             pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2511             pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2512             pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2513             pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2514
2515     dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2516             "  .VoltageMode          = 0x%02x\n"
2517             "  .SnapToDiscrete       = 0x%02x\n"
2518             "  .NumDiscreteLevels    = 0x%02x\n"
2519             "  .padding              = 0x%02x\n"
2520             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2521             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2522             "  .SsFmin               = 0x%04x\n"
2523             "  .Padding_16           = 0x%04x\n",
2524             pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2525             pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2526             pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2527             pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2528             pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2529             pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2530             pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2531             pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2532             pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2533             pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2534             pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2535
2536     dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2537             "  .VoltageMode          = 0x%02x\n"
2538             "  .SnapToDiscrete       = 0x%02x\n"
2539             "  .NumDiscreteLevels    = 0x%02x\n"
2540             "  .padding              = 0x%02x\n"
2541             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2542             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2543             "  .SsFmin               = 0x%04x\n"
2544             "  .Padding_16           = 0x%04x\n",
2545             pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2546             pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2547             pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2548             pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2549             pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2550             pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2551             pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2552             pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2553             pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2554             pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2555             pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2556
2557     dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2558             "  .VoltageMode          = 0x%02x\n"
2559             "  .SnapToDiscrete       = 0x%02x\n"
2560             "  .NumDiscreteLevels    = 0x%02x\n"
2561             "  .padding              = 0x%02x\n"
2562             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2563             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2564             "  .SsFmin               = 0x%04x\n"
2565             "  .Padding_16           = 0x%04x\n",
2566             pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2567             pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2568             pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2569             pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2570             pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2571             pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2572             pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2573             pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2574             pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2575             pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2576             pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2577
2578     dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2579             "  .VoltageMode          = 0x%02x\n"
2580             "  .SnapToDiscrete       = 0x%02x\n"
2581             "  .NumDiscreteLevels    = 0x%02x\n"
2582             "  .padding              = 0x%02x\n"
2583             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2584             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2585             "  .SsFmin               = 0x%04x\n"
2586             "  .Padding_16           = 0x%04x\n",
2587             pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2588             pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2589             pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2590             pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2591             pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2592             pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2593             pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2594             pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2595             pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2596             pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2597             pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2598
2599     dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2600             "  .VoltageMode          = 0x%02x\n"
2601             "  .SnapToDiscrete       = 0x%02x\n"
2602             "  .NumDiscreteLevels    = 0x%02x\n"
2603             "  .padding              = 0x%02x\n"
2604             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2605             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2606             "  .SsFmin               = 0x%04x\n"
2607             "  .Padding_16           = 0x%04x\n",
2608             pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2609             pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2610             pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2611             pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2612             pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2613             pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2614             pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2615             pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2616             pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2617             pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2618             pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2619
2620     dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2621             "  .VoltageMode          = 0x%02x\n"
2622             "  .SnapToDiscrete       = 0x%02x\n"
2623             "  .NumDiscreteLevels    = 0x%02x\n"
2624             "  .padding              = 0x%02x\n"
2625             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2626             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2627             "  .SsFmin               = 0x%04x\n"
2628             "  .Padding_16           = 0x%04x\n",
2629             pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2630             pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2631             pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2632             pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2633             pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2634             pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2635             pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2636             pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2637             pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2638             pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2639             pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2640
2641     dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2642             "  .VoltageMode          = 0x%02x\n"
2643             "  .SnapToDiscrete       = 0x%02x\n"
2644             "  .NumDiscreteLevels    = 0x%02x\n"
2645             "  .padding              = 0x%02x\n"
2646             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2647             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2648             "  .SsFmin               = 0x%04x\n"
2649             "  .Padding_16           = 0x%04x\n",
2650             pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2651             pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2652             pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2653             pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2654             pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2655             pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2656             pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2657             pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2658             pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2659             pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2660             pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2661
2662     dev_info(smu->adev->dev, "FreqTableGfx\n");
2663     for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2664         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2665
2666     dev_info(smu->adev->dev, "FreqTableVclk\n");
2667     for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2668         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2669
2670     dev_info(smu->adev->dev, "FreqTableDclk\n");
2671     for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2672         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2673
2674     dev_info(smu->adev->dev, "FreqTableSocclk\n");
2675     for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2676         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2677
2678     dev_info(smu->adev->dev, "FreqTableUclk\n");
2679     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2680         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2681
2682     dev_info(smu->adev->dev, "FreqTableFclk\n");
2683     for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2684         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2685
2686     dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2687     dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2688     dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2689     dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2690     dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2691     dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2692     dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2693     dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2694     dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2695
2696     dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2697     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2698         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2699
2700     dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2701     dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2702
2703     dev_info(smu->adev->dev, "Mp0clkFreq\n");
2704     for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2705         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2706
2707     dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2708     for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2709         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2710
2711     dev_info(smu->adev->dev, "MemVddciVoltage\n");
2712     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2713         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2714
2715     dev_info(smu->adev->dev, "MemMvddVoltage\n");
2716     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2717         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2718
2719     dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2720     dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2721     dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2722     dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2723     dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2724
2725     dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2726
2727     dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2728     dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2729     dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2730     dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2731     dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2732     dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2733     dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2734     dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2735     dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2736     dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2737     dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2738
2739     dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2740     dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2741     dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2742     dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2743     dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2744     dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2745
2746     dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2747     dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2748     dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2749     dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2750     dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2751
2752     dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2753     for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2754         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2755
2756     dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2757     dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2758     dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2759     dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2760
2761     dev_info(smu->adev->dev, "UclkDpmPstates\n");
2762     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2763         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2764
2765     dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2766     dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2767         pptable->UclkDpmSrcFreqRange.Fmin);
2768     dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2769         pptable->UclkDpmSrcFreqRange.Fmax);
2770     dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2771     dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2772         pptable->UclkDpmTargFreqRange.Fmin);
2773     dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2774         pptable->UclkDpmTargFreqRange.Fmax);
2775     dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2776     dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2777
2778     dev_info(smu->adev->dev, "PcieGenSpeed\n");
2779     for (i = 0; i < NUM_LINK_LEVELS; i++)
2780         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2781
2782     dev_info(smu->adev->dev, "PcieLaneCount\n");
2783     for (i = 0; i < NUM_LINK_LEVELS; i++)
2784         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2785
2786     dev_info(smu->adev->dev, "LclkFreq\n");
2787     for (i = 0; i < NUM_LINK_LEVELS; i++)
2788         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2789
2790     dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2791     dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2792
2793     dev_info(smu->adev->dev, "FanGain\n");
2794     for (i = 0; i < TEMP_COUNT; i++)
2795         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2796
2797     dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2798     dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2799     dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2800     dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2801     dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2802     dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2803     dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2804     dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2805     dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2806     dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2807     dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2808     dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2809
2810     dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2811     dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2812     dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2813     dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2814
2815     dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2816     dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2817     dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2818     dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2819
2820     dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2821             pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2822             pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2823             pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2824     dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2825             pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2826             pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2827             pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2828     dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2829             pptable->dBtcGbGfxPll.a,
2830             pptable->dBtcGbGfxPll.b,
2831             pptable->dBtcGbGfxPll.c);
2832     dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2833             pptable->dBtcGbGfxDfll.a,
2834             pptable->dBtcGbGfxDfll.b,
2835             pptable->dBtcGbGfxDfll.c);
2836     dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2837             pptable->dBtcGbSoc.a,
2838             pptable->dBtcGbSoc.b,
2839             pptable->dBtcGbSoc.c);
2840     dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2841             pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2842             pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2843     dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2844             pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2845             pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2846
2847     dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2848     for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2849         dev_info(smu->adev->dev, "      Fset[%d] = 0x%x\n",
2850             i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2851         dev_info(smu->adev->dev, "      Vdroop[%d] = 0x%x\n",
2852             i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2853     }
2854
2855     dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2856             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2857             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2858             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2859     dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2860             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2861             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2862             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2863
2864     dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2865     dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2866
2867     dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2868     dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2869     dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2870     dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2871
2872     dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2873     dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2874     dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2875     dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2876
2877     dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2878     dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2879
2880     dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2881     for (i = 0; i < NUM_XGMI_LEVELS; i++)
2882         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2883     dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2884     dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2885
2886     dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2887     dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2888             pptable->ReservedEquation0.a,
2889             pptable->ReservedEquation0.b,
2890             pptable->ReservedEquation0.c);
2891     dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2892             pptable->ReservedEquation1.a,
2893             pptable->ReservedEquation1.b,
2894             pptable->ReservedEquation1.c);
2895     dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2896             pptable->ReservedEquation2.a,
2897             pptable->ReservedEquation2.b,
2898             pptable->ReservedEquation2.c);
2899     dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2900             pptable->ReservedEquation3.a,
2901             pptable->ReservedEquation3.b,
2902             pptable->ReservedEquation3.c);
2903
2904     dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2905     dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2906     dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2907     dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2908     dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2909     dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2910     dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2911     dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2912
2913     dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2914     dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2915     dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2916     dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2917     dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2918     dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2919
2920     for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2921         dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2922         dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2923                 pptable->I2cControllers[i].Enabled);
2924         dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2925                 pptable->I2cControllers[i].Speed);
2926         dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2927                 pptable->I2cControllers[i].SlaveAddress);
2928         dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2929                 pptable->I2cControllers[i].ControllerPort);
2930         dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2931                 pptable->I2cControllers[i].ControllerName);
2932         dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2933                 pptable->I2cControllers[i].ThermalThrotter);
2934         dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2935                 pptable->I2cControllers[i].I2cProtocol);
2936         dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2937                 pptable->I2cControllers[i].PaddingConfig);
2938     }
2939
2940     dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2941     dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2942     dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2943     dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2944
2945     dev_info(smu->adev->dev, "Board Parameters:\n");
2946     dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2947     dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2948     dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2949     dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2950     dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2951     dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2952     dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2953     dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2954
2955     dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2956     dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2957     dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2958
2959     dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2960     dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2961     dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2962
2963     dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2964     dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2965     dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2966
2967     dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2968     dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2969     dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2970
2971     dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2972
2973     dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2974     dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2975     dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2976     dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2977     dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2978     dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2979     dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2980     dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2981     dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2982     dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2983     dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2984     dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2985     dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2986     dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2987     dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2988     dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2989
2990     dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2991     dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2992     dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2993
2994     dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2995     dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2996     dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2997
2998     dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2999     dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3000
3001     dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3002     dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3003     dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3004
3005     dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3006     dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3007     dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3008     dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3009     dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3010
3011     dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3012     dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3013
3014     dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3015     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3016         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3017     dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3018     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3019         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3020     dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3021     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3022         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3023     dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3024     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3025         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3026
3027     dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3028     dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3029     dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3030     dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3031
3032     dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3033     dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3034     dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3035     dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3036     dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3037     dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3038     dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3039     dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3040     dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3041     dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3042     dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3043
3044     dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3045     dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3046     dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3047     dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3048     dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3049     dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3050     dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3051     dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3052 }
3053
3054 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
3055 {
3056     struct smu_table_context *table_context = &smu->smu_table;
3057     PPTable_t *pptable = table_context->driver_pptable;
3058     int i;
3059
3060     if (smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) {
3061         beige_goby_dump_pptable(smu);
3062         return;
3063     }
3064
3065     dev_info(smu->adev->dev, "Dumped PPTable:\n");
3066
3067     dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
3068     dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
3069     dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
3070
3071     for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
3072         dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
3073         dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
3074         dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
3075         dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
3076     }
3077
3078     for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
3079         dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
3080         dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
3081     }
3082
3083     for (i = 0; i < TEMP_COUNT; i++) {
3084         dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
3085     }
3086
3087     dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
3088     dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
3089     dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
3090     dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
3091     dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
3092
3093     dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
3094     for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
3095         dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
3096         dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
3097     }
3098     dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
3099
3100     dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
3101
3102     dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
3103     dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
3104     dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
3105     dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
3106
3107     dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
3108     dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
3109
3110     dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
3111     dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
3112     dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
3113     dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
3114
3115     dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
3116     dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
3117     dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
3118     dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
3119
3120     dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
3121     dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
3122
3123     dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
3124     dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
3125     dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
3126     dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
3127     dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
3128     dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
3129     dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
3130     dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
3131
3132     dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
3133             "  .VoltageMode          = 0x%02x\n"
3134             "  .SnapToDiscrete       = 0x%02x\n"
3135             "  .NumDiscreteLevels    = 0x%02x\n"
3136             "  .padding              = 0x%02x\n"
3137             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3138             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3139             "  .SsFmin               = 0x%04x\n"
3140             "  .Padding_16           = 0x%04x\n",
3141             pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
3142             pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
3143             pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
3144             pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
3145             pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
3146             pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
3147             pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
3148             pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
3149             pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
3150             pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
3151             pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
3152
3153     dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
3154             "  .VoltageMode          = 0x%02x\n"
3155             "  .SnapToDiscrete       = 0x%02x\n"
3156             "  .NumDiscreteLevels    = 0x%02x\n"
3157             "  .padding              = 0x%02x\n"
3158             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3159             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3160             "  .SsFmin               = 0x%04x\n"
3161             "  .Padding_16           = 0x%04x\n",
3162             pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
3163             pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
3164             pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
3165             pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
3166             pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
3167             pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
3168             pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
3169             pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
3170             pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
3171             pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
3172             pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
3173
3174     dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
3175             "  .VoltageMode          = 0x%02x\n"
3176             "  .SnapToDiscrete       = 0x%02x\n"
3177             "  .NumDiscreteLevels    = 0x%02x\n"
3178             "  .padding              = 0x%02x\n"
3179             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3180             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3181             "  .SsFmin               = 0x%04x\n"
3182             "  .Padding_16           = 0x%04x\n",
3183             pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
3184             pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
3185             pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3186             pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3187             pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3188             pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3189             pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3190             pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3191             pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3192             pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3193             pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3194
3195     dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3196             "  .VoltageMode          = 0x%02x\n"
3197             "  .SnapToDiscrete       = 0x%02x\n"
3198             "  .NumDiscreteLevels    = 0x%02x\n"
3199             "  .padding              = 0x%02x\n"
3200             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3201             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3202             "  .SsFmin               = 0x%04x\n"
3203             "  .Padding_16           = 0x%04x\n",
3204             pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3205             pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3206             pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3207             pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3208             pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3209             pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3210             pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3211             pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3212             pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3213             pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3214             pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3215
3216     dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3217             "  .VoltageMode          = 0x%02x\n"
3218             "  .SnapToDiscrete       = 0x%02x\n"
3219             "  .NumDiscreteLevels    = 0x%02x\n"
3220             "  .padding              = 0x%02x\n"
3221             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3222             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3223             "  .SsFmin               = 0x%04x\n"
3224             "  .Padding_16           = 0x%04x\n",
3225             pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3226             pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3227             pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3228             pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3229             pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3230             pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3231             pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3232             pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3233             pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3234             pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3235             pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3236
3237     dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3238             "  .VoltageMode          = 0x%02x\n"
3239             "  .SnapToDiscrete       = 0x%02x\n"
3240             "  .NumDiscreteLevels    = 0x%02x\n"
3241             "  .padding              = 0x%02x\n"
3242             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3243             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3244             "  .SsFmin               = 0x%04x\n"
3245             "  .Padding_16           = 0x%04x\n",
3246             pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3247             pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3248             pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3249             pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3250             pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3251             pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3252             pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3253             pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3254             pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3255             pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3256             pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3257
3258     dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3259             "  .VoltageMode          = 0x%02x\n"
3260             "  .SnapToDiscrete       = 0x%02x\n"
3261             "  .NumDiscreteLevels    = 0x%02x\n"
3262             "  .padding              = 0x%02x\n"
3263             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3264             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3265             "  .SsFmin               = 0x%04x\n"
3266             "  .Padding_16           = 0x%04x\n",
3267             pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3268             pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3269             pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3270             pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3271             pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3272             pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3273             pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3274             pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3275             pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3276             pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3277             pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3278
3279     dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3280             "  .VoltageMode          = 0x%02x\n"
3281             "  .SnapToDiscrete       = 0x%02x\n"
3282             "  .NumDiscreteLevels    = 0x%02x\n"
3283             "  .padding              = 0x%02x\n"
3284             "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3285             "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3286             "  .SsFmin               = 0x%04x\n"
3287             "  .Padding_16           = 0x%04x\n",
3288             pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3289             pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3290             pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3291             pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3292             pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3293             pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3294             pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3295             pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3296             pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3297             pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3298             pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3299
3300     dev_info(smu->adev->dev, "FreqTableGfx\n");
3301     for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3302         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3303
3304     dev_info(smu->adev->dev, "FreqTableVclk\n");
3305     for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3306         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3307
3308     dev_info(smu->adev->dev, "FreqTableDclk\n");
3309     for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3310         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3311
3312     dev_info(smu->adev->dev, "FreqTableSocclk\n");
3313     for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3314         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3315
3316     dev_info(smu->adev->dev, "FreqTableUclk\n");
3317     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3318         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3319
3320     dev_info(smu->adev->dev, "FreqTableFclk\n");
3321     for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3322         dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3323
3324     dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3325     dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3326     dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3327     dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3328     dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3329     dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3330     dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3331     dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3332     dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3333
3334     dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3335     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3336         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3337
3338     dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3339     dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3340
3341     dev_info(smu->adev->dev, "Mp0clkFreq\n");
3342     for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3343         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3344
3345     dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3346     for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3347         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3348
3349     dev_info(smu->adev->dev, "MemVddciVoltage\n");
3350     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3351         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3352
3353     dev_info(smu->adev->dev, "MemMvddVoltage\n");
3354     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3355         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3356
3357     dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3358     dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3359     dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3360     dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3361     dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3362
3363     dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3364
3365     dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3366     dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3367     dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3368     dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3369     dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3370     dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3371     dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3372     dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3373     dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3374     dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3375     dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3376
3377     dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3378     dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3379     dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3380     dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3381     dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3382     dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3383
3384     dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3385     dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3386     dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3387     dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3388     dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3389
3390     dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3391     for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3392         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3393
3394     dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3395     dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3396     dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3397     dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3398
3399     dev_info(smu->adev->dev, "UclkDpmPstates\n");
3400     for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3401         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3402
3403     dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3404     dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3405         pptable->UclkDpmSrcFreqRange.Fmin);
3406     dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3407         pptable->UclkDpmSrcFreqRange.Fmax);
3408     dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3409     dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3410         pptable->UclkDpmTargFreqRange.Fmin);
3411     dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3412         pptable->UclkDpmTargFreqRange.Fmax);
3413     dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3414     dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3415
3416     dev_info(smu->adev->dev, "PcieGenSpeed\n");
3417     for (i = 0; i < NUM_LINK_LEVELS; i++)
3418         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3419
3420     dev_info(smu->adev->dev, "PcieLaneCount\n");
3421     for (i = 0; i < NUM_LINK_LEVELS; i++)
3422         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3423
3424     dev_info(smu->adev->dev, "LclkFreq\n");
3425     for (i = 0; i < NUM_LINK_LEVELS; i++)
3426         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3427
3428     dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3429     dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3430
3431     dev_info(smu->adev->dev, "FanGain\n");
3432     for (i = 0; i < TEMP_COUNT; i++)
3433         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3434
3435     dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3436     dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3437     dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3438     dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3439     dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3440     dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3441     dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3442     dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3443     dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3444     dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3445     dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3446     dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3447
3448     dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3449     dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3450     dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3451     dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3452
3453     dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3454     dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3455     dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3456     dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3457
3458     dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3459             pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3460             pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3461             pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3462     dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3463             pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3464             pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3465             pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3466     dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3467             pptable->dBtcGbGfxPll.a,
3468             pptable->dBtcGbGfxPll.b,
3469             pptable->dBtcGbGfxPll.c);
3470     dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3471             pptable->dBtcGbGfxDfll.a,
3472             pptable->dBtcGbGfxDfll.b,
3473             pptable->dBtcGbGfxDfll.c);
3474     dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3475             pptable->dBtcGbSoc.a,
3476             pptable->dBtcGbSoc.b,
3477             pptable->dBtcGbSoc.c);
3478     dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3479             pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3480             pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3481     dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3482             pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3483             pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3484
3485     dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3486     for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3487         dev_info(smu->adev->dev, "      Fset[%d] = 0x%x\n",
3488             i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3489         dev_info(smu->adev->dev, "      Vdroop[%d] = 0x%x\n",
3490             i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3491     }
3492
3493     dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3494             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3495             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3496             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3497     dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3498             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3499             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3500             pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3501
3502     dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3503     dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3504
3505     dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3506     dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3507     dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3508     dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3509
3510     dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3511     dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3512     dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3513     dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3514
3515     dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3516     dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3517
3518     dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3519     for (i = 0; i < NUM_XGMI_LEVELS; i++)
3520         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3521     dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3522     dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3523
3524     dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3525     dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3526             pptable->ReservedEquation0.a,
3527             pptable->ReservedEquation0.b,
3528             pptable->ReservedEquation0.c);
3529     dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3530             pptable->ReservedEquation1.a,
3531             pptable->ReservedEquation1.b,
3532             pptable->ReservedEquation1.c);
3533     dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3534             pptable->ReservedEquation2.a,
3535             pptable->ReservedEquation2.b,
3536             pptable->ReservedEquation2.c);
3537     dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3538             pptable->ReservedEquation3.a,
3539             pptable->ReservedEquation3.b,
3540             pptable->ReservedEquation3.c);
3541
3542     dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3543     dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3544     dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3545     dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3546     dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3547     dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3548     dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3549     dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3550
3551     dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3552     dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3553     dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3554     dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3555     dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3556     dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3557
3558     for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3559         dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3560         dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3561                 pptable->I2cControllers[i].Enabled);
3562         dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3563                 pptable->I2cControllers[i].Speed);
3564         dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3565                 pptable->I2cControllers[i].SlaveAddress);
3566         dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3567                 pptable->I2cControllers[i].ControllerPort);
3568         dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3569                 pptable->I2cControllers[i].ControllerName);
3570         dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3571                 pptable->I2cControllers[i].ThermalThrotter);
3572         dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3573                 pptable->I2cControllers[i].I2cProtocol);
3574         dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3575                 pptable->I2cControllers[i].PaddingConfig);
3576     }
3577
3578     dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3579     dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3580     dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3581     dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3582
3583     dev_info(smu->adev->dev, "Board Parameters:\n");
3584     dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3585     dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3586     dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3587     dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3588     dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3589     dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3590     dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3591     dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3592
3593     dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3594     dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3595     dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3596
3597     dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3598     dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3599     dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3600
3601     dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3602     dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3603     dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3604
3605     dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3606     dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3607     dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3608
3609     dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3610
3611     dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3612     dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3613     dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3614     dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3615     dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3616     dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3617     dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3618     dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3619     dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3620     dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3621     dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3622     dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3623     dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3624     dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3625     dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3626     dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3627
3628     dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3629     dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3630     dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3631
3632     dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3633     dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3634     dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3635
3636     dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3637     dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3638
3639     dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3640     dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3641     dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3642
3643     dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3644     dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3645     dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3646     dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3647     dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3648
3649     dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3650     dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3651
3652     dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3653     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3654         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3655     dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3656     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3657         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3658     dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3659     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3660         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3661     dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3662     for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3663         dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3664
3665     dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3666     dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3667     dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3668     dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3669
3670     dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3671     dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3672     dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3673     dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3674     dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3675     dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3676     dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3677     dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3678     dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3679     dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3680     dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3681
3682     dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3683     dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3684     dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3685     dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3686     dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3687     dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3688     dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3689     dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3690 }
3691
3692 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3693                    struct i2c_msg *msg, int num_msgs)
3694 {
3695     struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
3696     struct amdgpu_device *adev = smu_i2c->adev;
3697     struct smu_context *smu = adev->powerplay.pp_handle;
3698     struct smu_table_context *smu_table = &smu->smu_table;
3699     struct smu_table *table = &smu_table->driver_table;
3700     SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3701     int i, j, r, c;
3702     u16 dir;
3703
3704     if (!adev->pm.dpm_enabled)
3705         return -EBUSY;
3706
3707     req = kzalloc(sizeof(*req), GFP_KERNEL);
3708     if (!req)
3709         return -ENOMEM;
3710
3711     req->I2CcontrollerPort = smu_i2c->port;
3712     req->I2CSpeed = I2C_SPEED_FAST_400K;
3713     req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3714     dir = msg[0].flags & I2C_M_RD;
3715
3716     for (c = i = 0; i < num_msgs; i++) {
3717         for (j = 0; j < msg[i].len; j++, c++) {
3718             SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3719
3720             if (!(msg[i].flags & I2C_M_RD)) {
3721                 /* write */
3722                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3723                 cmd->ReadWriteData = msg[i].buf[j];
3724             }
3725
3726             if ((dir ^ msg[i].flags) & I2C_M_RD) {
3727                 /* The direction changes.
3728                  */
3729                 dir = msg[i].flags & I2C_M_RD;
3730                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3731             }
3732
3733             req->NumCmds++;
3734
3735             /*
3736              * Insert STOP if we are at the last byte of either last
3737              * message for the transaction or the client explicitly
3738              * requires a STOP at this particular message.
3739              */
3740             if ((j == msg[i].len - 1) &&
3741                 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3742                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3743                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3744             }
3745         }
3746     }
3747     mutex_lock(&adev->pm.mutex);
3748     r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3749     mutex_unlock(&adev->pm.mutex);
3750     if (r)
3751         goto fail;
3752
3753     for (c = i = 0; i < num_msgs; i++) {
3754         if (!(msg[i].flags & I2C_M_RD)) {
3755             c += msg[i].len;
3756             continue;
3757         }
3758         for (j = 0; j < msg[i].len; j++, c++) {
3759             SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3760
3761             msg[i].buf[j] = cmd->ReadWriteData;
3762         }
3763     }
3764     r = num_msgs;
3765 fail:
3766     kfree(req);
3767     return r;
3768 }
3769
3770 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3771 {
3772     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3773 }
3774
3775
3776 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3777     .master_xfer = sienna_cichlid_i2c_xfer,
3778     .functionality = sienna_cichlid_i2c_func,
3779 };
3780
3781 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3782     .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3783     .max_read_len  = MAX_SW_I2C_COMMANDS,
3784     .max_write_len = MAX_SW_I2C_COMMANDS,
3785     .max_comb_1st_msg_len = 2,
3786     .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3787 };
3788
3789 static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
3790 {
3791     struct amdgpu_device *adev = smu->adev;
3792     int res, i;
3793
3794     for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3795         struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3796         struct i2c_adapter *control = &smu_i2c->adapter;
3797
3798         smu_i2c->adev = adev;
3799         smu_i2c->port = i;
3800         mutex_init(&smu_i2c->mutex);
3801         control->owner = THIS_MODULE;
3802         control->class = I2C_CLASS_HWMON;
3803         control->dev.parent = &adev->pdev->dev;
3804         control->algo = &sienna_cichlid_i2c_algo;
3805         snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3806         control->quirks = &sienna_cichlid_i2c_control_quirks;
3807         i2c_set_adapdata(control, smu_i2c);
3808
3809         res = i2c_add_adapter(control);
3810         if (res) {
3811             DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3812             goto Out_err;
3813         }
3814     }
3815     /* assign the buses used for the FRU EEPROM and RAS EEPROM */
3816     /* XXX ideally this would be something in a vbios data table */
3817     adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3818     adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3819
3820     return 0;
3821 Out_err:
3822     for ( ; i >= 0; i--) {
3823         struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3824         struct i2c_adapter *control = &smu_i2c->adapter;
3825
3826         i2c_del_adapter(control);
3827     }
3828     return res;
3829 }
3830
3831 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
3832 {
3833     struct amdgpu_device *adev = smu->adev;
3834     int i;
3835
3836     for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3837         struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3838         struct i2c_adapter *control = &smu_i2c->adapter;
3839
3840         i2c_del_adapter(control);
3841     }
3842     adev->pm.ras_eeprom_i2c_bus = NULL;
3843     adev->pm.fru_eeprom_i2c_bus = NULL;
3844 }
3845
3846 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3847                           void **table)
3848 {
3849     struct smu_table_context *smu_table = &smu->smu_table;
3850     struct gpu_metrics_v1_3 *gpu_metrics =
3851         (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3852     SmuMetricsExternal_t metrics_external;
3853     SmuMetrics_t *metrics =
3854         &(metrics_external.SmuMetrics);
3855     SmuMetrics_V2_t *metrics_v2 =
3856         &(metrics_external.SmuMetrics_V2);
3857     SmuMetrics_V3_t *metrics_v3 =
3858         &(metrics_external.SmuMetrics_V3);
3859     struct amdgpu_device *adev = smu->adev;
3860     bool use_metrics_v2 = false;
3861     bool use_metrics_v3 = false;
3862     uint16_t average_gfx_activity;
3863     int ret = 0;
3864
3865     switch (smu->adev->ip_versions[MP1_HWIP][0]) {
3866     case IP_VERSION(11, 0, 7):
3867         if (smu->smc_fw_version >= 0x3A4900)
3868             use_metrics_v3 = true;
3869         else if (smu->smc_fw_version >= 0x3A4300)
3870             use_metrics_v2 = true;
3871         break;
3872     case IP_VERSION(11, 0, 11):
3873         if (smu->smc_fw_version >= 0x412D00)
3874             use_metrics_v2 = true;
3875         break;
3876     case IP_VERSION(11, 0, 12):
3877         if (smu->smc_fw_version >= 0x3B2300)
3878             use_metrics_v2 = true;
3879         break;
3880     case IP_VERSION(11, 0, 13):
3881         if (smu->smc_fw_version >= 0x491100)
3882             use_metrics_v2 = true;
3883         break;
3884     default:
3885         break;
3886     }
3887
3888     ret = smu_cmn_get_metrics_table(smu,
3889                     &metrics_external,
3890                     true);
3891     if (ret)
3892         return ret;
3893
3894     smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3895
3896     gpu_metrics->temperature_edge = use_metrics_v3 ? metrics_v3->TemperatureEdge :
3897         use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3898     gpu_metrics->temperature_hotspot = use_metrics_v3 ? metrics_v3->TemperatureHotspot :
3899         use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3900     gpu_metrics->temperature_mem = use_metrics_v3 ? metrics_v3->TemperatureMem :
3901         use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3902     gpu_metrics->temperature_vrgfx = use_metrics_v3 ? metrics_v3->TemperatureVrGfx :
3903         use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3904     gpu_metrics->temperature_vrsoc = use_metrics_v3 ? metrics_v3->TemperatureVrSoc :
3905         use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3906     gpu_metrics->temperature_vrmem = use_metrics_v3 ? metrics_v3->TemperatureVrMem0 :
3907         use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3908
3909     gpu_metrics->average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3910         use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3911     gpu_metrics->average_umc_activity = use_metrics_v3 ? metrics_v3->AverageUclkActivity :
3912         use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3913     gpu_metrics->average_mm_activity = use_metrics_v3 ?
3914         (metrics_v3->VcnUsagePercentage0 + metrics_v3->VcnUsagePercentage1) / 2 :
3915         use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3916
3917     gpu_metrics->average_socket_power = use_metrics_v3 ? metrics_v3->AverageSocketPower :
3918         use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3919     gpu_metrics->energy_accumulator = use_metrics_v3 ? metrics_v3->EnergyAccumulator :
3920         use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3921
3922     if (metrics->CurrGfxVoltageOffset)
3923         gpu_metrics->voltage_gfx =
3924             (155000 - 625 * metrics->CurrGfxVoltageOffset) / 100;
3925     if (metrics->CurrMemVidOffset)
3926         gpu_metrics->voltage_mem =
3927             (155000 - 625 * metrics->CurrMemVidOffset) / 100;
3928     if (metrics->CurrSocVoltageOffset)
3929         gpu_metrics->voltage_soc =
3930             (155000 - 625 * metrics->CurrSocVoltageOffset) / 100;
3931
3932     average_gfx_activity = use_metrics_v3 ? metrics_v3->AverageGfxActivity :
3933         use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3934     if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3935         gpu_metrics->average_gfxclk_frequency =
3936             use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPostDs :
3937             use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
3938             metrics->AverageGfxclkFrequencyPostDs;
3939     else
3940         gpu_metrics->average_gfxclk_frequency =
3941             use_metrics_v3 ? metrics_v3->AverageGfxclkFrequencyPreDs :
3942             use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
3943             metrics->AverageGfxclkFrequencyPreDs;
3944
3945     gpu_metrics->average_uclk_frequency =
3946         use_metrics_v3 ? metrics_v3->AverageUclkFrequencyPostDs :
3947         use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
3948         metrics->AverageUclkFrequencyPostDs;
3949     gpu_metrics->average_vclk0_frequency = use_metrics_v3 ? metrics_v3->AverageVclk0Frequency :
3950         use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3951     gpu_metrics->average_dclk0_frequency = use_metrics_v3 ? metrics_v3->AverageDclk0Frequency :
3952         use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3953     gpu_metrics->average_vclk1_frequency = use_metrics_v3 ? metrics_v3->AverageVclk1Frequency :
3954         use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3955     gpu_metrics->average_dclk1_frequency = use_metrics_v3 ? metrics_v3->AverageDclk1Frequency :
3956         use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3957
3958     gpu_metrics->current_gfxclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_GFXCLK] :
3959         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3960     gpu_metrics->current_socclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_SOCCLK] :
3961         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3962     gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] :
3963         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3964     gpu_metrics->current_vclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_0] :
3965         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3966     gpu_metrics->current_dclk0 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_0] :
3967         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3968     gpu_metrics->current_vclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_VCLK_1] :
3969         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3970     gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
3971         use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3972
3973     gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3974     gpu_metrics->indep_throttle_status =
3975             smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3976                                sienna_cichlid_throttler_map);
3977
3978     gpu_metrics->current_fan_speed = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
3979         use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3980
3981     if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) && smu->smc_fw_version > 0x003A1E00) ||
3982           ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11)) && smu->smc_fw_version > 0x00410400)) {
3983         gpu_metrics->pcie_link_width = use_metrics_v3 ? metrics_v3->PcieWidth :
3984             use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3985         gpu_metrics->pcie_link_speed = link_speed[use_metrics_v3 ? metrics_v3->PcieRate :
3986             use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3987     } else {
3988         gpu_metrics->pcie_link_width =
3989                 smu_v11_0_get_current_pcie_link_width(smu);
3990         gpu_metrics->pcie_link_speed =
3991                 smu_v11_0_get_current_pcie_link_speed(smu);
3992     }
3993
3994     gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3995
3996     *table = (void *)gpu_metrics;
3997
3998     return sizeof(struct gpu_metrics_v1_3);
3999 }
4000
4001 static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
4002 {
4003     uint32_t if_version = 0xff, smu_version = 0xff;
4004     int ret = 0;
4005
4006     ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
4007     if (ret)
4008         return -EOPNOTSUPP;
4009
4010     if (smu_version < SUPPORT_ECCTABLE_SMU_VERSION)
4011         ret = -EOPNOTSUPP;
4012
4013     return ret;
4014 }
4015
4016 static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
4017                     void *table)
4018 {
4019     struct smu_table_context *smu_table = &smu->smu_table;
4020     EccInfoTable_t *ecc_table = NULL;
4021     struct ecc_info_per_ch *ecc_info_per_channel = NULL;
4022     int i, ret = 0;
4023     struct umc_ecc_info *eccinfo = (struct umc_ecc_info *)table;
4024
4025     ret = sienna_cichlid_check_ecc_table_support(smu);
4026     if (ret)
4027         return ret;
4028
4029     ret = smu_cmn_update_table(smu,
4030                 SMU_TABLE_ECCINFO,
4031                 0,
4032                 smu_table->ecc_table,
4033                 false);
4034     if (ret) {
4035         dev_info(smu->adev->dev, "Failed to export SMU ecc table!\n");
4036         return ret;
4037     }
4038
4039     ecc_table = (EccInfoTable_t *)smu_table->ecc_table;
4040
4041     for (i = 0; i < SIENNA_CICHLID_UMC_CHANNEL_NUM; i++) {
4042         ecc_info_per_channel = &(eccinfo->ecc[i]);
4043         ecc_info_per_channel->ce_count_lo_chip =
4044             ecc_table->EccInfo[i].ce_count_lo_chip;
4045         ecc_info_per_channel->ce_count_hi_chip =
4046             ecc_table->EccInfo[i].ce_count_hi_chip;
4047         ecc_info_per_channel->mca_umc_status =
4048             ecc_table->EccInfo[i].mca_umc_status;
4049         ecc_info_per_channel->mca_umc_addr =
4050             ecc_table->EccInfo[i].mca_umc_addr;
4051     }
4052
4053     return ret;
4054 }
4055 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
4056 {
4057     uint16_t *mgpu_fan_boost_limit_rpm;
4058
4059     GET_PPTABLE_MEMBER(MGpuFanBoostLimitRpm, &mgpu_fan_boost_limit_rpm);
4060     /*
4061      * Skip the MGpuFanBoost setting for those ASICs
4062      * which do not support it
4063      */
4064     if (*mgpu_fan_boost_limit_rpm == 0)
4065         return 0;
4066
4067     return smu_cmn_send_smc_msg_with_param(smu,
4068                            SMU_MSG_SetMGpuFanBoostLimitRpm,
4069                            0,
4070                            NULL);
4071 }
4072
4073 static int sienna_cichlid_gpo_control(struct smu_context *smu,
4074                       bool enablement)
4075 {
4076     uint32_t smu_version;
4077     int ret = 0;
4078
4079
4080     if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
4081         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4082         if (ret)
4083             return ret;
4084
4085         if (enablement) {
4086             if (smu_version < 0x003a2500) {
4087                 ret = smu_cmn_send_smc_msg_with_param(smu,
4088                                       SMU_MSG_SetGpoFeaturePMask,
4089                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
4090                                       NULL);
4091             } else {
4092                 ret = smu_cmn_send_smc_msg_with_param(smu,
4093                                       SMU_MSG_DisallowGpo,
4094                                       0,
4095                                       NULL);
4096             }
4097         } else {
4098             if (smu_version < 0x003a2500) {
4099                 ret = smu_cmn_send_smc_msg_with_param(smu,
4100                                       SMU_MSG_SetGpoFeaturePMask,
4101                                       0,
4102                                       NULL);
4103             } else {
4104                 ret = smu_cmn_send_smc_msg_with_param(smu,
4105                                       SMU_MSG_DisallowGpo,
4106                                       1,
4107                                       NULL);
4108             }
4109         }
4110     }
4111
4112     return ret;
4113 }
4114
4115 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
4116 {
4117     uint32_t smu_version;
4118     int ret = 0;
4119
4120     ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
4121     if (ret)
4122         return ret;
4123
4124     /*
4125      * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
4126      * onwards PMFWs.
4127      */
4128     if (smu_version < 0x003A2D00)
4129         return 0;
4130
4131     return smu_cmn_send_smc_msg_with_param(smu,
4132                            SMU_MSG_Enable2ndUSB20Port,
4133                            smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
4134                            1 : 0,
4135                            NULL);
4136 }
4137
4138 static int sienna_cichlid_system_features_control(struct smu_context *smu,
4139                           bool en)
4140 {
4141     int ret = 0;
4142
4143     if (en) {
4144         ret = sienna_cichlid_notify_2nd_usb20_port(smu);
4145         if (ret)
4146             return ret;
4147     }
4148
4149     return smu_v11_0_system_features_control(smu, en);
4150 }
4151
4152 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
4153                     enum pp_mp1_state mp1_state)
4154 {
4155     int ret;
4156
4157     switch (mp1_state) {
4158     case PP_MP1_STATE_UNLOAD:
4159         ret = smu_cmn_set_mp1_state(smu, mp1_state);
4160         break;
4161     default:
4162         /* Ignore others */
4163         ret = 0;
4164     }
4165
4166     return ret;
4167 }
4168
4169 static void sienna_cichlid_stb_init(struct smu_context *smu)
4170 {
4171     struct amdgpu_device *adev = smu->adev;
4172     uint32_t reg;
4173
4174     reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START);
4175     smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);
4176
4177     /* STB is disabled */
4178     if (!smu->stb_context.enabled)
4179         return;
4180
4181     spin_lock_init(&smu->stb_context.lock);
4182
4183     /* STB buffer size in bytes as function of FIFO depth */
4184     reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO);
4185     smu->stb_context.stb_buf_size = 1 << REG_GET_FIELD(reg, MP1_PMI_3_FIFO, DEPTH);
4186     smu->stb_context.stb_buf_size *=  SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES;
4187
4188     dev_info(smu->adev->dev, "STB initialized to %d entries",
4189          smu->stb_context.stb_buf_size / SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES);
4190
4191 }
4192
4193 static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
4194                                 struct config_table_setting *table)
4195 {
4196     struct amdgpu_device *adev = smu->adev;
4197
4198     if (!table)
4199         return -EINVAL;
4200
4201     table->gfxclk_average_tau = 10;
4202     table->socclk_average_tau = 10;
4203     table->fclk_average_tau = 10;
4204     table->uclk_average_tau = 10;
4205     table->gfx_activity_average_tau = 10;
4206     table->mem_activity_average_tau = 10;
4207     table->socket_power_average_tau = 100;
4208     if (adev->ip_versions[MP1_HWIP][0] != IP_VERSION(11, 0, 7))
4209         table->apu_socket_power_average_tau = 100;
4210
4211     return 0;
4212 }
4213
4214 static int sienna_cichlid_set_config_table(struct smu_context *smu,
4215                        struct config_table_setting *table)
4216 {
4217     DriverSmuConfigExternal_t driver_smu_config_table;
4218
4219     if (!table)
4220         return -EINVAL;
4221
4222     memset(&driver_smu_config_table,
4223            0,
4224            sizeof(driver_smu_config_table));
4225     driver_smu_config_table.DriverSmuConfig.GfxclkAverageLpfTau =
4226                 table->gfxclk_average_tau;
4227     driver_smu_config_table.DriverSmuConfig.FclkAverageLpfTau =
4228                 table->fclk_average_tau;
4229     driver_smu_config_table.DriverSmuConfig.UclkAverageLpfTau =
4230                 table->uclk_average_tau;
4231     driver_smu_config_table.DriverSmuConfig.GfxActivityLpfTau =
4232                 table->gfx_activity_average_tau;
4233     driver_smu_config_table.DriverSmuConfig.UclkActivityLpfTau =
4234                 table->mem_activity_average_tau;
4235     driver_smu_config_table.DriverSmuConfig.SocketPowerLpfTau =
4236                 table->socket_power_average_tau;
4237
4238     return smu_cmn_update_table(smu,
4239                     SMU_TABLE_DRIVER_SMU_CONFIG,
4240                     0,
4241                     (void *)&driver_smu_config_table,
4242                     true);
4243 }
4244
4245 static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
4246                           void *buf,
4247                           uint32_t size)
4248 {
4249     uint32_t *p = buf;
4250     struct amdgpu_device *adev = smu->adev;
4251
4252     /* No need to disable interrupts for now as we don't lock it yet from ISR */
4253     spin_lock(&smu->stb_context.lock);
4254
4255     /*
4256      * Read the STB FIFO in units of 32bit since this is the accessor window
4257      * (register width) we have.
4258      */
4259     buf = ((char *) buf) + size;
4260     while ((void *)p < buf)
4261         *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3));
4262
4263     spin_unlock(&smu->stb_context.lock);
4264
4265     return 0;
4266 }
4267
4268 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
4269     .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
4270     .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
4271     .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
4272     .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
4273     .i2c_init = sienna_cichlid_i2c_control_init,
4274     .i2c_fini = sienna_cichlid_i2c_control_fini,
4275     .print_clk_levels = sienna_cichlid_print_clk_levels,
4276     .force_clk_levels = sienna_cichlid_force_clk_levels,
4277     .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
4278     .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
4279     .display_config_changed = sienna_cichlid_display_config_changed,
4280     .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
4281     .is_dpm_running = sienna_cichlid_is_dpm_running,
4282     .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
4283     .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
4284     .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
4285     .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
4286     .set_watermarks_table = sienna_cichlid_set_watermarks_table,
4287     .read_sensor = sienna_cichlid_read_sensor,
4288     .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
4289     .set_performance_level = smu_v11_0_set_performance_level,
4290     .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
4291     .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
4292     .get_power_limit = sienna_cichlid_get_power_limit,
4293     .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
4294     .dump_pptable = sienna_cichlid_dump_pptable,
4295     .init_microcode = smu_v11_0_init_microcode,
4296     .load_microcode = smu_v11_0_load_microcode,
4297     .fini_microcode = smu_v11_0_fini_microcode,
4298     .init_smc_tables = sienna_cichlid_init_smc_tables,
4299     .fini_smc_tables = smu_v11_0_fini_smc_tables,
4300     .init_power = smu_v11_0_init_power,
4301     .fini_power = smu_v11_0_fini_power,
4302     .check_fw_status = smu_v11_0_check_fw_status,
4303     .setup_pptable = sienna_cichlid_setup_pptable,
4304     .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
4305     .check_fw_version = smu_v11_0_check_fw_version,
4306     .write_pptable = smu_cmn_write_pptable,
4307     .set_driver_table_location = smu_v11_0_set_driver_table_location,
4308     .set_tool_table_location = smu_v11_0_set_tool_table_location,
4309     .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
4310     .system_features_control = sienna_cichlid_system_features_control,
4311     .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
4312     .send_smc_msg = smu_cmn_send_smc_msg,
4313     .init_display_count = NULL,
4314     .set_allowed_mask = smu_v11_0_set_allowed_mask,
4315     .get_enabled_mask = smu_cmn_get_enabled_mask,
4316     .feature_is_enabled = smu_cmn_feature_is_enabled,
4317     .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
4318     .notify_display_change = NULL,
4319     .set_power_limit = smu_v11_0_set_power_limit,
4320     .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
4321     .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
4322     .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
4323     .set_min_dcef_deep_sleep = NULL,
4324     .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
4325     .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
4326     .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
4327     .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
4328     .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
4329     .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
4330     .gfx_off_control = smu_v11_0_gfx_off_control,
4331     .register_irq_handler = smu_v11_0_register_irq_handler,
4332     .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
4333     .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
4334     .baco_is_support = smu_v11_0_baco_is_support,
4335     .baco_get_state = smu_v11_0_baco_get_state,
4336     .baco_set_state = smu_v11_0_baco_set_state,
4337     .baco_enter = sienna_cichlid_baco_enter,
4338     .baco_exit = sienna_cichlid_baco_exit,
4339     .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
4340     .mode1_reset = smu_v11_0_mode1_reset,
4341     .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
4342     .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
4343     .set_default_od_settings = sienna_cichlid_set_default_od_settings,
4344     .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
4345     .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
4346     .run_btc = sienna_cichlid_run_btc,
4347     .set_power_source = smu_v11_0_set_power_source,
4348     .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
4349     .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
4350     .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
4351     .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
4352     .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
4353     .deep_sleep_control = smu_v11_0_deep_sleep_control,
4354     .get_fan_parameters = sienna_cichlid_get_fan_parameters,
4355     .interrupt_work = smu_v11_0_interrupt_work,
4356     .gpo_control = sienna_cichlid_gpo_control,
4357     .set_mp1_state = sienna_cichlid_set_mp1_state,
4358     .stb_collect_info = sienna_cichlid_stb_get_data_direct,
4359     .get_ecc_info = sienna_cichlid_get_ecc_info,
4360     .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
4361     .set_config_table = sienna_cichlid_set_config_table,
4362     .get_unique_id = sienna_cichlid_get_unique_id,
4363 };
4364
4365 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
4366 {
4367     smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
4368     smu->message_map = sienna_cichlid_message_map;
4369     smu->clock_map = sienna_cichlid_clk_map;
4370     smu->feature_map = sienna_cichlid_feature_mask_map;
4371     smu->table_map = sienna_cichlid_table_map;
4372     smu->pwr_src_map = sienna_cichlid_pwr_src_map;
4373     smu->workload_map = sienna_cichlid_workload_map;
4374     smu_v11_0_set_smu_mailbox_registers(smu);
4375 }