swsmu/inc/smu_v13_0_pptable.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #ifndef SMU_13_0_PPTABLE_H
0023 #define SMU_13_0_PPTABLE_H
0024
0025 #pragma pack(push, 1)
0026
0027 #define SMU_13_0_TABLE_FORMAT_REVISION                  1
0028
0029 //// POWERPLAYTABLE::ulPlatformCaps
0030 #define SMU_13_0_PP_PLATFORM_CAP_POWERPLAY              0x1
0031 #define SMU_13_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE       0x2
0032 #define SMU_13_0_PP_PLATFORM_CAP_HARDWAREDC             0x4
0033 #define SMU_13_0_PP_PLATFORM_CAP_BACO                   0x8
0034 #define SMU_13_0_PP_PLATFORM_CAP_MACO                   0x10
0035 #define SMU_13_0_PP_PLATFORM_CAP_SHADOWPSTATE           0x20
0036
0037 // SMU_13_0_PP_THERMALCONTROLLER - Thermal Controller Type
0038 #define SMU_13_0_PP_THERMALCONTROLLER_NONE              0
0039
0040 #define SMU_13_0_PP_OVERDRIVE_VERSION                   0x0800
0041 #define SMU_13_0_PP_POWERSAVINGCLOCK_VERSION            0x0100
0042
0043 enum SMU_13_0_ODFEATURE_CAP {
0044     SMU_13_0_ODCAP_GFXCLK_LIMITS = 0,
0045     SMU_13_0_ODCAP_GFXCLK_CURVE,
0046     SMU_13_0_ODCAP_UCLK_MAX,
0047     SMU_13_0_ODCAP_POWER_LIMIT,
0048     SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT,
0049     SMU_13_0_ODCAP_FAN_SPEED_MIN,
0050     SMU_13_0_ODCAP_TEMPERATURE_FAN,
0051     SMU_13_0_ODCAP_TEMPERATURE_SYSTEM,
0052     SMU_13_0_ODCAP_MEMORY_TIMING_TUNE,
0053     SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL,
0054     SMU_13_0_ODCAP_AUTO_UV_ENGINE,
0055     SMU_13_0_ODCAP_AUTO_OC_ENGINE,
0056     SMU_13_0_ODCAP_AUTO_OC_MEMORY,
0057     SMU_13_0_ODCAP_FAN_CURVE,
0058     SMU_13_0_ODCAP_COUNT,
0059 };
0060
0061 enum SMU_13_0_ODFEATURE_ID {
0062     SMU_13_0_ODFEATURE_GFXCLK_LIMITS        = 1 << SMU_13_0_ODCAP_GFXCLK_LIMITS,            //GFXCLK Limit feature
0063     SMU_13_0_ODFEATURE_GFXCLK_CURVE         = 1 << SMU_13_0_ODCAP_GFXCLK_CURVE,             //GFXCLK Curve feature
0064     SMU_13_0_ODFEATURE_UCLK_MAX             = 1 << SMU_13_0_ODCAP_UCLK_MAX,                 //UCLK Limit feature
0065     SMU_13_0_ODFEATURE_POWER_LIMIT          = 1 << SMU_13_0_ODCAP_POWER_LIMIT,              //Power Limit feature
0066     SMU_13_0_ODFEATURE_FAN_ACOUSTIC_LIMIT   = 1 << SMU_13_0_ODCAP_FAN_ACOUSTIC_LIMIT,       //Fan Acoustic RPM feature
0067     SMU_13_0_ODFEATURE_FAN_SPEED_MIN        = 1 << SMU_13_0_ODCAP_FAN_SPEED_MIN,            //Minimum Fan Speed feature
0068     SMU_13_0_ODFEATURE_TEMPERATURE_FAN      = 1 << SMU_13_0_ODCAP_TEMPERATURE_FAN,          //Fan Target Temperature Limit feature
0069     SMU_13_0_ODFEATURE_TEMPERATURE_SYSTEM   = 1 << SMU_13_0_ODCAP_TEMPERATURE_SYSTEM,       //Operating Temperature Limit feature
0070     SMU_13_0_ODFEATURE_MEMORY_TIMING_TUNE   = 1 << SMU_13_0_ODCAP_MEMORY_TIMING_TUNE,       //AC Timing Tuning feature
0071     SMU_13_0_ODFEATURE_FAN_ZERO_RPM_CONTROL = 1 << SMU_13_0_ODCAP_FAN_ZERO_RPM_CONTROL,     //Zero RPM feature
0072     SMU_13_0_ODFEATURE_AUTO_UV_ENGINE       = 1 << SMU_13_0_ODCAP_AUTO_UV_ENGINE,           //Auto Under Volt GFXCLK feature
0073     SMU_13_0_ODFEATURE_AUTO_OC_ENGINE       = 1 << SMU_13_0_ODCAP_AUTO_OC_ENGINE,           //Auto Over Clock GFXCLK feature
0074     SMU_13_0_ODFEATURE_AUTO_OC_MEMORY       = 1 << SMU_13_0_ODCAP_AUTO_OC_MEMORY,           //Auto Over Clock MCLK feature
0075     SMU_13_0_ODFEATURE_FAN_CURVE            = 1 << SMU_13_0_ODCAP_FAN_CURVE,                //Fan Curve feature
0076     SMU_13_0_ODFEATURE_COUNT                = 14,
0077 };
0078
0079 #define SMU_13_0_MAX_ODFEATURE    32          //Maximum Number of OD Features
0080
0081 enum SMU_13_0_ODSETTING_ID {
0082     SMU_13_0_ODSETTING_GFXCLKFMAX = 0,
0083     SMU_13_0_ODSETTING_GFXCLKFMIN,
0084     SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P1,
0085     SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
0086     SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P2,
0087     SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
0088     SMU_13_0_ODSETTING_VDDGFXCURVEFREQ_P3,
0089     SMU_13_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
0090     SMU_13_0_ODSETTING_UCLKFMAX,
0091     SMU_13_0_ODSETTING_POWERPERCENTAGE,
0092     SMU_13_0_ODSETTING_FANRPMMIN,
0093     SMU_13_0_ODSETTING_FANRPMACOUSTICLIMIT,
0094     SMU_13_0_ODSETTING_FANTARGETTEMPERATURE,
0095     SMU_13_0_ODSETTING_OPERATINGTEMPMAX,
0096     SMU_13_0_ODSETTING_ACTIMING,
0097     SMU_13_0_ODSETTING_FAN_ZERO_RPM_CONTROL,
0098     SMU_13_0_ODSETTING_AUTOUVENGINE,
0099     SMU_13_0_ODSETTING_AUTOOCENGINE,
0100     SMU_13_0_ODSETTING_AUTOOCMEMORY,
0101     SMU_13_0_ODSETTING_COUNT,
0102 };
0103
0104 #define SMU_13_0_MAX_ODSETTING    32          //Maximum Number of ODSettings
0105
0106 struct smu_13_0_overdrive_table {
0107     uint8_t  revision;                                        //Revision = SMU_11_0_PP_OVERDRIVE_VERSION
0108     uint8_t  reserve[3];                                      //Zero filled field reserved for future use
0109     uint32_t feature_count;                                   //Total number of supported features
0110     uint32_t setting_count;                                   //Total number of supported settings
0111     uint8_t  cap[SMU_13_0_MAX_ODFEATURE];                     //OD feature support flags
0112     uint32_t max[SMU_13_0_MAX_ODSETTING];                     //default maximum settings
0113     uint32_t min[SMU_13_0_MAX_ODSETTING];                     //default minimum settings
0114 };
0115
0116 enum SMU_13_0_PPCLOCK_ID {
0117     SMU_13_0_PPCLOCK_GFXCLK = 0,
0118     SMU_13_0_PPCLOCK_VCLK,
0119     SMU_13_0_PPCLOCK_DCLK,
0120     SMU_13_0_PPCLOCK_ECLK,
0121     SMU_13_0_PPCLOCK_SOCCLK,
0122     SMU_13_0_PPCLOCK_UCLK,
0123     SMU_13_0_PPCLOCK_DCEFCLK,
0124     SMU_13_0_PPCLOCK_DISPCLK,
0125     SMU_13_0_PPCLOCK_PIXCLK,
0126     SMU_13_0_PPCLOCK_PHYCLK,
0127     SMU_13_0_PPCLOCK_COUNT,
0128 };
0129 #define SMU_13_0_MAX_PPCLOCK      16          //Maximum Number of PP Clocks
0130
0131 struct smu_13_0_power_saving_clock_table {
0132     uint8_t  revision;                                        //Revision = SMU_11_0_PP_POWERSAVINGCLOCK_VERSION
0133     uint8_t  reserve[3];                                      //Zero filled field reserved for future use
0134     uint32_t count;                                           //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
0135     uint32_t max[SMU_13_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Maximum array In MHz
0136     uint32_t min[SMU_13_0_MAX_PPCLOCK];                       //PowerSavingClock Mode Clock Minimum array In MHz
0137 };
0138
0139 struct smu_13_0_powerplay_table {
0140     struct atom_common_table_header header;
0141     uint8_t  table_revision;
0142     uint16_t table_size;                          //Driver portion table size. The offset to smc_pptable including header size
0143     uint32_t golden_pp_id;
0144     uint32_t golden_revision;
0145     uint16_t format_id;
0146     uint32_t platform_caps;                       //POWERPLAYABLE::ulPlatformCaps
0147
0148     uint8_t  thermal_controller_type;             //one of SMU_13_0_PP_THERMALCONTROLLER
0149
0150     uint16_t small_power_limit1;
0151     uint16_t small_power_limit2;
0152     uint16_t boost_power_limit;
0153     uint16_t od_turbo_power_limit;                //Power limit setting for Turbo mode in Performance UI Tuning.
0154     uint16_t od_power_save_power_limit;           //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
0155     uint16_t software_shutdown_temp;
0156
0157     uint16_t reserve[6];                          //Zero filled field reserved for future use
0158
0159     struct smu_13_0_power_saving_clock_table      power_saving_clock;
0160     struct smu_13_0_overdrive_table               overdrive_table;
0161
0162 #ifndef SMU_13_0_PARTIAL_PPTABLE
0163     PPTable_t smc_pptable;                        //PPTable_t in driver_if.h
0164 #endif
0165 };
0166
0167 #pragma pack(pop)
0168
0169 #endif