swsmu/inc/smu_v13_0.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __SMU_V13_0_H__
0024 #define __SMU_V13_0_H__
0025
0026 #include "amdgpu_smu.h"
0027
0028 #define SMU13_DRIVER_IF_VERSION_INV 0xFFFFFFFF
0029 #define SMU13_DRIVER_IF_VERSION_YELLOW_CARP 0x04
0030 #define SMU13_DRIVER_IF_VERSION_ALDE 0x08
0031 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_4 0x05
0032 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_5 0x04
0033 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_0 0x30
0034 #define SMU13_DRIVER_IF_VERSION_SMU_V13_0_7 0x2C
0035
0036 #define SMU13_MODE1_RESET_WAIT_TIME_IN_MS 500  //500ms
0037
0038 /* MP Apertures */
0039 #define MP0_Public          0x03800000
0040 #define MP0_SRAM            0x03900000
0041 #define MP1_Public          0x03b00000
0042 #define MP1_SRAM            0x03c00004
0043
0044 /* address block */
0045 #define smnMP1_FIRMWARE_FLAGS       0x3010024
0046 #define smnMP1_V13_0_4_FIRMWARE_FLAGS   0x3010028
0047 #define smnMP0_FW_INTF          0x30101c0
0048 #define smnMP1_PUB_CTRL         0x3010b14
0049
0050 #define TEMP_RANGE_MIN          (0)
0051 #define TEMP_RANGE_MAX          (80 * 1000)
0052
0053 #define SMU13_TOOL_SIZE         0x19000
0054
0055 #define MAX_DPM_LEVELS 16
0056 #define MAX_PCIE_CONF 3
0057
0058 #define CTF_OFFSET_EDGE         5
0059 #define CTF_OFFSET_HOTSPOT      5
0060 #define CTF_OFFSET_MEM          5
0061
0062 struct smu_13_0_max_sustainable_clocks {
0063     uint32_t display_clock;
0064     uint32_t phy_clock;
0065     uint32_t pixel_clock;
0066     uint32_t uclock;
0067     uint32_t dcef_clock;
0068     uint32_t soc_clock;
0069 };
0070
0071 struct smu_13_0_dpm_clk_level {
0072     bool                enabled;
0073     uint32_t            value;
0074 };
0075
0076 struct smu_13_0_dpm_table {
0077     uint32_t            min;        /* MHz */
0078     uint32_t            max;        /* MHz */
0079     uint32_t            count;
0080     bool                is_fine_grained;
0081     struct smu_13_0_dpm_clk_level   dpm_levels[MAX_DPM_LEVELS];
0082 };
0083
0084 struct smu_13_0_pcie_table {
0085     uint8_t  pcie_gen[MAX_PCIE_CONF];
0086     uint8_t  pcie_lane[MAX_PCIE_CONF];
0087     uint16_t clk_freq[MAX_PCIE_CONF];
0088     uint32_t num_of_link_levels;
0089 };
0090
0091 struct smu_13_0_dpm_tables {
0092     struct smu_13_0_dpm_table        soc_table;
0093     struct smu_13_0_dpm_table        gfx_table;
0094     struct smu_13_0_dpm_table        uclk_table;
0095     struct smu_13_0_dpm_table        eclk_table;
0096     struct smu_13_0_dpm_table        vclk_table;
0097     struct smu_13_0_dpm_table        dclk_table;
0098     struct smu_13_0_dpm_table        dcef_table;
0099     struct smu_13_0_dpm_table        pixel_table;
0100     struct smu_13_0_dpm_table        display_table;
0101     struct smu_13_0_dpm_table        phy_table;
0102     struct smu_13_0_dpm_table        fclk_table;
0103     struct smu_13_0_pcie_table       pcie_table;
0104 };
0105
0106 struct smu_13_0_dpm_context {
0107     struct smu_13_0_dpm_tables  dpm_tables;
0108     uint32_t                    workload_policy_mask;
0109     uint32_t                    dcef_min_ds_clk;
0110 };
0111
0112 enum smu_13_0_power_state {
0113     SMU_13_0_POWER_STATE__D0 = 0,
0114     SMU_13_0_POWER_STATE__D1,
0115     SMU_13_0_POWER_STATE__D3, /* Sleep*/
0116     SMU_13_0_POWER_STATE__D4, /* Hibernate*/
0117     SMU_13_0_POWER_STATE__D5, /* Power off*/
0118 };
0119
0120 struct smu_13_0_power_context {
0121     uint32_t    power_source;
0122     uint8_t     in_power_limit_boost_mode;
0123     enum smu_13_0_power_state power_state;
0124 };
0125
0126 enum smu_v13_0_baco_seq {
0127     BACO_SEQ_BACO = 0,
0128     BACO_SEQ_MSR,
0129     BACO_SEQ_BAMACO,
0130     BACO_SEQ_ULPS,
0131     BACO_SEQ_COUNT,
0132 };
0133
0134 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
0135
0136 int smu_v13_0_init_microcode(struct smu_context *smu);
0137
0138 void smu_v13_0_fini_microcode(struct smu_context *smu);
0139
0140 int smu_v13_0_load_microcode(struct smu_context *smu);
0141
0142 int smu_v13_0_init_smc_tables(struct smu_context *smu);
0143
0144 int smu_v13_0_fini_smc_tables(struct smu_context *smu);
0145
0146 int smu_v13_0_init_power(struct smu_context *smu);
0147
0148 int smu_v13_0_fini_power(struct smu_context *smu);
0149
0150 int smu_v13_0_check_fw_status(struct smu_context *smu);
0151
0152 int smu_v13_0_setup_pptable(struct smu_context *smu);
0153
0154 int smu_v13_0_get_vbios_bootup_values(struct smu_context *smu);
0155
0156 int smu_v13_0_check_fw_version(struct smu_context *smu);
0157
0158 int smu_v13_0_set_driver_table_location(struct smu_context *smu);
0159
0160 int smu_v13_0_set_tool_table_location(struct smu_context *smu);
0161
0162 int smu_v13_0_notify_memory_pool_location(struct smu_context *smu);
0163
0164 int smu_v13_0_system_features_control(struct smu_context *smu,
0165                       bool en);
0166
0167 int smu_v13_0_init_display_count(struct smu_context *smu, uint32_t count);
0168
0169 int smu_v13_0_set_allowed_mask(struct smu_context *smu);
0170
0171 int smu_v13_0_notify_display_change(struct smu_context *smu);
0172
0173 int smu_v13_0_get_current_power_limit(struct smu_context *smu,
0174                       uint32_t *power_limit);
0175
0176 int smu_v13_0_set_power_limit(struct smu_context *smu,
0177                   enum smu_ppt_limit_type limit_type,
0178                   uint32_t limit);
0179
0180 int smu_v13_0_init_max_sustainable_clocks(struct smu_context *smu);
0181
0182 int smu_v13_0_enable_thermal_alert(struct smu_context *smu);
0183
0184 int smu_v13_0_disable_thermal_alert(struct smu_context *smu);
0185
0186 int smu_v13_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
0187
0188 int smu_v13_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
0189
0190 int
0191 smu_v13_0_display_clock_voltage_request(struct smu_context *smu,
0192                     struct pp_display_clock_request
0193                     *clock_req);
0194
0195 uint32_t
0196 smu_v13_0_get_fan_control_mode(struct smu_context *smu);
0197
0198 int
0199 smu_v13_0_set_fan_control_mode(struct smu_context *smu,
0200                    uint32_t mode);
0201
0202 int smu_v13_0_set_fan_speed_pwm(struct smu_context *smu,
0203                 uint32_t speed);
0204
0205 int smu_v13_0_set_fan_speed_rpm(struct smu_context *smu,
0206                 uint32_t speed);
0207
0208 int smu_v13_0_set_xgmi_pstate(struct smu_context *smu,
0209                   uint32_t pstate);
0210
0211 int smu_v13_0_gfx_off_control(struct smu_context *smu, bool enable);
0212
0213 int smu_v13_0_register_irq_handler(struct smu_context *smu);
0214
0215 int smu_v13_0_set_azalia_d3_pme(struct smu_context *smu);
0216
0217 int smu_v13_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
0218                            struct pp_smu_nv_clock_table *max_clocks);
0219
0220 bool smu_v13_0_baco_is_support(struct smu_context *smu);
0221
0222 enum smu_baco_state smu_v13_0_baco_get_state(struct smu_context *smu);
0223
0224 int smu_v13_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
0225
0226 int smu_v13_0_baco_enter(struct smu_context *smu);
0227 int smu_v13_0_baco_exit(struct smu_context *smu);
0228
0229 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
0230                     uint32_t *min, uint32_t *max);
0231
0232 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
0233                       uint32_t min, uint32_t max);
0234
0235 int smu_v13_0_set_hard_freq_limited_range(struct smu_context *smu,
0236                       enum smu_clk_type clk_type,
0237                       uint32_t min,
0238                       uint32_t max);
0239
0240 int smu_v13_0_set_performance_level(struct smu_context *smu,
0241                     enum amd_dpm_forced_level level);
0242
0243 int smu_v13_0_set_power_source(struct smu_context *smu,
0244                    enum smu_power_src_type power_src);
0245
0246 int smu_v13_0_set_single_dpm_table(struct smu_context *smu,
0247                    enum smu_clk_type clk_type,
0248                    struct smu_13_0_dpm_table *single_dpm_table);
0249
0250 int smu_v13_0_get_dpm_level_range(struct smu_context *smu,
0251                   enum smu_clk_type clk_type,
0252                   uint32_t *min_value,
0253                   uint32_t *max_value);
0254
0255 int smu_v13_0_get_current_pcie_link_width_level(struct smu_context *smu);
0256
0257 int smu_v13_0_get_current_pcie_link_width(struct smu_context *smu);
0258
0259 int smu_v13_0_get_current_pcie_link_speed_level(struct smu_context *smu);
0260
0261 int smu_v13_0_get_current_pcie_link_speed(struct smu_context *smu);
0262
0263 int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
0264                   bool enablement);
0265
0266 int smu_v13_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
0267                  uint64_t event_arg);
0268
0269 int smu_v13_0_set_vcn_enable(struct smu_context *smu,
0270                  bool enable);
0271
0272 int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
0273                   bool enable);
0274
0275 int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
0276
0277 int smu_v13_0_run_btc(struct smu_context *smu);
0278
0279 int smu_v13_0_deep_sleep_control(struct smu_context *smu,
0280                  bool enablement);
0281
0282 int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
0283
0284 int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
0285                 enum PP_OD_DPM_TABLE_COMMAND type,
0286                 long input[],
0287                 uint32_t size);
0288
0289 int smu_v13_0_set_default_dpm_tables(struct smu_context *smu);
0290
0291 void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu);
0292
0293 int smu_v13_0_mode1_reset(struct smu_context *smu);
0294
0295 int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
0296                     void **table,
0297                     uint32_t *size,
0298                     uint32_t pptable_id);
0299
0300 #endif
0301 #endif