swsmu/inc/smu_v12_0.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __SMU_V12_0_H__
0024 #define __SMU_V12_0_H__
0025
0026 #include "amdgpu_smu.h"
0027
0028 /* MP Apertures */
0029 #define MP0_Public          0x03800000
0030 #define MP0_SRAM            0x03900000
0031 #define MP1_Public          0x03b00000
0032 #define MP1_SRAM            0x03c00004
0033
0034 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
0035
0036 int smu_v12_0_check_fw_status(struct smu_context *smu);
0037
0038 int smu_v12_0_check_fw_version(struct smu_context *smu);
0039
0040 int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
0041
0042 int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
0043
0044 int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
0045
0046 int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
0047
0048 uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
0049
0050 int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
0051
0052 int smu_v12_0_fini_smc_tables(struct smu_context *smu);
0053
0054 int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
0055
0056 int smu_v12_0_mode2_reset(struct smu_context *smu);
0057
0058 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
0059                 uint32_t min, uint32_t max);
0060
0061 int smu_v12_0_set_driver_table_location(struct smu_context *smu);
0062
0063 int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu);
0064
0065 #endif
0066 #endif