swsmu/inc/smu_v11_0.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __SMU_V11_0_H__
0024 #define __SMU_V11_0_H__
0025
0026 #include "amdgpu_smu.h"
0027
0028 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
0029 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
0030 #define SMU11_DRIVER_IF_VERSION_NV10 0x37
0031 #define SMU11_DRIVER_IF_VERSION_NV12 0x38
0032 #define SMU11_DRIVER_IF_VERSION_NV14 0x38
0033 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x40
0034 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xE
0035 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x03
0036 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
0037 #define SMU11_DRIVER_IF_VERSION_Beige_Goby 0xD
0038 #define SMU11_DRIVER_IF_VERSION_Cyan_Skillfish 0x8
0039
0040 /* MP Apertures */
0041 #define MP0_Public          0x03800000
0042 #define MP0_SRAM            0x03900000
0043 #define MP1_Public          0x03b00000
0044 #define MP1_SRAM            0x03c00004
0045
0046 /* address block */
0047 #define smnMP1_FIRMWARE_FLAGS       0x3010024
0048 #define smnMP0_FW_INTF          0x30101c0
0049 #define smnMP1_PUB_CTRL         0x3010b14
0050
0051 #define TEMP_RANGE_MIN          (0)
0052 #define TEMP_RANGE_MAX          (80 * 1000)
0053
0054 #define SMU11_TOOL_SIZE         0x19000
0055
0056 #define MAX_DPM_LEVELS 16
0057 #define MAX_PCIE_CONF 2
0058
0059 #define CTF_OFFSET_EDGE         5
0060 #define CTF_OFFSET_HOTSPOT      5
0061 #define CTF_OFFSET_MEM          5
0062
0063 #define LINK_WIDTH_MAX          6
0064 #define LINK_SPEED_MAX          3
0065
0066 static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
0067 static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
0068
0069 static const
0070 struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =
0071 {
0072     {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
0073     { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
0074 };
0075
0076 struct smu_11_0_max_sustainable_clocks {
0077     uint32_t display_clock;
0078     uint32_t phy_clock;
0079     uint32_t pixel_clock;
0080     uint32_t uclock;
0081     uint32_t dcef_clock;
0082     uint32_t soc_clock;
0083 };
0084
0085 struct smu_11_0_dpm_clk_level {
0086     bool                enabled;
0087     uint32_t            value;
0088 };
0089
0090 struct smu_11_0_dpm_table {
0091     uint32_t            min;        /* MHz */
0092     uint32_t            max;        /* MHz */
0093     uint32_t            count;
0094     bool                is_fine_grained;
0095     struct smu_11_0_dpm_clk_level   dpm_levels[MAX_DPM_LEVELS];
0096 };
0097
0098 struct smu_11_0_pcie_table {
0099         uint8_t  pcie_gen[MAX_PCIE_CONF];
0100         uint8_t  pcie_lane[MAX_PCIE_CONF];
0101 };
0102
0103 struct smu_11_0_dpm_tables {
0104     struct smu_11_0_dpm_table        soc_table;
0105     struct smu_11_0_dpm_table        gfx_table;
0106     struct smu_11_0_dpm_table        uclk_table;
0107     struct smu_11_0_dpm_table        eclk_table;
0108     struct smu_11_0_dpm_table        vclk_table;
0109     struct smu_11_0_dpm_table        vclk1_table;
0110     struct smu_11_0_dpm_table        dclk_table;
0111     struct smu_11_0_dpm_table        dclk1_table;
0112     struct smu_11_0_dpm_table        dcef_table;
0113     struct smu_11_0_dpm_table        pixel_table;
0114     struct smu_11_0_dpm_table        display_table;
0115     struct smu_11_0_dpm_table        phy_table;
0116     struct smu_11_0_dpm_table        fclk_table;
0117     struct smu_11_0_pcie_table       pcie_table;
0118 };
0119
0120 struct smu_11_0_dpm_context {
0121     struct smu_11_0_dpm_tables  dpm_tables;
0122     uint32_t                    workload_policy_mask;
0123     uint32_t                    dcef_min_ds_clk;
0124 };
0125
0126 enum smu_11_0_power_state {
0127     SMU_11_0_POWER_STATE__D0 = 0,
0128     SMU_11_0_POWER_STATE__D1,
0129     SMU_11_0_POWER_STATE__D3, /* Sleep*/
0130     SMU_11_0_POWER_STATE__D4, /* Hibernate*/
0131     SMU_11_0_POWER_STATE__D5, /* Power off*/
0132 };
0133
0134 struct smu_11_0_power_context {
0135     uint32_t    power_source;
0136     uint8_t     in_power_limit_boost_mode;
0137     enum smu_11_0_power_state power_state;
0138 };
0139
0140 struct smu_11_5_power_context {
0141     uint32_t    power_source;
0142     uint8_t     in_power_limit_boost_mode;
0143     enum smu_11_0_power_state power_state;
0144
0145     uint32_t    current_fast_ppt_limit;
0146     uint32_t    default_fast_ppt_limit;
0147     uint32_t    max_fast_ppt_limit;
0148 };
0149
0150 enum smu_v11_0_baco_seq {
0151     BACO_SEQ_BACO = 0,
0152     BACO_SEQ_MSR,
0153     BACO_SEQ_BAMACO,
0154     BACO_SEQ_ULPS,
0155     BACO_SEQ_COUNT,
0156 };
0157
0158 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
0159
0160 int smu_v11_0_init_microcode(struct smu_context *smu);
0161
0162 void smu_v11_0_fini_microcode(struct smu_context *smu);
0163
0164 int smu_v11_0_load_microcode(struct smu_context *smu);
0165
0166 int smu_v11_0_init_smc_tables(struct smu_context *smu);
0167
0168 int smu_v11_0_fini_smc_tables(struct smu_context *smu);
0169
0170 int smu_v11_0_init_power(struct smu_context *smu);
0171
0172 int smu_v11_0_fini_power(struct smu_context *smu);
0173
0174 int smu_v11_0_check_fw_status(struct smu_context *smu);
0175
0176 int smu_v11_0_setup_pptable(struct smu_context *smu);
0177
0178 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
0179
0180 int smu_v11_0_check_fw_version(struct smu_context *smu);
0181
0182 int smu_v11_0_set_driver_table_location(struct smu_context *smu);
0183
0184 int smu_v11_0_set_tool_table_location(struct smu_context *smu);
0185
0186 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
0187
0188 int smu_v11_0_system_features_control(struct smu_context *smu,
0189                          bool en);
0190
0191 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
0192
0193 int smu_v11_0_set_allowed_mask(struct smu_context *smu);
0194
0195 int smu_v11_0_notify_display_change(struct smu_context *smu);
0196
0197 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
0198                       uint32_t *power_limit);
0199
0200 int smu_v11_0_set_power_limit(struct smu_context *smu,
0201                   enum smu_ppt_limit_type limit_type,
0202                   uint32_t limit);
0203
0204 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
0205
0206 int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
0207
0208 int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
0209
0210 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
0211
0212 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
0213
0214 int
0215 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
0216                     struct pp_display_clock_request
0217                     *clock_req);
0218
0219 uint32_t
0220 smu_v11_0_get_fan_control_mode(struct smu_context *smu);
0221
0222 int
0223 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
0224                    uint32_t mode);
0225
0226 int smu_v11_0_set_fan_speed_pwm(struct smu_context *smu,
0227                     uint32_t speed);
0228
0229 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
0230                 uint32_t speed);
0231
0232 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
0233                     uint32_t *speed);
0234
0235 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
0236                 uint32_t *speed);
0237
0238 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
0239                      uint32_t pstate);
0240
0241 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
0242
0243 int smu_v11_0_register_irq_handler(struct smu_context *smu);
0244
0245 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
0246
0247 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
0248         struct pp_smu_nv_clock_table *max_clocks);
0249
0250 bool smu_v11_0_baco_is_support(struct smu_context *smu);
0251
0252 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
0253
0254 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
0255
0256 int smu_v11_0_baco_enter(struct smu_context *smu);
0257 int smu_v11_0_baco_exit(struct smu_context *smu);
0258
0259 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
0260                       enum smu_v11_0_baco_seq baco_seq);
0261
0262 int smu_v11_0_mode1_reset(struct smu_context *smu);
0263
0264 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
0265                          uint32_t *min, uint32_t *max);
0266
0267 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
0268                 uint32_t min, uint32_t max);
0269
0270 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
0271                       enum smu_clk_type clk_type,
0272                       uint32_t min,
0273                       uint32_t max);
0274
0275 int smu_v11_0_set_performance_level(struct smu_context *smu,
0276                     enum amd_dpm_forced_level level);
0277
0278 int smu_v11_0_set_power_source(struct smu_context *smu,
0279                    enum smu_power_src_type power_src);
0280
0281 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
0282                     enum smu_clk_type clk_type,
0283                     uint16_t level,
0284                     uint32_t *value);
0285
0286 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
0287                   enum smu_clk_type clk_type,
0288                   uint32_t *value);
0289
0290 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
0291                    enum smu_clk_type clk_type,
0292                    struct smu_11_0_dpm_table *single_dpm_table);
0293
0294 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
0295                   enum smu_clk_type clk_type,
0296                   uint32_t *min_value,
0297                   uint32_t *max_value);
0298
0299 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
0300
0301 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
0302
0303 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
0304
0305 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
0306
0307 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
0308                   bool enablement);
0309
0310 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
0311                  bool enablement);
0312
0313 void smu_v11_0_interrupt_work(struct smu_context *smu);
0314
0315 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
0316
0317 int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
0318
0319 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
0320
0321 #endif
0322 #endif