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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #ifndef __AMDGPU_SMU_H__
0023 #define __AMDGPU_SMU_H__
0024 
0025 #include "amdgpu.h"
0026 #include "kgd_pp_interface.h"
0027 #include "dm_pp_interface.h"
0028 #include "dm_pp_smu.h"
0029 #include "smu_types.h"
0030 #include "linux/firmware.h"
0031 
0032 #define SMU_THERMAL_MINIMUM_ALERT_TEMP      0
0033 #define SMU_THERMAL_MAXIMUM_ALERT_TEMP      255
0034 #define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES   1000
0035 #define SMU_FW_NAME_LEN         0x24
0036 
0037 #define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
0038 #define SMU_CUSTOM_FAN_SPEED_RPM     (1 << 1)
0039 #define SMU_CUSTOM_FAN_SPEED_PWM     (1 << 2)
0040 
0041 // Power Throttlers
0042 #define SMU_THROTTLER_PPT0_BIT          0
0043 #define SMU_THROTTLER_PPT1_BIT          1
0044 #define SMU_THROTTLER_PPT2_BIT          2
0045 #define SMU_THROTTLER_PPT3_BIT          3
0046 #define SMU_THROTTLER_SPL_BIT           4
0047 #define SMU_THROTTLER_FPPT_BIT          5
0048 #define SMU_THROTTLER_SPPT_BIT          6
0049 #define SMU_THROTTLER_SPPT_APU_BIT      7
0050 
0051 // Current Throttlers
0052 #define SMU_THROTTLER_TDC_GFX_BIT       16
0053 #define SMU_THROTTLER_TDC_SOC_BIT       17
0054 #define SMU_THROTTLER_TDC_MEM_BIT       18
0055 #define SMU_THROTTLER_TDC_VDD_BIT       19
0056 #define SMU_THROTTLER_TDC_CVIP_BIT      20
0057 #define SMU_THROTTLER_EDC_CPU_BIT       21
0058 #define SMU_THROTTLER_EDC_GFX_BIT       22
0059 #define SMU_THROTTLER_APCC_BIT          23
0060 
0061 // Temperature
0062 #define SMU_THROTTLER_TEMP_GPU_BIT      32
0063 #define SMU_THROTTLER_TEMP_CORE_BIT     33
0064 #define SMU_THROTTLER_TEMP_MEM_BIT      34
0065 #define SMU_THROTTLER_TEMP_EDGE_BIT     35
0066 #define SMU_THROTTLER_TEMP_HOTSPOT_BIT      36
0067 #define SMU_THROTTLER_TEMP_SOC_BIT      37
0068 #define SMU_THROTTLER_TEMP_VR_GFX_BIT       38
0069 #define SMU_THROTTLER_TEMP_VR_SOC_BIT       39
0070 #define SMU_THROTTLER_TEMP_VR_MEM0_BIT      40
0071 #define SMU_THROTTLER_TEMP_VR_MEM1_BIT      41
0072 #define SMU_THROTTLER_TEMP_LIQUID0_BIT      42
0073 #define SMU_THROTTLER_TEMP_LIQUID1_BIT      43
0074 #define SMU_THROTTLER_VRHOT0_BIT        44
0075 #define SMU_THROTTLER_VRHOT1_BIT        45
0076 #define SMU_THROTTLER_PROCHOT_CPU_BIT       46
0077 #define SMU_THROTTLER_PROCHOT_GFX_BIT       47
0078 
0079 // Other
0080 #define SMU_THROTTLER_PPM_BIT           56
0081 #define SMU_THROTTLER_FIT_BIT           57
0082 
0083 struct smu_hw_power_state {
0084     unsigned int magic;
0085 };
0086 
0087 struct smu_power_state;
0088 
0089 enum smu_state_ui_label {
0090     SMU_STATE_UI_LABEL_NONE,
0091     SMU_STATE_UI_LABEL_BATTERY,
0092     SMU_STATE_UI_TABEL_MIDDLE_LOW,
0093     SMU_STATE_UI_LABEL_BALLANCED,
0094     SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
0095     SMU_STATE_UI_LABEL_PERFORMANCE,
0096     SMU_STATE_UI_LABEL_BACO,
0097 };
0098 
0099 enum smu_state_classification_flag {
0100     SMU_STATE_CLASSIFICATION_FLAG_BOOT                     = 0x0001,
0101     SMU_STATE_CLASSIFICATION_FLAG_THERMAL                  = 0x0002,
0102     SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE      = 0x0004,
0103     SMU_STATE_CLASSIFICATION_FLAG_RESET                    = 0x0008,
0104     SMU_STATE_CLASSIFICATION_FLAG_FORCED                   = 0x0010,
0105     SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE      = 0x0020,
0106     SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE      = 0x0040,
0107     SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE           = 0x0080,
0108     SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE   = 0x0100,
0109     SMU_STATE_CLASSIFICATION_FLAG_UVD                      = 0x0200,
0110     SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW       = 0x0400,
0111     SMU_STATE_CLASSIFICATION_FLAG_ACPI                     = 0x0800,
0112     SMU_STATE_CLASSIFICATION_FLAG_HD2                      = 0x1000,
0113     SMU_STATE_CLASSIFICATION_FLAG_UVD_HD                   = 0x2000,
0114     SMU_STATE_CLASSIFICATION_FLAG_UVD_SD                   = 0x4000,
0115     SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE      = 0x8000,
0116     SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE   = 0x10000,
0117     SMU_STATE_CLASSIFICATION_FLAG_BACO                     = 0x20000,
0118     SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2      = 0x40000,
0119     SMU_STATE_CLASSIFICATION_FLAG_ULV                      = 0x80000,
0120     SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC                  = 0x100000,
0121 };
0122 
0123 struct smu_state_classification_block {
0124     enum smu_state_ui_label         ui_label;
0125     enum smu_state_classification_flag  flags;
0126     int                          bios_index;
0127     bool                      temporary_state;
0128     bool                      to_be_deleted;
0129 };
0130 
0131 struct smu_state_pcie_block {
0132     unsigned int lanes;
0133 };
0134 
0135 enum smu_refreshrate_source {
0136     SMU_REFRESHRATE_SOURCE_EDID,
0137     SMU_REFRESHRATE_SOURCE_EXPLICIT
0138 };
0139 
0140 struct smu_state_display_block {
0141     bool              disable_frame_modulation;
0142     bool              limit_refreshrate;
0143     enum smu_refreshrate_source refreshrate_source;
0144     int                  explicit_refreshrate;
0145     int                  edid_refreshrate_index;
0146     bool              enable_vari_bright;
0147 };
0148 
0149 struct smu_state_memory_block {
0150     bool              dll_off;
0151     uint8_t                 m3arb;
0152     uint8_t                 unused[3];
0153 };
0154 
0155 struct smu_state_software_algorithm_block {
0156     bool disable_load_balancing;
0157     bool enable_sleep_for_timestamps;
0158 };
0159 
0160 struct smu_temperature_range {
0161     int min;
0162     int max;
0163     int edge_emergency_max;
0164     int hotspot_min;
0165     int hotspot_crit_max;
0166     int hotspot_emergency_max;
0167     int mem_min;
0168     int mem_crit_max;
0169     int mem_emergency_max;
0170     int software_shutdown_temp;
0171 };
0172 
0173 struct smu_state_validation_block {
0174     bool single_display_only;
0175     bool disallow_on_dc;
0176     uint8_t supported_power_levels;
0177 };
0178 
0179 struct smu_uvd_clocks {
0180     uint32_t vclk;
0181     uint32_t dclk;
0182 };
0183 
0184 /**
0185 * Structure to hold a SMU Power State.
0186 */
0187 struct smu_power_state {
0188     uint32_t                                      id;
0189     struct list_head                              ordered_list;
0190     struct list_head                              all_states_list;
0191 
0192     struct smu_state_classification_block         classification;
0193     struct smu_state_validation_block             validation;
0194     struct smu_state_pcie_block                   pcie;
0195     struct smu_state_display_block                display;
0196     struct smu_state_memory_block                 memory;
0197     struct smu_state_software_algorithm_block     software;
0198     struct smu_uvd_clocks                         uvd_clocks;
0199     struct smu_hw_power_state                     hardware;
0200 };
0201 
0202 enum smu_power_src_type
0203 {
0204     SMU_POWER_SOURCE_AC,
0205     SMU_POWER_SOURCE_DC,
0206     SMU_POWER_SOURCE_COUNT,
0207 };
0208 
0209 enum smu_ppt_limit_type
0210 {
0211     SMU_DEFAULT_PPT_LIMIT = 0,
0212     SMU_FAST_PPT_LIMIT,
0213 };
0214 
0215 enum smu_ppt_limit_level
0216 {
0217     SMU_PPT_LIMIT_MIN = -1,
0218     SMU_PPT_LIMIT_CURRENT,
0219     SMU_PPT_LIMIT_DEFAULT,
0220     SMU_PPT_LIMIT_MAX,
0221 };
0222 
0223 enum smu_memory_pool_size
0224 {
0225     SMU_MEMORY_POOL_SIZE_ZERO   = 0,
0226     SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
0227     SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
0228     SMU_MEMORY_POOL_SIZE_1_GB   = 0x40000000,
0229     SMU_MEMORY_POOL_SIZE_2_GB   = 0x80000000,
0230 };
0231 
0232 struct smu_user_dpm_profile {
0233     uint32_t fan_mode;
0234     uint32_t power_limit;
0235     uint32_t fan_speed_pwm;
0236     uint32_t fan_speed_rpm;
0237     uint32_t flags;
0238     uint32_t user_od;
0239 
0240     /* user clock state information */
0241     uint32_t clk_mask[SMU_CLK_COUNT];
0242     uint32_t clk_dependency;
0243 };
0244 
0245 #define SMU_TABLE_INIT(tables, table_id, s, a, d)   \
0246     do {                        \
0247         tables[table_id].size = s;      \
0248         tables[table_id].align = a;     \
0249         tables[table_id].domain = d;        \
0250     } while (0)
0251 
0252 struct smu_table {
0253     uint64_t size;
0254     uint32_t align;
0255     uint8_t domain;
0256     uint64_t mc_address;
0257     void *cpu_addr;
0258     struct amdgpu_bo *bo;
0259 };
0260 
0261 enum smu_perf_level_designation {
0262     PERF_LEVEL_ACTIVITY,
0263     PERF_LEVEL_POWER_CONTAINMENT,
0264 };
0265 
0266 struct smu_performance_level {
0267     uint32_t core_clock;
0268     uint32_t memory_clock;
0269     uint32_t vddc;
0270     uint32_t vddci;
0271     uint32_t non_local_mem_freq;
0272     uint32_t non_local_mem_width;
0273 };
0274 
0275 struct smu_clock_info {
0276     uint32_t min_mem_clk;
0277     uint32_t max_mem_clk;
0278     uint32_t min_eng_clk;
0279     uint32_t max_eng_clk;
0280     uint32_t min_bus_bandwidth;
0281     uint32_t max_bus_bandwidth;
0282 };
0283 
0284 struct smu_bios_boot_up_values
0285 {
0286     uint32_t            revision;
0287     uint32_t            gfxclk;
0288     uint32_t            uclk;
0289     uint32_t            socclk;
0290     uint32_t            dcefclk;
0291     uint32_t            eclk;
0292     uint32_t            vclk;
0293     uint32_t            dclk;
0294     uint16_t            vddc;
0295     uint16_t            vddci;
0296     uint16_t            mvddc;
0297     uint16_t            vdd_gfx;
0298     uint8_t             cooling_id;
0299     uint32_t            pp_table_id;
0300     uint32_t            format_revision;
0301     uint32_t            content_revision;
0302     uint32_t            fclk;
0303     uint32_t            lclk;
0304     uint32_t            firmware_caps;
0305 };
0306 
0307 enum smu_table_id
0308 {
0309     SMU_TABLE_PPTABLE = 0,
0310     SMU_TABLE_WATERMARKS,
0311     SMU_TABLE_CUSTOM_DPM,
0312     SMU_TABLE_DPMCLOCKS,
0313     SMU_TABLE_AVFS,
0314     SMU_TABLE_AVFS_PSM_DEBUG,
0315     SMU_TABLE_AVFS_FUSE_OVERRIDE,
0316     SMU_TABLE_PMSTATUSLOG,
0317     SMU_TABLE_SMU_METRICS,
0318     SMU_TABLE_DRIVER_SMU_CONFIG,
0319     SMU_TABLE_ACTIVITY_MONITOR_COEFF,
0320     SMU_TABLE_OVERDRIVE,
0321     SMU_TABLE_I2C_COMMANDS,
0322     SMU_TABLE_PACE,
0323     SMU_TABLE_ECCINFO,
0324     SMU_TABLE_COMBO_PPTABLE,
0325     SMU_TABLE_COUNT,
0326 };
0327 
0328 struct smu_table_context
0329 {
0330     void                *power_play_table;
0331     uint32_t            power_play_table_size;
0332     void                *hardcode_pptable;
0333     unsigned long           metrics_time;
0334     void                *metrics_table;
0335     void                *clocks_table;
0336     void                *watermarks_table;
0337 
0338     void                *max_sustainable_clocks;
0339     struct smu_bios_boot_up_values  boot_values;
0340     void                *driver_pptable;
0341     void                *combo_pptable;
0342     void                            *ecc_table;
0343     void                *driver_smu_config_table;
0344     struct smu_table        tables[SMU_TABLE_COUNT];
0345     /*
0346      * The driver table is just a staging buffer for
0347      * uploading/downloading content from the SMU.
0348      *
0349      * And the table_id for SMU_MSG_TransferTableSmu2Dram/
0350      * SMU_MSG_TransferTableDram2Smu instructs SMU
0351      * which content driver is interested.
0352      */
0353     struct smu_table        driver_table;
0354     struct smu_table        memory_pool;
0355     struct smu_table        dummy_read_1_table;
0356     uint8_t                         thermal_controller_type;
0357 
0358     void                *overdrive_table;
0359     void                            *boot_overdrive_table;
0360     void                *user_overdrive_table;
0361 
0362     uint32_t            gpu_metrics_table_size;
0363     void                *gpu_metrics_table;
0364 };
0365 
0366 struct smu_dpm_context {
0367     uint32_t dpm_context_size;
0368     void *dpm_context;
0369     void *golden_dpm_context;
0370     enum amd_dpm_forced_level dpm_level;
0371     enum amd_dpm_forced_level saved_dpm_level;
0372     enum amd_dpm_forced_level requested_dpm_level;
0373     struct smu_power_state *dpm_request_power_state;
0374     struct smu_power_state *dpm_current_power_state;
0375     struct mclock_latency_table *mclk_latency_table;
0376 };
0377 
0378 struct smu_power_gate {
0379     bool uvd_gated;
0380     bool vce_gated;
0381     atomic_t vcn_gated;
0382     atomic_t jpeg_gated;
0383 };
0384 
0385 struct smu_power_context {
0386     void *power_context;
0387     uint32_t power_context_size;
0388     struct smu_power_gate power_gate;
0389 };
0390 
0391 #define SMU_FEATURE_MAX (64)
0392 struct smu_feature
0393 {
0394     uint32_t feature_num;
0395     DECLARE_BITMAP(supported, SMU_FEATURE_MAX);
0396     DECLARE_BITMAP(allowed, SMU_FEATURE_MAX);
0397 };
0398 
0399 struct smu_clocks {
0400     uint32_t engine_clock;
0401     uint32_t memory_clock;
0402     uint32_t bus_bandwidth;
0403     uint32_t engine_clock_in_sr;
0404     uint32_t dcef_clock;
0405     uint32_t dcef_clock_in_sr;
0406 };
0407 
0408 #define MAX_REGULAR_DPM_NUM 16
0409 struct mclk_latency_entries {
0410     uint32_t  frequency;
0411     uint32_t  latency;
0412 };
0413 struct mclock_latency_table {
0414     uint32_t  count;
0415     struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];
0416 };
0417 
0418 enum smu_reset_mode
0419 {
0420     SMU_RESET_MODE_0,
0421     SMU_RESET_MODE_1,
0422     SMU_RESET_MODE_2,
0423 };
0424 
0425 enum smu_baco_state
0426 {
0427     SMU_BACO_STATE_ENTER = 0,
0428     SMU_BACO_STATE_EXIT,
0429 };
0430 
0431 struct smu_baco_context
0432 {
0433     uint32_t state;
0434     bool platform_support;
0435     bool maco_support;
0436 };
0437 
0438 struct smu_freq_info {
0439     uint32_t min;
0440     uint32_t max;
0441     uint32_t freq_level;
0442 };
0443 
0444 struct pstates_clk_freq {
0445     uint32_t            min;
0446     uint32_t            standard;
0447     uint32_t            peak;
0448     struct smu_freq_info        custom;
0449     struct smu_freq_info        curr;
0450 };
0451 
0452 struct smu_umd_pstate_table {
0453     struct pstates_clk_freq     gfxclk_pstate;
0454     struct pstates_clk_freq     socclk_pstate;
0455     struct pstates_clk_freq     uclk_pstate;
0456     struct pstates_clk_freq     vclk_pstate;
0457     struct pstates_clk_freq     dclk_pstate;
0458     struct pstates_clk_freq     fclk_pstate;
0459 };
0460 
0461 struct cmn2asic_msg_mapping {
0462     int valid_mapping;
0463     int map_to;
0464     int valid_in_vf;
0465 };
0466 
0467 struct cmn2asic_mapping {
0468     int valid_mapping;
0469     int map_to;
0470 };
0471 
0472 struct stb_context {
0473     uint32_t stb_buf_size;
0474     bool enabled;
0475     spinlock_t lock;
0476 };
0477 
0478 #define WORKLOAD_POLICY_MAX 7
0479 
0480 struct smu_context
0481 {
0482     struct amdgpu_device            *adev;
0483     struct amdgpu_irq_src       irq_source;
0484 
0485     const struct pptable_funcs  *ppt_funcs;
0486     const struct cmn2asic_msg_mapping   *message_map;
0487     const struct cmn2asic_mapping   *clock_map;
0488     const struct cmn2asic_mapping   *feature_map;
0489     const struct cmn2asic_mapping   *table_map;
0490     const struct cmn2asic_mapping   *pwr_src_map;
0491     const struct cmn2asic_mapping   *workload_map;
0492     struct mutex            message_lock;
0493     uint64_t pool_size;
0494 
0495     struct smu_table_context    smu_table;
0496     struct smu_dpm_context      smu_dpm;
0497     struct smu_power_context    smu_power;
0498     struct smu_feature      smu_feature;
0499     struct amd_pp_display_configuration  *display_config;
0500     struct smu_baco_context     smu_baco;
0501     struct smu_temperature_range    thermal_range;
0502     void *od_settings;
0503 
0504     struct smu_umd_pstate_table pstate_table;
0505     uint32_t pstate_sclk;
0506     uint32_t pstate_mclk;
0507 
0508     bool od_enabled;
0509     uint32_t current_power_limit;
0510     uint32_t default_power_limit;
0511     uint32_t max_power_limit;
0512 
0513     /* soft pptable */
0514     uint32_t ppt_offset_bytes;
0515     uint32_t ppt_size_bytes;
0516     uint8_t  *ppt_start_addr;
0517 
0518     bool support_power_containment;
0519     bool disable_watermark;
0520 
0521 #define WATERMARKS_EXIST    (1 << 0)
0522 #define WATERMARKS_LOADED   (1 << 1)
0523     uint32_t watermarks_bitmap;
0524     uint32_t hard_min_uclk_req_from_dal;
0525     bool disable_uclk_switch;
0526 
0527     uint32_t workload_mask;
0528     uint32_t workload_prority[WORKLOAD_POLICY_MAX];
0529     uint32_t workload_setting[WORKLOAD_POLICY_MAX];
0530     uint32_t power_profile_mode;
0531     uint32_t default_power_profile_mode;
0532     bool pm_enabled;
0533     bool is_apu;
0534 
0535     uint32_t smc_driver_if_version;
0536     uint32_t smc_fw_if_version;
0537     uint32_t smc_fw_version;
0538 
0539     bool uploading_custom_pp_table;
0540     bool dc_controlled_by_gpio;
0541 
0542     struct work_struct throttling_logging_work;
0543     atomic64_t throttle_int_counter;
0544     struct work_struct interrupt_work;
0545 
0546     unsigned fan_max_rpm;
0547     unsigned manual_fan_speed_pwm;
0548 
0549     uint32_t gfx_default_hard_min_freq;
0550     uint32_t gfx_default_soft_max_freq;
0551     uint32_t gfx_actual_hard_min_freq;
0552     uint32_t gfx_actual_soft_max_freq;
0553 
0554     /* APU only */
0555     uint32_t cpu_default_soft_min_freq;
0556     uint32_t cpu_default_soft_max_freq;
0557     uint32_t cpu_actual_soft_min_freq;
0558     uint32_t cpu_actual_soft_max_freq;
0559     uint32_t cpu_core_id_select;
0560     uint16_t cpu_core_num;
0561 
0562     struct smu_user_dpm_profile user_dpm_profile;
0563 
0564     struct stb_context stb_context;
0565 
0566     struct firmware pptable_firmware;
0567 
0568     u32 param_reg;
0569     u32 msg_reg;
0570     u32 resp_reg;
0571 };
0572 
0573 struct i2c_adapter;
0574 
0575 /**
0576  * struct pptable_funcs - Callbacks used to interact with the SMU.
0577  */
0578 struct pptable_funcs {
0579     /**
0580      * @run_btc: Calibrate voltage/frequency curve to fit the system's
0581      *           power delivery and voltage margins. Required for adaptive
0582      *           voltage frequency scaling (AVFS).
0583      */
0584     int (*run_btc)(struct smu_context *smu);
0585 
0586     /**
0587      * @get_allowed_feature_mask: Get allowed feature mask.
0588      * &feature_mask: Array to store feature mask.
0589      * &num: Elements in &feature_mask.
0590      */
0591     int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
0592 
0593     /**
0594      * @get_current_power_state: Get the current power state.
0595      *
0596      * Return: Current power state on success, negative errno on failure.
0597      */
0598     enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
0599 
0600     /**
0601      * @set_default_dpm_table: Retrieve the default overdrive settings from
0602      *                         the SMU.
0603      */
0604     int (*set_default_dpm_table)(struct smu_context *smu);
0605 
0606     int (*set_power_state)(struct smu_context *smu);
0607 
0608     /**
0609      * @populate_umd_state_clk: Populate the UMD power state table with
0610      *                          defaults.
0611      */
0612     int (*populate_umd_state_clk)(struct smu_context *smu);
0613 
0614     /**
0615      * @print_clk_levels: Print DPM clock levels for a clock domain
0616      *                    to buffer. Star current level.
0617      *
0618      * Used for sysfs interfaces.
0619      * Return: Number of characters written to the buffer
0620      */
0621     int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
0622 
0623     /**
0624      * @emit_clk_levels: Print DPM clock levels for a clock domain
0625      *                    to buffer using sysfs_emit_at. Star current level.
0626      *
0627      * Used for sysfs interfaces.
0628      * &buf: sysfs buffer
0629      * &offset: offset within buffer to start printing, which is updated by the
0630      * function.
0631      *
0632      * Return: 0 on Success or Negative to indicate an error occurred.
0633      */
0634     int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset);
0635 
0636     /**
0637      * @force_clk_levels: Set a range of allowed DPM levels for a clock
0638      *                    domain.
0639      * &clk_type: Clock domain.
0640      * &mask: Range of allowed DPM levels.
0641      */
0642     int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
0643 
0644     /**
0645      * @od_edit_dpm_table: Edit the custom overdrive DPM table.
0646      * &type: Type of edit.
0647      * &input: Edit parameters.
0648      * &size: Size of &input.
0649      */
0650     int (*od_edit_dpm_table)(struct smu_context *smu,
0651                  enum PP_OD_DPM_TABLE_COMMAND type,
0652                  long *input, uint32_t size);
0653 
0654     /**
0655      * @restore_user_od_settings: Restore the user customized
0656      *                            OD settings on S3/S4/Runpm resume.
0657      */
0658     int (*restore_user_od_settings)(struct smu_context *smu);
0659 
0660     /**
0661      * @get_clock_by_type_with_latency: Get the speed and latency of a clock
0662      *                                  domain.
0663      */
0664     int (*get_clock_by_type_with_latency)(struct smu_context *smu,
0665                           enum smu_clk_type clk_type,
0666                           struct
0667                           pp_clock_levels_with_latency
0668                           *clocks);
0669     /**
0670      * @get_clock_by_type_with_voltage: Get the speed and voltage of a clock
0671      *                                  domain.
0672      */
0673     int (*get_clock_by_type_with_voltage)(struct smu_context *smu,
0674                           enum amd_pp_clock_type type,
0675                           struct
0676                           pp_clock_levels_with_voltage
0677                           *clocks);
0678 
0679     /**
0680      * @get_power_profile_mode: Print all power profile modes to
0681      *                          buffer. Star current mode.
0682      */
0683     int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
0684 
0685     /**
0686      * @set_power_profile_mode: Set a power profile mode. Also used to
0687      *                          create/set custom power profile modes.
0688      * &input: Power profile mode parameters.
0689      * &size: Size of &input.
0690      */
0691     int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
0692 
0693     /**
0694      * @dpm_set_vcn_enable: Enable/disable VCN engine dynamic power
0695      *                      management.
0696      */
0697     int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
0698 
0699     /**
0700      * @dpm_set_jpeg_enable: Enable/disable JPEG engine dynamic power
0701      *                       management.
0702      */
0703     int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
0704 
0705     /**
0706      * @set_gfx_power_up_by_imu: Enable GFX engine with IMU
0707      */
0708     int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
0709 
0710     /**
0711      * @read_sensor: Read data from a sensor.
0712      * &sensor: Sensor to read data from.
0713      * &data: Sensor reading.
0714      * &size: Size of &data.
0715      */
0716     int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
0717                void *data, uint32_t *size);
0718 
0719     /**
0720      * @pre_display_config_changed: Prepare GPU for a display configuration
0721      *                              change.
0722      *
0723      * Disable display tracking and pin memory clock speed to maximum. Used
0724      * in display component synchronization.
0725      */
0726     int (*pre_display_config_changed)(struct smu_context *smu);
0727 
0728     /**
0729      * @display_config_changed: Notify the SMU of the current display
0730      *                          configuration.
0731      *
0732      * Allows SMU to properly track blanking periods for memory clock
0733      * adjustment. Used in display component synchronization.
0734      */
0735     int (*display_config_changed)(struct smu_context *smu);
0736 
0737     int (*apply_clocks_adjust_rules)(struct smu_context *smu);
0738 
0739     /**
0740      * @notify_smc_display_config: Applies display requirements to the
0741      *                             current power state.
0742      *
0743      * Optimize deep sleep DCEFclk and mclk for the current display
0744      * configuration. Used in display component synchronization.
0745      */
0746     int (*notify_smc_display_config)(struct smu_context *smu);
0747 
0748     /**
0749      * @is_dpm_running: Check if DPM is running.
0750      *
0751      * Return: True if DPM is running, false otherwise.
0752      */
0753     bool (*is_dpm_running)(struct smu_context *smu);
0754 
0755     /**
0756      * @get_fan_speed_pwm: Get the current fan speed in PWM.
0757      */
0758     int (*get_fan_speed_pwm)(struct smu_context *smu, uint32_t *speed);
0759 
0760     /**
0761      * @get_fan_speed_rpm: Get the current fan speed in rpm.
0762      */
0763     int (*get_fan_speed_rpm)(struct smu_context *smu, uint32_t *speed);
0764 
0765     /**
0766      * @set_watermarks_table: Configure and upload the watermarks tables to
0767      *                        the SMU.
0768      */
0769     int (*set_watermarks_table)(struct smu_context *smu,
0770                     struct pp_smu_wm_range_sets *clock_ranges);
0771 
0772     /**
0773      * @get_thermal_temperature_range: Get safe thermal limits in Celcius.
0774      */
0775     int (*get_thermal_temperature_range)(struct smu_context *smu, struct smu_temperature_range *range);
0776 
0777     /**
0778      * @get_uclk_dpm_states: Get memory clock DPM levels in kHz.
0779      * &clocks_in_khz: Array of DPM levels.
0780      * &num_states: Elements in &clocks_in_khz.
0781      */
0782     int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states);
0783 
0784     /**
0785      * @set_default_od_settings: Set the overdrive tables to defaults.
0786      */
0787     int (*set_default_od_settings)(struct smu_context *smu);
0788 
0789     /**
0790      * @set_performance_level: Set a performance level.
0791      */
0792     int (*set_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
0793 
0794     /**
0795      * @display_disable_memory_clock_switch: Enable/disable dynamic memory
0796      *                                       clock switching.
0797      *
0798      * Disabling this feature forces memory clock speed to maximum.
0799      * Enabling sets the minimum memory clock capable of driving the
0800      * current display configuration.
0801      */
0802     int (*display_disable_memory_clock_switch)(struct smu_context *smu, bool disable_memory_clock_switch);
0803 
0804     /**
0805      * @dump_pptable: Print the power play table to the system log.
0806      */
0807     void (*dump_pptable)(struct smu_context *smu);
0808 
0809     /**
0810      * @get_power_limit: Get the device's power limits.
0811      */
0812     int (*get_power_limit)(struct smu_context *smu,
0813                    uint32_t *current_power_limit,
0814                    uint32_t *default_power_limit,
0815                    uint32_t *max_power_limit);
0816 
0817     /**
0818      * @get_ppt_limit: Get the device's ppt limits.
0819      */
0820     int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit,
0821             enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level);
0822 
0823     /**
0824      * @set_df_cstate: Set data fabric cstate.
0825      */
0826     int (*set_df_cstate)(struct smu_context *smu, enum pp_df_cstate state);
0827 
0828     /**
0829      * @allow_xgmi_power_down: Enable/disable external global memory
0830      *                         interconnect power down.
0831      */
0832     int (*allow_xgmi_power_down)(struct smu_context *smu, bool en);
0833 
0834     /**
0835      * @update_pcie_parameters: Update and upload the system's PCIe
0836      *                          capabilites to the SMU.
0837      * &pcie_gen_cap: Maximum allowed PCIe generation.
0838      * &pcie_width_cap: Maximum allowed PCIe width.
0839      */
0840     int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
0841 
0842     /**
0843      * @i2c_init: Initialize i2c.
0844      *
0845      * The i2c bus is used internally by the SMU voltage regulators and
0846      * other devices. The i2c's EEPROM also stores bad page tables on boards
0847      * with ECC.
0848      */
0849     int (*i2c_init)(struct smu_context *smu);
0850 
0851     /**
0852      * @i2c_fini: Tear down i2c.
0853      */
0854     void (*i2c_fini)(struct smu_context *smu);
0855 
0856     /**
0857      * @get_unique_id: Get the GPU's unique id. Used for asset tracking.
0858      */
0859     void (*get_unique_id)(struct smu_context *smu);
0860 
0861     /**
0862      * @get_dpm_clock_table: Get a copy of the DPM clock table.
0863      *
0864      * Used by display component in bandwidth and watermark calculations.
0865      */
0866     int (*get_dpm_clock_table)(struct smu_context *smu, struct dpm_clocks *clock_table);
0867 
0868     /**
0869      * @init_microcode: Request the SMU's firmware from the kernel.
0870      */
0871     int (*init_microcode)(struct smu_context *smu);
0872 
0873     /**
0874      * @load_microcode: Load firmware onto the SMU.
0875      */
0876     int (*load_microcode)(struct smu_context *smu);
0877 
0878     /**
0879      * @fini_microcode: Release the SMU's firmware.
0880      */
0881     void (*fini_microcode)(struct smu_context *smu);
0882 
0883     /**
0884      * @init_smc_tables: Initialize the SMU tables.
0885      */
0886     int (*init_smc_tables)(struct smu_context *smu);
0887 
0888     /**
0889      * @fini_smc_tables: Release the SMU tables.
0890      */
0891     int (*fini_smc_tables)(struct smu_context *smu);
0892 
0893     /**
0894      * @init_power: Initialize the power gate table context.
0895      */
0896     int (*init_power)(struct smu_context *smu);
0897 
0898     /**
0899      * @fini_power: Release the power gate table context.
0900      */
0901     int (*fini_power)(struct smu_context *smu);
0902 
0903     /**
0904      * @check_fw_status: Check the SMU's firmware status.
0905      *
0906      * Return: Zero if check passes, negative errno on failure.
0907      */
0908     int (*check_fw_status)(struct smu_context *smu);
0909 
0910     /**
0911      * @set_mp1_state: put SMU into a correct state for comming
0912      *                 resume from runpm or gpu reset.
0913      */
0914     int (*set_mp1_state)(struct smu_context *smu,
0915                  enum pp_mp1_state mp1_state);
0916 
0917     /**
0918      * @setup_pptable: Initialize the power play table and populate it with
0919      *                 default values.
0920      */
0921     int (*setup_pptable)(struct smu_context *smu);
0922 
0923     /**
0924      * @get_vbios_bootup_values: Get default boot values from the VBIOS.
0925      */
0926     int (*get_vbios_bootup_values)(struct smu_context *smu);
0927 
0928     /**
0929      * @check_fw_version: Print driver and SMU interface versions to the
0930      *                    system log.
0931      *
0932      * Interface mismatch is not a critical failure.
0933      */
0934     int (*check_fw_version)(struct smu_context *smu);
0935 
0936     /**
0937      * @powergate_sdma: Power up/down system direct memory access.
0938      */
0939     int (*powergate_sdma)(struct smu_context *smu, bool gate);
0940 
0941     /**
0942      * @set_gfx_cgpg: Enable/disable graphics engine course grain power
0943      *                gating.
0944      */
0945     int (*set_gfx_cgpg)(struct smu_context *smu, bool enable);
0946 
0947     /**
0948      * @write_pptable: Write the power play table to the SMU.
0949      */
0950     int (*write_pptable)(struct smu_context *smu);
0951 
0952     /**
0953      * @set_driver_table_location: Send the location of the driver table to
0954      *                             the SMU.
0955      */
0956     int (*set_driver_table_location)(struct smu_context *smu);
0957 
0958     /**
0959      * @set_tool_table_location: Send the location of the tool table to the
0960      *                           SMU.
0961      */
0962     int (*set_tool_table_location)(struct smu_context *smu);
0963 
0964     /**
0965      * @notify_memory_pool_location: Send the location of the memory pool to
0966      *                               the SMU.
0967      */
0968     int (*notify_memory_pool_location)(struct smu_context *smu);
0969 
0970     /**
0971      * @system_features_control: Enable/disable all SMU features.
0972      */
0973     int (*system_features_control)(struct smu_context *smu, bool en);
0974 
0975     /**
0976      * @send_smc_msg_with_param: Send a message with a parameter to the SMU.
0977      * &msg: Type of message.
0978      * &param: Message parameter.
0979      * &read_arg: SMU response (optional).
0980      */
0981     int (*send_smc_msg_with_param)(struct smu_context *smu,
0982                        enum smu_message_type msg, uint32_t param, uint32_t *read_arg);
0983 
0984     /**
0985      * @send_smc_msg: Send a message to the SMU.
0986      * &msg: Type of message.
0987      * &read_arg: SMU response (optional).
0988      */
0989     int (*send_smc_msg)(struct smu_context *smu,
0990                 enum smu_message_type msg,
0991                 uint32_t *read_arg);
0992 
0993     /**
0994      * @init_display_count: Notify the SMU of the number of display
0995      *                      components in current display configuration.
0996      */
0997     int (*init_display_count)(struct smu_context *smu, uint32_t count);
0998 
0999     /**
1000      * @set_allowed_mask: Notify the SMU of the features currently allowed
1001      *                    by the driver.
1002      */
1003     int (*set_allowed_mask)(struct smu_context *smu);
1004 
1005     /**
1006      * @get_enabled_mask: Get a mask of features that are currently enabled
1007      *                    on the SMU.
1008      * &feature_mask: Enabled feature mask.
1009      */
1010     int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
1011 
1012     /**
1013      * @feature_is_enabled: Test if a feature is enabled.
1014      *
1015      * Return: One if enabled, zero if disabled.
1016      */
1017     int (*feature_is_enabled)(struct smu_context *smu, enum smu_feature_mask mask);
1018 
1019     /**
1020      * @disable_all_features_with_exception: Disable all features with
1021      *                                       exception to those in &mask.
1022      */
1023     int (*disable_all_features_with_exception)(struct smu_context *smu,
1024                            enum smu_feature_mask mask);
1025 
1026     /**
1027      * @notify_display_change: Enable fast memory clock switching.
1028      *
1029      * Allows for fine grained memory clock switching but has more stringent
1030      * timing requirements.
1031      */
1032     int (*notify_display_change)(struct smu_context *smu);
1033 
1034     /**
1035      * @set_power_limit: Set power limit in watts.
1036      */
1037     int (*set_power_limit)(struct smu_context *smu,
1038                    enum smu_ppt_limit_type limit_type,
1039                    uint32_t limit);
1040 
1041     /**
1042      * @init_max_sustainable_clocks: Populate max sustainable clock speed
1043      *                               table with values from the SMU.
1044      */
1045     int (*init_max_sustainable_clocks)(struct smu_context *smu);
1046 
1047     /**
1048      * @enable_thermal_alert: Enable thermal alert interrupts.
1049      */
1050     int (*enable_thermal_alert)(struct smu_context *smu);
1051 
1052     /**
1053      * @disable_thermal_alert: Disable thermal alert interrupts.
1054      */
1055     int (*disable_thermal_alert)(struct smu_context *smu);
1056 
1057     /**
1058      * @set_min_dcef_deep_sleep: Set a minimum display fabric deep sleep
1059      *                           clock speed in MHz.
1060      */
1061     int (*set_min_dcef_deep_sleep)(struct smu_context *smu, uint32_t clk);
1062 
1063     /**
1064      * @display_clock_voltage_request: Set a hard minimum frequency
1065      * for a clock domain.
1066      */
1067     int (*display_clock_voltage_request)(struct smu_context *smu, struct
1068                          pp_display_clock_request
1069                          *clock_req);
1070 
1071     /**
1072      * @get_fan_control_mode: Get the current fan control mode.
1073      */
1074     uint32_t (*get_fan_control_mode)(struct smu_context *smu);
1075 
1076     /**
1077      * @set_fan_control_mode: Set the fan control mode.
1078      */
1079     int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode);
1080 
1081     /**
1082      * @set_fan_speed_pwm: Set a static fan speed in PWM.
1083      */
1084     int (*set_fan_speed_pwm)(struct smu_context *smu, uint32_t speed);
1085 
1086     /**
1087      * @set_fan_speed_rpm: Set a static fan speed in rpm.
1088      */
1089     int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
1090 
1091     /**
1092      * @set_xgmi_pstate: Set inter-chip global memory interconnect pstate.
1093      * &pstate: Pstate to set. D0 if Nonzero, D3 otherwise.
1094      */
1095     int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
1096 
1097     /**
1098      * @gfx_off_control: Enable/disable graphics engine poweroff.
1099      */
1100     int (*gfx_off_control)(struct smu_context *smu, bool enable);
1101 
1102 
1103     /**
1104      * @get_gfx_off_status: Get graphics engine poweroff status.
1105      *
1106      * Return:
1107      * 0 - GFXOFF(default).
1108      * 1 - Transition out of GFX State.
1109      * 2 - Not in GFXOFF.
1110      * 3 - Transition into GFXOFF.
1111      */
1112     uint32_t (*get_gfx_off_status)(struct smu_context *smu);
1113 
1114     /**
1115      * @register_irq_handler: Register interupt request handlers.
1116      */
1117     int (*register_irq_handler)(struct smu_context *smu);
1118 
1119     /**
1120      * @set_azalia_d3_pme: Wake the audio decode engine from d3 sleep.
1121      */
1122     int (*set_azalia_d3_pme)(struct smu_context *smu);
1123 
1124     /**
1125      * @get_max_sustainable_clocks_by_dc: Get a copy of the max sustainable
1126      *                                    clock speeds table.
1127      *
1128      * Provides a way for the display component (DC) to get the max
1129      * sustainable clocks from the SMU.
1130      */
1131     int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
1132 
1133     /**
1134      * @baco_is_support: Check if GPU supports BACO (Bus Active, Chip Off).
1135      */
1136     bool (*baco_is_support)(struct smu_context *smu);
1137 
1138     /**
1139      * @baco_get_state: Get the current BACO state.
1140      *
1141      * Return: Current BACO state.
1142      */
1143     enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
1144 
1145     /**
1146      * @baco_set_state: Enter/exit BACO.
1147      */
1148     int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
1149 
1150     /**
1151      * @baco_enter: Enter BACO.
1152      */
1153     int (*baco_enter)(struct smu_context *smu);
1154 
1155     /**
1156      * @baco_exit: Exit Baco.
1157      */
1158     int (*baco_exit)(struct smu_context *smu);
1159 
1160     /**
1161      * @mode1_reset_is_support: Check if GPU supports mode1 reset.
1162      */
1163     bool (*mode1_reset_is_support)(struct smu_context *smu);
1164     /**
1165      * @mode2_reset_is_support: Check if GPU supports mode2 reset.
1166      */
1167     bool (*mode2_reset_is_support)(struct smu_context *smu);
1168 
1169     /**
1170      * @mode1_reset: Perform mode1 reset.
1171      *
1172      * Complete GPU reset.
1173      */
1174     int (*mode1_reset)(struct smu_context *smu);
1175 
1176     /**
1177      * @mode2_reset: Perform mode2 reset.
1178      *
1179      * Mode2 reset generally does not reset as many IPs as mode1 reset. The
1180      * IPs reset varies by asic.
1181      */
1182     int (*mode2_reset)(struct smu_context *smu);
1183 
1184     /**
1185      * @get_dpm_ultimate_freq: Get the hard frequency range of a clock
1186      *                         domain in MHz.
1187      */
1188     int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
1189 
1190     /**
1191      * @set_soft_freq_limited_range: Set the soft frequency range of a clock
1192      *                               domain in MHz.
1193      */
1194     int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
1195 
1196     /**
1197      * @set_power_source: Notify the SMU of the current power source.
1198      */
1199     int (*set_power_source)(struct smu_context *smu, enum smu_power_src_type power_src);
1200 
1201     /**
1202      * @log_thermal_throttling_event: Print a thermal throttling warning to
1203      *                                the system's log.
1204      */
1205     void (*log_thermal_throttling_event)(struct smu_context *smu);
1206 
1207     /**
1208      * @get_pp_feature_mask: Print a human readable table of enabled
1209      *                       features to buffer.
1210      */
1211     size_t (*get_pp_feature_mask)(struct smu_context *smu, char *buf);
1212 
1213     /**
1214      * @set_pp_feature_mask: Request the SMU enable/disable features to
1215      *                       match those enabled in &new_mask.
1216      */
1217     int (*set_pp_feature_mask)(struct smu_context *smu, uint64_t new_mask);
1218 
1219     /**
1220      * @get_gpu_metrics: Get a copy of the GPU metrics table from the SMU.
1221      *
1222      * Return: Size of &table
1223      */
1224     ssize_t (*get_gpu_metrics)(struct smu_context *smu, void **table);
1225 
1226     /**
1227      * @enable_mgpu_fan_boost: Enable multi-GPU fan boost.
1228      */
1229     int (*enable_mgpu_fan_boost)(struct smu_context *smu);
1230 
1231     /**
1232      * @gfx_ulv_control: Enable/disable ultra low voltage.
1233      */
1234     int (*gfx_ulv_control)(struct smu_context *smu, bool enablement);
1235 
1236     /**
1237      * @deep_sleep_control: Enable/disable deep sleep.
1238      */
1239     int (*deep_sleep_control)(struct smu_context *smu, bool enablement);
1240 
1241     /**
1242      * @get_fan_parameters: Get fan parameters.
1243      *
1244      * Get maximum fan speed from the power play table.
1245      */
1246     int (*get_fan_parameters)(struct smu_context *smu);
1247 
1248     /**
1249      * @post_init: Helper function for asic specific workarounds.
1250      */
1251     int (*post_init)(struct smu_context *smu);
1252 
1253     /**
1254      * @interrupt_work: Work task scheduled from SMU interrupt handler.
1255      */
1256     void (*interrupt_work)(struct smu_context *smu);
1257 
1258     /**
1259      * @gpo_control: Enable/disable graphics power optimization if supported.
1260      */
1261     int (*gpo_control)(struct smu_context *smu, bool enablement);
1262 
1263     /**
1264      * @gfx_state_change_set: Send the current graphics state to the SMU.
1265      */
1266     int (*gfx_state_change_set)(struct smu_context *smu, uint32_t state);
1267 
1268     /**
1269      * @set_fine_grain_gfx_freq_parameters: Set fine grain graphics clock
1270      *                                      parameters to defaults.
1271      */
1272     int (*set_fine_grain_gfx_freq_parameters)(struct smu_context *smu);
1273 
1274     /**
1275      * @smu_handle_passthrough_sbr:  Send message to SMU about special handling for SBR.
1276      */
1277     int (*smu_handle_passthrough_sbr)(struct smu_context *smu, bool enable);
1278 
1279     /**
1280      * @wait_for_event:  Wait for events from SMU.
1281      */
1282     int (*wait_for_event)(struct smu_context *smu,
1283                   enum smu_event_type event, uint64_t event_arg);
1284 
1285     /**
1286      * @sned_hbm_bad_pages_num:  message SMU to update bad page number
1287      *                                      of SMUBUS table.
1288      */
1289     int (*send_hbm_bad_pages_num)(struct smu_context *smu, uint32_t size);
1290 
1291     /**
1292      * @get_ecc_table:  message SMU to get ECC INFO table.
1293      */
1294     ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
1295     
1296     
1297     /**
1298      * @stb_collect_info: Collects Smart Trace Buffers data.
1299      */
1300     int (*stb_collect_info)(struct smu_context *smu, void *buf, uint32_t size);
1301 
1302     /**
1303      * @get_default_config_table_settings: Get the ASIC default DriverSmuConfig table settings.
1304      */
1305     int (*get_default_config_table_settings)(struct smu_context *smu, struct config_table_setting *table);
1306 
1307     /**
1308      * @set_config_table: Apply the input DriverSmuConfig table settings.
1309      */
1310     int (*set_config_table)(struct smu_context *smu, struct config_table_setting *table);
1311 
1312     /**
1313      * @sned_hbm_bad_channel_flag:  message SMU to update bad channel info
1314      *                                      of SMUBUS table.
1315      */
1316     int (*send_hbm_bad_channel_flag)(struct smu_context *smu, uint32_t size);
1317 
1318     /**
1319      * @init_pptable_microcode: Prepare the pptable microcode to upload via PSP
1320      */
1321     int (*init_pptable_microcode)(struct smu_context *smu);
1322 };
1323 
1324 typedef enum {
1325     METRICS_CURR_GFXCLK,
1326     METRICS_CURR_SOCCLK,
1327     METRICS_CURR_UCLK,
1328     METRICS_CURR_VCLK,
1329     METRICS_CURR_VCLK1,
1330     METRICS_CURR_DCLK,
1331     METRICS_CURR_DCLK1,
1332     METRICS_CURR_FCLK,
1333     METRICS_CURR_DCEFCLK,
1334     METRICS_AVERAGE_CPUCLK,
1335     METRICS_AVERAGE_GFXCLK,
1336     METRICS_AVERAGE_SOCCLK,
1337     METRICS_AVERAGE_FCLK,
1338     METRICS_AVERAGE_UCLK,
1339     METRICS_AVERAGE_VCLK,
1340     METRICS_AVERAGE_DCLK,
1341     METRICS_AVERAGE_VCLK1,
1342     METRICS_AVERAGE_DCLK1,
1343     METRICS_AVERAGE_GFXACTIVITY,
1344     METRICS_AVERAGE_MEMACTIVITY,
1345     METRICS_AVERAGE_VCNACTIVITY,
1346     METRICS_AVERAGE_SOCKETPOWER,
1347     METRICS_TEMPERATURE_EDGE,
1348     METRICS_TEMPERATURE_HOTSPOT,
1349     METRICS_TEMPERATURE_MEM,
1350     METRICS_TEMPERATURE_VRGFX,
1351     METRICS_TEMPERATURE_VRSOC,
1352     METRICS_TEMPERATURE_VRMEM,
1353     METRICS_THROTTLER_STATUS,
1354     METRICS_CURR_FANSPEED,
1355     METRICS_VOLTAGE_VDDSOC,
1356     METRICS_VOLTAGE_VDDGFX,
1357     METRICS_SS_APU_SHARE,
1358     METRICS_SS_DGPU_SHARE,
1359     METRICS_UNIQUE_ID_UPPER32,
1360     METRICS_UNIQUE_ID_LOWER32,
1361     METRICS_PCIE_RATE,
1362     METRICS_PCIE_WIDTH,
1363     METRICS_CURR_FANPWM,
1364 } MetricsMember_t;
1365 
1366 enum smu_cmn2asic_mapping_type {
1367     CMN2ASIC_MAPPING_MSG,
1368     CMN2ASIC_MAPPING_CLK,
1369     CMN2ASIC_MAPPING_FEATURE,
1370     CMN2ASIC_MAPPING_TABLE,
1371     CMN2ASIC_MAPPING_PWR,
1372     CMN2ASIC_MAPPING_WORKLOAD,
1373 };
1374 
1375 #define MSG_MAP(msg, index, valid_in_vf) \
1376     [SMU_MSG_##msg] = {1, (index), (valid_in_vf)}
1377 
1378 #define CLK_MAP(clk, index) \
1379     [SMU_##clk] = {1, (index)}
1380 
1381 #define FEA_MAP(fea) \
1382     [SMU_FEATURE_##fea##_BIT] = {1, FEATURE_##fea##_BIT}
1383 
1384 #define FEA_MAP_REVERSE(fea) \
1385     [SMU_FEATURE_DPM_##fea##_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1386 
1387 #define FEA_MAP_HALF_REVERSE(fea) \
1388     [SMU_FEATURE_DPM_##fea##CLK_BIT] = {1, FEATURE_##fea##_DPM_BIT}
1389 
1390 #define TAB_MAP(tab) \
1391     [SMU_TABLE_##tab] = {1, TABLE_##tab}
1392 
1393 #define TAB_MAP_VALID(tab) \
1394     [SMU_TABLE_##tab] = {1, TABLE_##tab}
1395 
1396 #define TAB_MAP_INVALID(tab) \
1397     [SMU_TABLE_##tab] = {0, TABLE_##tab}
1398 
1399 #define PWR_MAP(tab) \
1400     [SMU_POWER_SOURCE_##tab] = {1, POWER_SOURCE_##tab}
1401 
1402 #define WORKLOAD_MAP(profile, workload) \
1403     [profile] = {1, (workload)}
1404 
1405 /**
1406  * smu_memcpy_trailing - Copy the end of one structure into the middle of another
1407  *
1408  * @dst: Pointer to destination struct
1409  * @first_dst_member: The member name in @dst where the overwrite begins
1410  * @last_dst_member: The member name in @dst where the overwrite ends after
1411  * @src: Pointer to the source struct
1412  * @first_src_member: The member name in @src where the copy begins
1413  *
1414  */
1415 #define smu_memcpy_trailing(dst, first_dst_member, last_dst_member,    \
1416                 src, first_src_member)             \
1417 ({                                     \
1418     size_t __src_offset = offsetof(typeof(*(src)), first_src_member);  \
1419     size_t __src_size = sizeof(*(src)) - __src_offset;         \
1420     size_t __dst_offset = offsetof(typeof(*(dst)), first_dst_member);  \
1421     size_t __dst_size = offsetofend(typeof(*(dst)), last_dst_member) - \
1422                 __dst_offset;                  \
1423     BUILD_BUG_ON(__src_size != __dst_size);                \
1424     __builtin_memcpy((u8 *)(dst) + __dst_offset,               \
1425              (u8 *)(src) + __src_offset,               \
1426              __dst_size);                      \
1427 })
1428 
1429 #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
1430 int smu_get_power_limit(void *handle,
1431             uint32_t *limit,
1432             enum pp_power_limit_level pp_limit_level,
1433             enum pp_power_type pp_power_type);
1434 
1435 bool smu_mode1_reset_is_support(struct smu_context *smu);
1436 bool smu_mode2_reset_is_support(struct smu_context *smu);
1437 int smu_mode1_reset(struct smu_context *smu);
1438 
1439 extern const struct amd_ip_funcs smu_ip_funcs;
1440 
1441 bool is_support_sw_smu(struct amdgpu_device *adev);
1442 bool is_support_cclk_dpm(struct amdgpu_device *adev);
1443 int smu_write_watermarks_table(struct smu_context *smu);
1444 
1445 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1446                uint32_t *min, uint32_t *max);
1447 
1448 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1449                 uint32_t min, uint32_t max);
1450 
1451 int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
1452 
1453 int smu_set_ac_dc(struct smu_context *smu);
1454 
1455 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
1456 
1457 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value);
1458 
1459 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable);
1460 
1461 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
1462                uint64_t event_arg);
1463 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc);
1464 int smu_stb_collect_info(struct smu_context *smu, void *buff, uint32_t size);
1465 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev);
1466 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size);
1467 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size);
1468 #endif
1469 #endif
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