pm/swsmu/amdgpu_smu.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #define SWSMU_CODE_LAYER_L1
0024
0025 #include <linux/firmware.h>
0026 #include <linux/pci.h>
0027
0028 #include "amdgpu.h"
0029 #include "amdgpu_smu.h"
0030 #include "smu_internal.h"
0031 #include "atom.h"
0032 #include "arcturus_ppt.h"
0033 #include "navi10_ppt.h"
0034 #include "sienna_cichlid_ppt.h"
0035 #include "renoir_ppt.h"
0036 #include "vangogh_ppt.h"
0037 #include "aldebaran_ppt.h"
0038 #include "yellow_carp_ppt.h"
0039 #include "cyan_skillfish_ppt.h"
0040 #include "smu_v13_0_0_ppt.h"
0041 #include "smu_v13_0_4_ppt.h"
0042 #include "smu_v13_0_5_ppt.h"
0043 #include "smu_v13_0_7_ppt.h"
0044 #include "amd_pcie.h"
0045
0046 /*
0047  * DO NOT use these for err/warn/info/debug messages.
0048  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
0049  * They are more MGPU friendly.
0050  */
0051 #undef pr_err
0052 #undef pr_warn
0053 #undef pr_info
0054 #undef pr_debug
0055
0056 static const struct amd_pm_funcs swsmu_pm_funcs;
0057 static int smu_force_smuclk_levels(struct smu_context *smu,
0058                    enum smu_clk_type clk_type,
0059                    uint32_t mask);
0060 static int smu_handle_task(struct smu_context *smu,
0061                enum amd_dpm_forced_level level,
0062                enum amd_pp_task task_id);
0063 static int smu_reset(struct smu_context *smu);
0064 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
0065 static int smu_set_fan_control_mode(void *handle, u32 value);
0066 static int smu_set_power_limit(void *handle, uint32_t limit);
0067 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
0068 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
0069 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
0070
0071 static int smu_sys_get_pp_feature_mask(void *handle,
0072                        char *buf)
0073 {
0074     struct smu_context *smu = handle;
0075
0076     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
0077         return -EOPNOTSUPP;
0078
0079     return smu_get_pp_feature_mask(smu, buf);
0080 }
0081
0082 static int smu_sys_set_pp_feature_mask(void *handle,
0083                        uint64_t new_mask)
0084 {
0085     struct smu_context *smu = handle;
0086
0087     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
0088         return -EOPNOTSUPP;
0089
0090     return smu_set_pp_feature_mask(smu, new_mask);
0091 }
0092
0093 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
0094 {
0095     if (!smu->ppt_funcs->get_gfx_off_status)
0096         return -EINVAL;
0097
0098     *value = smu_get_gfx_off_status(smu);
0099
0100     return 0;
0101 }
0102
0103 int smu_set_soft_freq_range(struct smu_context *smu,
0104                 enum smu_clk_type clk_type,
0105                 uint32_t min,
0106                 uint32_t max)
0107 {
0108     int ret = 0;
0109
0110     if (smu->ppt_funcs->set_soft_freq_limited_range)
0111         ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
0112                                   clk_type,
0113                                   min,
0114                                   max);
0115
0116     return ret;
0117 }
0118
0119 int smu_get_dpm_freq_range(struct smu_context *smu,
0120                enum smu_clk_type clk_type,
0121                uint32_t *min,
0122                uint32_t *max)
0123 {
0124     int ret = -ENOTSUPP;
0125
0126     if (!min && !max)
0127         return -EINVAL;
0128
0129     if (smu->ppt_funcs->get_dpm_ultimate_freq)
0130         ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
0131                                 clk_type,
0132                                 min,
0133                                 max);
0134
0135     return ret;
0136 }
0137
0138 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
0139 {
0140     if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
0141         return -EOPNOTSUPP;
0142
0143     return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
0144 }
0145
0146 static u32 smu_get_mclk(void *handle, bool low)
0147 {
0148     struct smu_context *smu = handle;
0149     uint32_t clk_freq;
0150     int ret = 0;
0151
0152     ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
0153                      low ? &clk_freq : NULL,
0154                      !low ? &clk_freq : NULL);
0155     if (ret)
0156         return 0;
0157     return clk_freq * 100;
0158 }
0159
0160 static u32 smu_get_sclk(void *handle, bool low)
0161 {
0162     struct smu_context *smu = handle;
0163     uint32_t clk_freq;
0164     int ret = 0;
0165
0166     ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
0167                      low ? &clk_freq : NULL,
0168                      !low ? &clk_freq : NULL);
0169     if (ret)
0170         return 0;
0171     return clk_freq * 100;
0172 }
0173
0174 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
0175                   bool enable)
0176 {
0177     struct smu_power_context *smu_power = &smu->smu_power;
0178     struct smu_power_gate *power_gate = &smu_power->power_gate;
0179     int ret = 0;
0180
0181     if (!smu->ppt_funcs->dpm_set_vcn_enable)
0182         return 0;
0183
0184     if (atomic_read(&power_gate->vcn_gated) ^ enable)
0185         return 0;
0186
0187     ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
0188     if (!ret)
0189         atomic_set(&power_gate->vcn_gated, !enable);
0190
0191     return ret;
0192 }
0193
0194 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
0195                    bool enable)
0196 {
0197     struct smu_power_context *smu_power = &smu->smu_power;
0198     struct smu_power_gate *power_gate = &smu_power->power_gate;
0199     int ret = 0;
0200
0201     if (!smu->ppt_funcs->dpm_set_jpeg_enable)
0202         return 0;
0203
0204     if (atomic_read(&power_gate->jpeg_gated) ^ enable)
0205         return 0;
0206
0207     ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
0208     if (!ret)
0209         atomic_set(&power_gate->jpeg_gated, !enable);
0210
0211     return ret;
0212 }
0213
0214 /**
0215  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
0216  *
0217  * @handle:        smu_context pointer
0218  * @block_type: the IP block to power gate/ungate
0219  * @gate:       to power gate if true, ungate otherwise
0220  *
0221  * This API uses no smu->mutex lock protection due to:
0222  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
0223  *    This is guarded to be race condition free by the caller.
0224  * 2. Or get called on user setting request of power_dpm_force_performance_level.
0225  *    Under this case, the smu->mutex lock protection is already enforced on
0226  *    the parent API smu_force_performance_level of the call path.
0227  */
0228 static int smu_dpm_set_power_gate(void *handle,
0229                   uint32_t block_type,
0230                   bool gate)
0231 {
0232     struct smu_context *smu = handle;
0233     int ret = 0;
0234
0235     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
0236         dev_WARN(smu->adev->dev,
0237              "SMU uninitialized but power %s requested for %u!\n",
0238              gate ? "gate" : "ungate", block_type);
0239         return -EOPNOTSUPP;
0240     }
0241
0242     switch (block_type) {
0243     /*
0244      * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
0245      * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
0246      */
0247     case AMD_IP_BLOCK_TYPE_UVD:
0248     case AMD_IP_BLOCK_TYPE_VCN:
0249         ret = smu_dpm_set_vcn_enable(smu, !gate);
0250         if (ret)
0251             dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
0252                 gate ? "gate" : "ungate");
0253         break;
0254     case AMD_IP_BLOCK_TYPE_GFX:
0255         ret = smu_gfx_off_control(smu, gate);
0256         if (ret)
0257             dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
0258                 gate ? "enable" : "disable");
0259         break;
0260     case AMD_IP_BLOCK_TYPE_SDMA:
0261         ret = smu_powergate_sdma(smu, gate);
0262         if (ret)
0263             dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
0264                 gate ? "gate" : "ungate");
0265         break;
0266     case AMD_IP_BLOCK_TYPE_JPEG:
0267         ret = smu_dpm_set_jpeg_enable(smu, !gate);
0268         if (ret)
0269             dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
0270                 gate ? "gate" : "ungate");
0271         break;
0272     default:
0273         dev_err(smu->adev->dev, "Unsupported block type!\n");
0274         return -EINVAL;
0275     }
0276
0277     return ret;
0278 }
0279
0280 /**
0281  * smu_set_user_clk_dependencies - set user profile clock dependencies
0282  *
0283  * @smu:    smu_context pointer
0284  * @clk:    enum smu_clk_type type
0285  *
0286  * Enable/Disable the clock dependency for the @clk type.
0287  */
0288 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
0289 {
0290     if (smu->adev->in_suspend)
0291         return;
0292
0293     if (clk == SMU_MCLK) {
0294         smu->user_dpm_profile.clk_dependency = 0;
0295         smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
0296     } else if (clk == SMU_FCLK) {
0297         /* MCLK takes precedence over FCLK */
0298         if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
0299             return;
0300
0301         smu->user_dpm_profile.clk_dependency = 0;
0302         smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
0303     } else if (clk == SMU_SOCCLK) {
0304         /* MCLK takes precedence over SOCCLK */
0305         if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
0306             return;
0307
0308         smu->user_dpm_profile.clk_dependency = 0;
0309         smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
0310     } else
0311         /* Add clk dependencies here, if any */
0312         return;
0313 }
0314
0315 /**
0316  * smu_restore_dpm_user_profile - reinstate user dpm profile
0317  *
0318  * @smu:    smu_context pointer
0319  *
0320  * Restore the saved user power configurations include power limit,
0321  * clock frequencies, fan control mode and fan speed.
0322  */
0323 static void smu_restore_dpm_user_profile(struct smu_context *smu)
0324 {
0325     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
0326     int ret = 0;
0327
0328     if (!smu->adev->in_suspend)
0329         return;
0330
0331     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
0332         return;
0333
0334     /* Enable restore flag */
0335     smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
0336
0337     /* set the user dpm power limit */
0338     if (smu->user_dpm_profile.power_limit) {
0339         ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
0340         if (ret)
0341             dev_err(smu->adev->dev, "Failed to set power limit value\n");
0342     }
0343
0344     /* set the user dpm clock configurations */
0345     if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
0346         enum smu_clk_type clk_type;
0347
0348         for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
0349             /*
0350              * Iterate over smu clk type and force the saved user clk
0351              * configs, skip if clock dependency is enabled
0352              */
0353             if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
0354                     smu->user_dpm_profile.clk_mask[clk_type]) {
0355                 ret = smu_force_smuclk_levels(smu, clk_type,
0356                         smu->user_dpm_profile.clk_mask[clk_type]);
0357                 if (ret)
0358                     dev_err(smu->adev->dev,
0359                         "Failed to set clock type = %d\n", clk_type);
0360             }
0361         }
0362     }
0363
0364     /* set the user dpm fan configurations */
0365     if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
0366         smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
0367         ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
0368         if (ret != -EOPNOTSUPP) {
0369             smu->user_dpm_profile.fan_speed_pwm = 0;
0370             smu->user_dpm_profile.fan_speed_rpm = 0;
0371             smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
0372             dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
0373         }
0374
0375         if (smu->user_dpm_profile.fan_speed_pwm) {
0376             ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
0377             if (ret != -EOPNOTSUPP)
0378                 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
0379         }
0380
0381         if (smu->user_dpm_profile.fan_speed_rpm) {
0382             ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
0383             if (ret != -EOPNOTSUPP)
0384                 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
0385         }
0386     }
0387
0388     /* Restore user customized OD settings */
0389     if (smu->user_dpm_profile.user_od) {
0390         if (smu->ppt_funcs->restore_user_od_settings) {
0391             ret = smu->ppt_funcs->restore_user_od_settings(smu);
0392             if (ret)
0393                 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
0394         }
0395     }
0396
0397     /* Disable restore flag */
0398     smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
0399 }
0400
0401 static int smu_get_power_num_states(void *handle,
0402                     struct pp_states_info *state_info)
0403 {
0404     if (!state_info)
0405         return -EINVAL;
0406
0407     /* not support power state */
0408     memset(state_info, 0, sizeof(struct pp_states_info));
0409     state_info->nums = 1;
0410     state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
0411
0412     return 0;
0413 }
0414
0415 bool is_support_sw_smu(struct amdgpu_device *adev)
0416 {
0417     /* vega20 is 11.0.2, but it's supported via the powerplay code */
0418     if (adev->asic_type == CHIP_VEGA20)
0419         return false;
0420
0421     if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
0422         return true;
0423
0424     return false;
0425 }
0426
0427 bool is_support_cclk_dpm(struct amdgpu_device *adev)
0428 {
0429     struct smu_context *smu = adev->powerplay.pp_handle;
0430
0431     if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
0432         return false;
0433
0434     return true;
0435 }
0436
0437
0438 static int smu_sys_get_pp_table(void *handle,
0439                 char **table)
0440 {
0441     struct smu_context *smu = handle;
0442     struct smu_table_context *smu_table = &smu->smu_table;
0443
0444     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
0445         return -EOPNOTSUPP;
0446
0447     if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
0448         return -EINVAL;
0449
0450     if (smu_table->hardcode_pptable)
0451         *table = smu_table->hardcode_pptable;
0452     else
0453         *table = smu_table->power_play_table;
0454
0455     return smu_table->power_play_table_size;
0456 }
0457
0458 static int smu_sys_set_pp_table(void *handle,
0459                 const char *buf,
0460                 size_t size)
0461 {
0462     struct smu_context *smu = handle;
0463     struct smu_table_context *smu_table = &smu->smu_table;
0464     ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
0465     int ret = 0;
0466
0467     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
0468         return -EOPNOTSUPP;
0469
0470     if (header->usStructureSize != size) {
0471         dev_err(smu->adev->dev, "pp table size not matched !\n");
0472         return -EIO;
0473     }
0474
0475     if (!smu_table->hardcode_pptable) {
0476         smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
0477         if (!smu_table->hardcode_pptable)
0478             return -ENOMEM;
0479     }
0480
0481     memcpy(smu_table->hardcode_pptable, buf, size);
0482     smu_table->power_play_table = smu_table->hardcode_pptable;
0483     smu_table->power_play_table_size = size;
0484
0485     /*
0486      * Special hw_fini action(for Navi1x, the DPMs disablement will be
0487      * skipped) may be needed for custom pptable uploading.
0488      */
0489     smu->uploading_custom_pp_table = true;
0490
0491     ret = smu_reset(smu);
0492     if (ret)
0493         dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
0494
0495     smu->uploading_custom_pp_table = false;
0496
0497     return ret;
0498 }
0499
0500 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
0501 {
0502     struct smu_feature *feature = &smu->smu_feature;
0503     uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
0504     int ret = 0;
0505
0506     /*
0507      * With SCPM enabled, the allowed featuremasks setting(via
0508      * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
0509      * That means there is no way to let PMFW knows the settings below.
0510      * Thus, we just assume all the features are allowed under
0511      * such scenario.
0512      */
0513     if (smu->adev->scpm_enabled) {
0514         bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
0515         return 0;
0516     }
0517
0518     bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
0519
0520     ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
0521                          SMU_FEATURE_MAX/32);
0522     if (ret)
0523         return ret;
0524
0525     bitmap_or(feature->allowed, feature->allowed,
0526               (unsigned long *)allowed_feature_mask,
0527               feature->feature_num);
0528
0529     return ret;
0530 }
0531
0532 static int smu_set_funcs(struct amdgpu_device *adev)
0533 {
0534     struct smu_context *smu = adev->powerplay.pp_handle;
0535
0536     if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
0537         smu->od_enabled = true;
0538
0539     switch (adev->ip_versions[MP1_HWIP][0]) {
0540     case IP_VERSION(11, 0, 0):
0541     case IP_VERSION(11, 0, 5):
0542     case IP_VERSION(11, 0, 9):
0543         navi10_set_ppt_funcs(smu);
0544         break;
0545     case IP_VERSION(11, 0, 7):
0546     case IP_VERSION(11, 0, 11):
0547     case IP_VERSION(11, 0, 12):
0548     case IP_VERSION(11, 0, 13):
0549         sienna_cichlid_set_ppt_funcs(smu);
0550         break;
0551     case IP_VERSION(12, 0, 0):
0552     case IP_VERSION(12, 0, 1):
0553         renoir_set_ppt_funcs(smu);
0554         break;
0555     case IP_VERSION(11, 5, 0):
0556         vangogh_set_ppt_funcs(smu);
0557         break;
0558     case IP_VERSION(13, 0, 1):
0559     case IP_VERSION(13, 0, 3):
0560     case IP_VERSION(13, 0, 8):
0561         yellow_carp_set_ppt_funcs(smu);
0562         break;
0563     case IP_VERSION(13, 0, 4):
0564         smu_v13_0_4_set_ppt_funcs(smu);
0565         break;
0566     case IP_VERSION(13, 0, 5):
0567         smu_v13_0_5_set_ppt_funcs(smu);
0568         break;
0569     case IP_VERSION(11, 0, 8):
0570         cyan_skillfish_set_ppt_funcs(smu);
0571         break;
0572     case IP_VERSION(11, 0, 2):
0573         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
0574         arcturus_set_ppt_funcs(smu);
0575         /* OD is not supported on Arcturus */
0576         smu->od_enabled =false;
0577         break;
0578     case IP_VERSION(13, 0, 2):
0579         aldebaran_set_ppt_funcs(smu);
0580         /* Enable pp_od_clk_voltage node */
0581         smu->od_enabled = true;
0582         break;
0583     case IP_VERSION(13, 0, 0):
0584         smu_v13_0_0_set_ppt_funcs(smu);
0585         break;
0586     case IP_VERSION(13, 0, 7):
0587         smu_v13_0_7_set_ppt_funcs(smu);
0588         break;
0589     default:
0590         return -EINVAL;
0591     }
0592
0593     return 0;
0594 }
0595
0596 static int smu_early_init(void *handle)
0597 {
0598     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0599     struct smu_context *smu;
0600
0601     smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
0602     if (!smu)
0603         return -ENOMEM;
0604
0605     smu->adev = adev;
0606     smu->pm_enabled = !!amdgpu_dpm;
0607     smu->is_apu = false;
0608     smu->smu_baco.state = SMU_BACO_STATE_EXIT;
0609     smu->smu_baco.platform_support = false;
0610     smu->user_dpm_profile.fan_mode = -1;
0611
0612     mutex_init(&smu->message_lock);
0613
0614     adev->powerplay.pp_handle = smu;
0615     adev->powerplay.pp_funcs = &swsmu_pm_funcs;
0616
0617     return smu_set_funcs(adev);
0618 }
0619
0620 static int smu_set_default_dpm_table(struct smu_context *smu)
0621 {
0622     struct smu_power_context *smu_power = &smu->smu_power;
0623     struct smu_power_gate *power_gate = &smu_power->power_gate;
0624     int vcn_gate, jpeg_gate;
0625     int ret = 0;
0626
0627     if (!smu->ppt_funcs->set_default_dpm_table)
0628         return 0;
0629
0630     vcn_gate = atomic_read(&power_gate->vcn_gated);
0631     jpeg_gate = atomic_read(&power_gate->jpeg_gated);
0632
0633     ret = smu_dpm_set_vcn_enable(smu, true);
0634     if (ret)
0635         return ret;
0636
0637     ret = smu_dpm_set_jpeg_enable(smu, true);
0638     if (ret)
0639         goto err_out;
0640
0641     ret = smu->ppt_funcs->set_default_dpm_table(smu);
0642     if (ret)
0643         dev_err(smu->adev->dev,
0644             "Failed to setup default dpm clock tables!\n");
0645
0646     smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
0647 err_out:
0648     smu_dpm_set_vcn_enable(smu, !vcn_gate);
0649     return ret;
0650 }
0651
0652 static int smu_apply_default_config_table_settings(struct smu_context *smu)
0653 {
0654     struct amdgpu_device *adev = smu->adev;
0655     int ret = 0;
0656
0657     ret = smu_get_default_config_table_settings(smu,
0658                             &adev->pm.config_table);
0659     if (ret)
0660         return ret;
0661
0662     return smu_set_config_table(smu, &adev->pm.config_table);
0663 }
0664
0665 static int smu_late_init(void *handle)
0666 {
0667     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0668     struct smu_context *smu = adev->powerplay.pp_handle;
0669     int ret = 0;
0670
0671     smu_set_fine_grain_gfx_freq_parameters(smu);
0672
0673     if (!smu->pm_enabled)
0674         return 0;
0675
0676     ret = smu_post_init(smu);
0677     if (ret) {
0678         dev_err(adev->dev, "Failed to post smu init!\n");
0679         return ret;
0680     }
0681
0682     if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
0683         (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
0684         return 0;
0685
0686     if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
0687         ret = smu_set_default_od_settings(smu);
0688         if (ret) {
0689             dev_err(adev->dev, "Failed to setup default OD settings!\n");
0690             return ret;
0691         }
0692     }
0693
0694     ret = smu_populate_umd_state_clk(smu);
0695     if (ret) {
0696         dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
0697         return ret;
0698     }
0699
0700     ret = smu_get_asic_power_limits(smu,
0701                     &smu->current_power_limit,
0702                     &smu->default_power_limit,
0703                     &smu->max_power_limit);
0704     if (ret) {
0705         dev_err(adev->dev, "Failed to get asic power limits!\n");
0706         return ret;
0707     }
0708
0709     if (!amdgpu_sriov_vf(adev))
0710         smu_get_unique_id(smu);
0711
0712     smu_get_fan_parameters(smu);
0713
0714     smu_handle_task(smu,
0715             smu->smu_dpm.dpm_level,
0716             AMD_PP_TASK_COMPLETE_INIT);
0717
0718     ret = smu_apply_default_config_table_settings(smu);
0719     if (ret && (ret != -EOPNOTSUPP)) {
0720         dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
0721         return ret;
0722     }
0723
0724     smu_restore_dpm_user_profile(smu);
0725
0726     return 0;
0727 }
0728
0729 static int smu_init_fb_allocations(struct smu_context *smu)
0730 {
0731     struct amdgpu_device *adev = smu->adev;
0732     struct smu_table_context *smu_table = &smu->smu_table;
0733     struct smu_table *tables = smu_table->tables;
0734     struct smu_table *driver_table = &(smu_table->driver_table);
0735     uint32_t max_table_size = 0;
0736     int ret, i;
0737
0738     /* VRAM allocation for tool table */
0739     if (tables[SMU_TABLE_PMSTATUSLOG].size) {
0740         ret = amdgpu_bo_create_kernel(adev,
0741                           tables[SMU_TABLE_PMSTATUSLOG].size,
0742                           tables[SMU_TABLE_PMSTATUSLOG].align,
0743                           tables[SMU_TABLE_PMSTATUSLOG].domain,
0744                           &tables[SMU_TABLE_PMSTATUSLOG].bo,
0745                           &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
0746                           &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
0747         if (ret) {
0748             dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
0749             return ret;
0750         }
0751     }
0752
0753     /* VRAM allocation for driver table */
0754     for (i = 0; i < SMU_TABLE_COUNT; i++) {
0755         if (tables[i].size == 0)
0756             continue;
0757
0758         if (i == SMU_TABLE_PMSTATUSLOG)
0759             continue;
0760
0761         if (max_table_size < tables[i].size)
0762             max_table_size = tables[i].size;
0763     }
0764
0765     driver_table->size = max_table_size;
0766     driver_table->align = PAGE_SIZE;
0767     driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
0768
0769     ret = amdgpu_bo_create_kernel(adev,
0770                       driver_table->size,
0771                       driver_table->align,
0772                       driver_table->domain,
0773                       &driver_table->bo,
0774                       &driver_table->mc_address,
0775                       &driver_table->cpu_addr);
0776     if (ret) {
0777         dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
0778         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
0779             amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
0780                           &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
0781                           &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
0782     }
0783
0784     return ret;
0785 }
0786
0787 static int smu_fini_fb_allocations(struct smu_context *smu)
0788 {
0789     struct smu_table_context *smu_table = &smu->smu_table;
0790     struct smu_table *tables = smu_table->tables;
0791     struct smu_table *driver_table = &(smu_table->driver_table);
0792
0793     if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
0794         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
0795                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
0796                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
0797
0798     amdgpu_bo_free_kernel(&driver_table->bo,
0799                   &driver_table->mc_address,
0800                   &driver_table->cpu_addr);
0801
0802     return 0;
0803 }
0804
0805 /**
0806  * smu_alloc_memory_pool - allocate memory pool in the system memory
0807  *
0808  * @smu: amdgpu_device pointer
0809  *
0810  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
0811  * and DramLogSetDramAddr can notify it changed.
0812  *
0813  * Returns 0 on success, error on failure.
0814  */
0815 static int smu_alloc_memory_pool(struct smu_context *smu)
0816 {
0817     struct amdgpu_device *adev = smu->adev;
0818     struct smu_table_context *smu_table = &smu->smu_table;
0819     struct smu_table *memory_pool = &smu_table->memory_pool;
0820     uint64_t pool_size = smu->pool_size;
0821     int ret = 0;
0822
0823     if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
0824         return ret;
0825
0826     memory_pool->size = pool_size;
0827     memory_pool->align = PAGE_SIZE;
0828     memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
0829
0830     switch (pool_size) {
0831     case SMU_MEMORY_POOL_SIZE_256_MB:
0832     case SMU_MEMORY_POOL_SIZE_512_MB:
0833     case SMU_MEMORY_POOL_SIZE_1_GB:
0834     case SMU_MEMORY_POOL_SIZE_2_GB:
0835         ret = amdgpu_bo_create_kernel(adev,
0836                           memory_pool->size,
0837                           memory_pool->align,
0838                           memory_pool->domain,
0839                           &memory_pool->bo,
0840                           &memory_pool->mc_address,
0841                           &memory_pool->cpu_addr);
0842         if (ret)
0843             dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
0844         break;
0845     default:
0846         break;
0847     }
0848
0849     return ret;
0850 }
0851
0852 static int smu_free_memory_pool(struct smu_context *smu)
0853 {
0854     struct smu_table_context *smu_table = &smu->smu_table;
0855     struct smu_table *memory_pool = &smu_table->memory_pool;
0856
0857     if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
0858         return 0;
0859
0860     amdgpu_bo_free_kernel(&memory_pool->bo,
0861                   &memory_pool->mc_address,
0862                   &memory_pool->cpu_addr);
0863
0864     memset(memory_pool, 0, sizeof(struct smu_table));
0865
0866     return 0;
0867 }
0868
0869 static int smu_alloc_dummy_read_table(struct smu_context *smu)
0870 {
0871     struct smu_table_context *smu_table = &smu->smu_table;
0872     struct smu_table *dummy_read_1_table =
0873             &smu_table->dummy_read_1_table;
0874     struct amdgpu_device *adev = smu->adev;
0875     int ret = 0;
0876
0877     dummy_read_1_table->size = 0x40000;
0878     dummy_read_1_table->align = PAGE_SIZE;
0879     dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
0880
0881     ret = amdgpu_bo_create_kernel(adev,
0882                       dummy_read_1_table->size,
0883                       dummy_read_1_table->align,
0884                       dummy_read_1_table->domain,
0885                       &dummy_read_1_table->bo,
0886                       &dummy_read_1_table->mc_address,
0887                       &dummy_read_1_table->cpu_addr);
0888     if (ret)
0889         dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
0890
0891     return ret;
0892 }
0893
0894 static void smu_free_dummy_read_table(struct smu_context *smu)
0895 {
0896     struct smu_table_context *smu_table = &smu->smu_table;
0897     struct smu_table *dummy_read_1_table =
0898             &smu_table->dummy_read_1_table;
0899
0900
0901     amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
0902                   &dummy_read_1_table->mc_address,
0903                   &dummy_read_1_table->cpu_addr);
0904
0905     memset(dummy_read_1_table, 0, sizeof(struct smu_table));
0906 }
0907
0908 static int smu_smc_table_sw_init(struct smu_context *smu)
0909 {
0910     int ret;
0911
0912     /**
0913      * Create smu_table structure, and init smc tables such as
0914      * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
0915      */
0916     ret = smu_init_smc_tables(smu);
0917     if (ret) {
0918         dev_err(smu->adev->dev, "Failed to init smc tables!\n");
0919         return ret;
0920     }
0921
0922     /**
0923      * Create smu_power_context structure, and allocate smu_dpm_context and
0924      * context size to fill the smu_power_context data.
0925      */
0926     ret = smu_init_power(smu);
0927     if (ret) {
0928         dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
0929         return ret;
0930     }
0931
0932     /*
0933      * allocate vram bos to store smc table contents.
0934      */
0935     ret = smu_init_fb_allocations(smu);
0936     if (ret)
0937         return ret;
0938
0939     ret = smu_alloc_memory_pool(smu);
0940     if (ret)
0941         return ret;
0942
0943     ret = smu_alloc_dummy_read_table(smu);
0944     if (ret)
0945         return ret;
0946
0947     ret = smu_i2c_init(smu);
0948     if (ret)
0949         return ret;
0950
0951     return 0;
0952 }
0953
0954 static int smu_smc_table_sw_fini(struct smu_context *smu)
0955 {
0956     int ret;
0957
0958     smu_i2c_fini(smu);
0959
0960     smu_free_dummy_read_table(smu);
0961
0962     ret = smu_free_memory_pool(smu);
0963     if (ret)
0964         return ret;
0965
0966     ret = smu_fini_fb_allocations(smu);
0967     if (ret)
0968         return ret;
0969
0970     ret = smu_fini_power(smu);
0971     if (ret) {
0972         dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
0973         return ret;
0974     }
0975
0976     ret = smu_fini_smc_tables(smu);
0977     if (ret) {
0978         dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
0979         return ret;
0980     }
0981
0982     return 0;
0983 }
0984
0985 static void smu_throttling_logging_work_fn(struct work_struct *work)
0986 {
0987     struct smu_context *smu = container_of(work, struct smu_context,
0988                            throttling_logging_work);
0989
0990     smu_log_thermal_throttling(smu);
0991 }
0992
0993 static void smu_interrupt_work_fn(struct work_struct *work)
0994 {
0995     struct smu_context *smu = container_of(work, struct smu_context,
0996                            interrupt_work);
0997
0998     if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
0999         smu->ppt_funcs->interrupt_work(smu);
1000 }
1001
1002 static int smu_sw_init(void *handle)
1003 {
1004     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005     struct smu_context *smu = adev->powerplay.pp_handle;
1006     int ret;
1007
1008     smu->pool_size = adev->pm.smu_prv_buffer_size;
1009     smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1010     bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1011     bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1012
1013     INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1014     INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1015     atomic64_set(&smu->throttle_int_counter, 0);
1016     smu->watermarks_bitmap = 0;
1017     smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1018     smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1019
1020     atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1021     atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1022
1023     smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1024     smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1025     smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1026     smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1027     smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1028     smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1029     smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1030     smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1031
1032     smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1033     smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1034     smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1035     smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1036     smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1037     smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1038     smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1039     smu->display_config = &adev->pm.pm_display_cfg;
1040
1041     smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1042     smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1043
1044     ret = smu_init_microcode(smu);
1045     if (ret) {
1046         dev_err(adev->dev, "Failed to load smu firmware!\n");
1047         return ret;
1048     }
1049
1050     ret = smu_smc_table_sw_init(smu);
1051     if (ret) {
1052         dev_err(adev->dev, "Failed to sw init smc table!\n");
1053         return ret;
1054     }
1055
1056     /* get boot_values from vbios to set revision, gfxclk, and etc. */
1057     ret = smu_get_vbios_bootup_values(smu);
1058     if (ret) {
1059         dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1060         return ret;
1061     }
1062
1063     ret = smu_init_pptable_microcode(smu);
1064     if (ret) {
1065         dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1066         return ret;
1067     }
1068
1069     ret = smu_register_irq_handler(smu);
1070     if (ret) {
1071         dev_err(adev->dev, "Failed to register smc irq handler!\n");
1072         return ret;
1073     }
1074
1075     /* If there is no way to query fan control mode, fan control is not supported */
1076     if (!smu->ppt_funcs->get_fan_control_mode)
1077         smu->adev->pm.no_fan = true;
1078
1079     return 0;
1080 }
1081
1082 static int smu_sw_fini(void *handle)
1083 {
1084     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085     struct smu_context *smu = adev->powerplay.pp_handle;
1086     int ret;
1087
1088     ret = smu_smc_table_sw_fini(smu);
1089     if (ret) {
1090         dev_err(adev->dev, "Failed to sw fini smc table!\n");
1091         return ret;
1092     }
1093
1094     smu_fini_microcode(smu);
1095
1096     return 0;
1097 }
1098
1099 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1100 {
1101     struct amdgpu_device *adev = smu->adev;
1102     struct smu_temperature_range *range =
1103                 &smu->thermal_range;
1104     int ret = 0;
1105
1106     if (!smu->ppt_funcs->get_thermal_temperature_range)
1107         return 0;
1108
1109     ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1110     if (ret)
1111         return ret;
1112
1113     adev->pm.dpm.thermal.min_temp = range->min;
1114     adev->pm.dpm.thermal.max_temp = range->max;
1115     adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1116     adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1117     adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1118     adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1119     adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1120     adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1121     adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1122
1123     return ret;
1124 }
1125
1126 static int smu_smc_hw_setup(struct smu_context *smu)
1127 {
1128     struct smu_feature *feature = &smu->smu_feature;
1129     struct amdgpu_device *adev = smu->adev;
1130     uint32_t pcie_gen = 0, pcie_width = 0;
1131     uint64_t features_supported;
1132     int ret = 0;
1133
1134     if (adev->in_suspend && smu_is_dpm_running(smu)) {
1135         dev_info(adev->dev, "dpm has been enabled\n");
1136         /* this is needed specifically */
1137         switch (adev->ip_versions[MP1_HWIP][0]) {
1138         case IP_VERSION(11, 0, 7):
1139         case IP_VERSION(11, 0, 11):
1140         case IP_VERSION(11, 5, 0):
1141         case IP_VERSION(11, 0, 12):
1142             ret = smu_system_features_control(smu, true);
1143             if (ret)
1144                 dev_err(adev->dev, "Failed system features control!\n");
1145             break;
1146         default:
1147             break;
1148         }
1149         return ret;
1150     }
1151
1152     ret = smu_init_display_count(smu, 0);
1153     if (ret) {
1154         dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1155         return ret;
1156     }
1157
1158     ret = smu_set_driver_table_location(smu);
1159     if (ret) {
1160         dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1161         return ret;
1162     }
1163
1164     /*
1165      * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1166      */
1167     ret = smu_set_tool_table_location(smu);
1168     if (ret) {
1169         dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1170         return ret;
1171     }
1172
1173     /*
1174      * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1175      * pool location.
1176      */
1177     ret = smu_notify_memory_pool_location(smu);
1178     if (ret) {
1179         dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1180         return ret;
1181     }
1182
1183     ret = smu_setup_pptable(smu);
1184     if (ret) {
1185         dev_err(adev->dev, "Failed to setup pptable!\n");
1186         return ret;
1187     }
1188
1189     /* smu_dump_pptable(smu); */
1190
1191     /*
1192      * With SCPM enabled, PSP is responsible for the PPTable transferring
1193      * (to SMU). Driver involvement is not needed and permitted.
1194      */
1195     if (!adev->scpm_enabled) {
1196         /*
1197          * Copy pptable bo in the vram to smc with SMU MSGs such as
1198          * SetDriverDramAddr and TransferTableDram2Smu.
1199          */
1200         ret = smu_write_pptable(smu);
1201         if (ret) {
1202             dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1203             return ret;
1204         }
1205     }
1206
1207     /* issue Run*Btc msg */
1208     ret = smu_run_btc(smu);
1209     if (ret)
1210         return ret;
1211
1212     /*
1213      * With SCPM enabled, these actions(and relevant messages) are
1214      * not needed and permitted.
1215      */
1216     if (!adev->scpm_enabled) {
1217         ret = smu_feature_set_allowed_mask(smu);
1218         if (ret) {
1219             dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1220             return ret;
1221         }
1222     }
1223
1224     ret = smu_system_features_control(smu, true);
1225     if (ret) {
1226         dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1227         return ret;
1228     }
1229
1230     ret = smu_feature_get_enabled_mask(smu, &features_supported);
1231     if (ret) {
1232         dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1233         return ret;
1234     }
1235     bitmap_copy(feature->supported,
1236             (unsigned long *)&features_supported,
1237             feature->feature_num);
1238
1239     if (!smu_is_dpm_running(smu))
1240         dev_info(adev->dev, "dpm has been disabled\n");
1241
1242     /*
1243      * Set initialized values (get from vbios) to dpm tables context such as
1244      * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1245      * type of clks.
1246      */
1247     ret = smu_set_default_dpm_table(smu);
1248     if (ret) {
1249         dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1250         return ret;
1251     }
1252
1253     if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1254         pcie_gen = 3;
1255     else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1256         pcie_gen = 2;
1257     else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1258         pcie_gen = 1;
1259     else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1260         pcie_gen = 0;
1261
1262     /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1263      * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1264      * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1265      */
1266     if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1267         pcie_width = 6;
1268     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1269         pcie_width = 5;
1270     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1271         pcie_width = 4;
1272     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1273         pcie_width = 3;
1274     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1275         pcie_width = 2;
1276     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1277         pcie_width = 1;
1278     ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1279     if (ret) {
1280         dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1281         return ret;
1282     }
1283
1284     ret = smu_get_thermal_temperature_range(smu);
1285     if (ret) {
1286         dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1287         return ret;
1288     }
1289
1290     ret = smu_enable_thermal_alert(smu);
1291     if (ret) {
1292         dev_err(adev->dev, "Failed to enable thermal alert!\n");
1293         return ret;
1294     }
1295
1296     ret = smu_notify_display_change(smu);
1297     if (ret) {
1298         dev_err(adev->dev, "Failed to notify display change!\n");
1299         return ret;
1300     }
1301
1302     /*
1303      * Set min deep sleep dce fclk with bootup value from vbios via
1304      * SetMinDeepSleepDcefclk MSG.
1305      */
1306     ret = smu_set_min_dcef_deep_sleep(smu,
1307                       smu->smu_table.boot_values.dcefclk / 100);
1308
1309     return ret;
1310 }
1311
1312 static int smu_start_smc_engine(struct smu_context *smu)
1313 {
1314     struct amdgpu_device *adev = smu->adev;
1315     int ret = 0;
1316
1317     if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1318         if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1319             if (smu->ppt_funcs->load_microcode) {
1320                 ret = smu->ppt_funcs->load_microcode(smu);
1321                 if (ret)
1322                     return ret;
1323             }
1324         }
1325     }
1326
1327     if (smu->ppt_funcs->check_fw_status) {
1328         ret = smu->ppt_funcs->check_fw_status(smu);
1329         if (ret) {
1330             dev_err(adev->dev, "SMC is not ready\n");
1331             return ret;
1332         }
1333     }
1334
1335     /*
1336      * Send msg GetDriverIfVersion to check if the return value is equal
1337      * with DRIVER_IF_VERSION of smc header.
1338      */
1339     ret = smu_check_fw_version(smu);
1340     if (ret)
1341         return ret;
1342
1343     return ret;
1344 }
1345
1346 static int smu_hw_init(void *handle)
1347 {
1348     int ret;
1349     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350     struct smu_context *smu = adev->powerplay.pp_handle;
1351
1352     if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1353         smu->pm_enabled = false;
1354         return 0;
1355     }
1356
1357     ret = smu_start_smc_engine(smu);
1358     if (ret) {
1359         dev_err(adev->dev, "SMC engine is not correctly up!\n");
1360         return ret;
1361     }
1362
1363     if (smu->is_apu) {
1364         if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
1365                 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1366             ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
1367             if (ret) {
1368                 dev_err(adev->dev, "Failed to Enable gfx imu!\n");
1369                 return ret;
1370             }
1371         }
1372
1373         smu_dpm_set_vcn_enable(smu, true);
1374         smu_dpm_set_jpeg_enable(smu, true);
1375         smu_set_gfx_cgpg(smu, true);
1376     }
1377
1378     if (!smu->pm_enabled)
1379         return 0;
1380
1381     ret = smu_get_driver_allowed_feature_mask(smu);
1382     if (ret)
1383         return ret;
1384
1385     ret = smu_smc_hw_setup(smu);
1386     if (ret) {
1387         dev_err(adev->dev, "Failed to setup smc hw!\n");
1388         return ret;
1389     }
1390
1391     /*
1392      * Move maximum sustainable clock retrieving here considering
1393      * 1. It is not needed on resume(from S3).
1394      * 2. DAL settings come between .hw_init and .late_init of SMU.
1395      *    And DAL needs to know the maximum sustainable clocks. Thus
1396      *    it cannot be put in .late_init().
1397      */
1398     ret = smu_init_max_sustainable_clocks(smu);
1399     if (ret) {
1400         dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1401         return ret;
1402     }
1403
1404     adev->pm.dpm_enabled = true;
1405
1406     dev_info(adev->dev, "SMU is initialized successfully!\n");
1407
1408     return 0;
1409 }
1410
1411 static int smu_disable_dpms(struct smu_context *smu)
1412 {
1413     struct amdgpu_device *adev = smu->adev;
1414     int ret = 0;
1415     bool use_baco = !smu->is_apu &&
1416         ((amdgpu_in_reset(adev) &&
1417           (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1418          ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1419
1420     /*
1421      * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1422      * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1423      */
1424     switch (adev->ip_versions[MP1_HWIP][0]) {
1425     case IP_VERSION(13, 0, 0):
1426     case IP_VERSION(13, 0, 7):
1427         return 0;
1428     default:
1429         break;
1430     }
1431
1432     /*
1433      * For custom pptable uploading, skip the DPM features
1434      * disable process on Navi1x ASICs.
1435      *   - As the gfx related features are under control of
1436      *     RLC on those ASICs. RLC reinitialization will be
1437      *     needed to reenable them. That will cost much more
1438      *     efforts.
1439      *
1440      *   - SMU firmware can handle the DPM reenablement
1441      *     properly.
1442      */
1443     if (smu->uploading_custom_pp_table) {
1444         switch (adev->ip_versions[MP1_HWIP][0]) {
1445         case IP_VERSION(11, 0, 0):
1446         case IP_VERSION(11, 0, 5):
1447         case IP_VERSION(11, 0, 9):
1448         case IP_VERSION(11, 0, 7):
1449         case IP_VERSION(11, 0, 11):
1450         case IP_VERSION(11, 5, 0):
1451         case IP_VERSION(11, 0, 12):
1452         case IP_VERSION(11, 0, 13):
1453             return 0;
1454         default:
1455             break;
1456         }
1457     }
1458
1459     /*
1460      * For Sienna_Cichlid, PMFW will handle the features disablement properly
1461      * on BACO in. Driver involvement is unnecessary.
1462      */
1463     if (use_baco) {
1464         switch (adev->ip_versions[MP1_HWIP][0]) {
1465         case IP_VERSION(11, 0, 7):
1466         case IP_VERSION(11, 0, 0):
1467         case IP_VERSION(11, 0, 5):
1468         case IP_VERSION(11, 0, 9):
1469         case IP_VERSION(13, 0, 7):
1470             return 0;
1471         default:
1472             break;
1473         }
1474     }
1475
1476     /*
1477      * For gpu reset, runpm and hibernation through BACO,
1478      * BACO feature has to be kept enabled.
1479      */
1480     if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1481         ret = smu_disable_all_features_with_exception(smu,
1482                                   SMU_FEATURE_BACO_BIT);
1483         if (ret)
1484             dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1485     } else {
1486         /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1487         if (!adev->scpm_enabled) {
1488             ret = smu_system_features_control(smu, false);
1489             if (ret)
1490                 dev_err(adev->dev, "Failed to disable smu features.\n");
1491         }
1492     }
1493
1494     if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1495         adev->gfx.rlc.funcs->stop)
1496         adev->gfx.rlc.funcs->stop(adev);
1497
1498     return ret;
1499 }
1500
1501 static int smu_smc_hw_cleanup(struct smu_context *smu)
1502 {
1503     struct amdgpu_device *adev = smu->adev;
1504     int ret = 0;
1505
1506     cancel_work_sync(&smu->throttling_logging_work);
1507     cancel_work_sync(&smu->interrupt_work);
1508
1509     ret = smu_disable_thermal_alert(smu);
1510     if (ret) {
1511         dev_err(adev->dev, "Fail to disable thermal alert!\n");
1512         return ret;
1513     }
1514
1515     ret = smu_disable_dpms(smu);
1516     if (ret) {
1517         dev_err(adev->dev, "Fail to disable dpm features!\n");
1518         return ret;
1519     }
1520
1521     return 0;
1522 }
1523
1524 static int smu_hw_fini(void *handle)
1525 {
1526     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1527     struct smu_context *smu = adev->powerplay.pp_handle;
1528
1529     if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1530         return 0;
1531
1532     smu_dpm_set_vcn_enable(smu, false);
1533     smu_dpm_set_jpeg_enable(smu, false);
1534
1535     adev->vcn.cur_state = AMD_PG_STATE_GATE;
1536     adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1537
1538     if (!smu->pm_enabled)
1539         return 0;
1540
1541     adev->pm.dpm_enabled = false;
1542
1543     return smu_smc_hw_cleanup(smu);
1544 }
1545
1546 static void smu_late_fini(void *handle)
1547 {
1548     struct amdgpu_device *adev = handle;
1549     struct smu_context *smu = adev->powerplay.pp_handle;
1550
1551     kfree(smu);
1552 }
1553
1554 static int smu_reset(struct smu_context *smu)
1555 {
1556     struct amdgpu_device *adev = smu->adev;
1557     int ret;
1558
1559     ret = smu_hw_fini(adev);
1560     if (ret)
1561         return ret;
1562
1563     ret = smu_hw_init(adev);
1564     if (ret)
1565         return ret;
1566
1567     ret = smu_late_init(adev);
1568     if (ret)
1569         return ret;
1570
1571     return 0;
1572 }
1573
1574 static int smu_suspend(void *handle)
1575 {
1576     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1577     struct smu_context *smu = adev->powerplay.pp_handle;
1578     int ret;
1579
1580     if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1581         return 0;
1582
1583     if (!smu->pm_enabled)
1584         return 0;
1585
1586     adev->pm.dpm_enabled = false;
1587
1588     ret = smu_smc_hw_cleanup(smu);
1589     if (ret)
1590         return ret;
1591
1592     smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1593
1594     smu_set_gfx_cgpg(smu, false);
1595
1596     return 0;
1597 }
1598
1599 static int smu_resume(void *handle)
1600 {
1601     int ret;
1602     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1603     struct smu_context *smu = adev->powerplay.pp_handle;
1604
1605     if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1606         return 0;
1607
1608     if (!smu->pm_enabled)
1609         return 0;
1610
1611     dev_info(adev->dev, "SMU is resuming...\n");
1612
1613     ret = smu_start_smc_engine(smu);
1614     if (ret) {
1615         dev_err(adev->dev, "SMC engine is not correctly up!\n");
1616         return ret;
1617     }
1618
1619     ret = smu_smc_hw_setup(smu);
1620     if (ret) {
1621         dev_err(adev->dev, "Failed to setup smc hw!\n");
1622         return ret;
1623     }
1624
1625     smu_set_gfx_cgpg(smu, true);
1626
1627     smu->disable_uclk_switch = 0;
1628
1629     adev->pm.dpm_enabled = true;
1630
1631     dev_info(adev->dev, "SMU is resumed successfully!\n");
1632
1633     return 0;
1634 }
1635
1636 static int smu_display_configuration_change(void *handle,
1637                         const struct amd_pp_display_configuration *display_config)
1638 {
1639     struct smu_context *smu = handle;
1640     int index = 0;
1641     int num_of_active_display = 0;
1642
1643     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1644         return -EOPNOTSUPP;
1645
1646     if (!display_config)
1647         return -EINVAL;
1648
1649     smu_set_min_dcef_deep_sleep(smu,
1650                     display_config->min_dcef_deep_sleep_set_clk / 100);
1651
1652     for (index = 0; index < display_config->num_path_including_non_display; index++) {
1653         if (display_config->displays[index].controller_id != 0)
1654             num_of_active_display++;
1655     }
1656
1657     return 0;
1658 }
1659
1660 static int smu_set_clockgating_state(void *handle,
1661                      enum amd_clockgating_state state)
1662 {
1663     return 0;
1664 }
1665
1666 static int smu_set_powergating_state(void *handle,
1667                      enum amd_powergating_state state)
1668 {
1669     return 0;
1670 }
1671
1672 static int smu_enable_umd_pstate(void *handle,
1673               enum amd_dpm_forced_level *level)
1674 {
1675     uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1676                     AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1677                     AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1678                     AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1679
1680     struct smu_context *smu = (struct smu_context*)(handle);
1681     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1682
1683     if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1684         return -EINVAL;
1685
1686     if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1687         /* enter umd pstate, save current level, disable gfx cg*/
1688         if (*level & profile_mode_mask) {
1689             smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1690             smu_gpo_control(smu, false);
1691             smu_gfx_ulv_control(smu, false);
1692             smu_deep_sleep_control(smu, false);
1693             amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1694         }
1695     } else {
1696         /* exit umd pstate, restore level, enable gfx cg*/
1697         if (!(*level & profile_mode_mask)) {
1698             if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1699                 *level = smu_dpm_ctx->saved_dpm_level;
1700             amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1701             smu_deep_sleep_control(smu, true);
1702             smu_gfx_ulv_control(smu, true);
1703             smu_gpo_control(smu, true);
1704         }
1705     }
1706
1707     return 0;
1708 }
1709
1710 static int smu_bump_power_profile_mode(struct smu_context *smu,
1711                        long *param,
1712                        uint32_t param_size)
1713 {
1714     int ret = 0;
1715
1716     if (smu->ppt_funcs->set_power_profile_mode)
1717         ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1718
1719     return ret;
1720 }
1721
1722 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1723                    enum amd_dpm_forced_level level,
1724                    bool skip_display_settings)
1725 {
1726     int ret = 0;
1727     int index = 0;
1728     long workload;
1729     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1730
1731     if (!skip_display_settings) {
1732         ret = smu_display_config_changed(smu);
1733         if (ret) {
1734             dev_err(smu->adev->dev, "Failed to change display config!");
1735             return ret;
1736         }
1737     }
1738
1739     ret = smu_apply_clocks_adjust_rules(smu);
1740     if (ret) {
1741         dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1742         return ret;
1743     }
1744
1745     if (!skip_display_settings) {
1746         ret = smu_notify_smc_display_config(smu);
1747         if (ret) {
1748             dev_err(smu->adev->dev, "Failed to notify smc display config!");
1749             return ret;
1750         }
1751     }
1752
1753     if (smu_dpm_ctx->dpm_level != level) {
1754         ret = smu_asic_set_performance_level(smu, level);
1755         if (ret) {
1756             dev_err(smu->adev->dev, "Failed to set performance level!");
1757             return ret;
1758         }
1759
1760         /* update the saved copy */
1761         smu_dpm_ctx->dpm_level = level;
1762     }
1763
1764     if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1765         smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1766         index = fls(smu->workload_mask);
1767         index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1768         workload = smu->workload_setting[index];
1769
1770         if (smu->power_profile_mode != workload)
1771             smu_bump_power_profile_mode(smu, &workload, 0);
1772     }
1773
1774     return ret;
1775 }
1776
1777 static int smu_handle_task(struct smu_context *smu,
1778                enum amd_dpm_forced_level level,
1779                enum amd_pp_task task_id)
1780 {
1781     int ret = 0;
1782
1783     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1784         return -EOPNOTSUPP;
1785
1786     switch (task_id) {
1787     case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1788         ret = smu_pre_display_config_changed(smu);
1789         if (ret)
1790             return ret;
1791         ret = smu_adjust_power_state_dynamic(smu, level, false);
1792         break;
1793     case AMD_PP_TASK_COMPLETE_INIT:
1794     case AMD_PP_TASK_READJUST_POWER_STATE:
1795         ret = smu_adjust_power_state_dynamic(smu, level, true);
1796         break;
1797     default:
1798         break;
1799     }
1800
1801     return ret;
1802 }
1803
1804 static int smu_handle_dpm_task(void *handle,
1805                    enum amd_pp_task task_id,
1806                    enum amd_pm_state_type *user_state)
1807 {
1808     struct smu_context *smu = handle;
1809     struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1810
1811     return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1812
1813 }
1814
1815 static int smu_switch_power_profile(void *handle,
1816                     enum PP_SMC_POWER_PROFILE type,
1817                     bool en)
1818 {
1819     struct smu_context *smu = handle;
1820     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1821     long workload;
1822     uint32_t index;
1823
1824     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1825         return -EOPNOTSUPP;
1826
1827     if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1828         return -EINVAL;
1829
1830     if (!en) {
1831         smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1832         index = fls(smu->workload_mask);
1833         index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1834         workload = smu->workload_setting[index];
1835     } else {
1836         smu->workload_mask |= (1 << smu->workload_prority[type]);
1837         index = fls(smu->workload_mask);
1838         index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1839         workload = smu->workload_setting[index];
1840     }
1841
1842     if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1843         smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1844         smu_bump_power_profile_mode(smu, &workload, 0);
1845
1846     return 0;
1847 }
1848
1849 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1850 {
1851     struct smu_context *smu = handle;
1852     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1853
1854     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1855         return -EOPNOTSUPP;
1856
1857     if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1858         return -EINVAL;
1859
1860     return smu_dpm_ctx->dpm_level;
1861 }
1862
1863 static int smu_force_performance_level(void *handle,
1864                        enum amd_dpm_forced_level level)
1865 {
1866     struct smu_context *smu = handle;
1867     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1868     int ret = 0;
1869
1870     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1871         return -EOPNOTSUPP;
1872
1873     if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1874         return -EINVAL;
1875
1876     ret = smu_enable_umd_pstate(smu, &level);
1877     if (ret)
1878         return ret;
1879
1880     ret = smu_handle_task(smu, level,
1881                   AMD_PP_TASK_READJUST_POWER_STATE);
1882
1883     /* reset user dpm clock state */
1884     if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1885         memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1886         smu->user_dpm_profile.clk_dependency = 0;
1887     }
1888
1889     return ret;
1890 }
1891
1892 static int smu_set_display_count(void *handle, uint32_t count)
1893 {
1894     struct smu_context *smu = handle;
1895
1896     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1897         return -EOPNOTSUPP;
1898
1899     return smu_init_display_count(smu, count);
1900 }
1901
1902 static int smu_force_smuclk_levels(struct smu_context *smu,
1903              enum smu_clk_type clk_type,
1904              uint32_t mask)
1905 {
1906     struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1907     int ret = 0;
1908
1909     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1910         return -EOPNOTSUPP;
1911
1912     if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1913         dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1914         return -EINVAL;
1915     }
1916
1917     if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1918         ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1919         if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1920             smu->user_dpm_profile.clk_mask[clk_type] = mask;
1921             smu_set_user_clk_dependencies(smu, clk_type);
1922         }
1923     }
1924
1925     return ret;
1926 }
1927
1928 static int smu_force_ppclk_levels(void *handle,
1929                   enum pp_clock_type type,
1930                   uint32_t mask)
1931 {
1932     struct smu_context *smu = handle;
1933     enum smu_clk_type clk_type;
1934
1935     switch (type) {
1936     case PP_SCLK:
1937         clk_type = SMU_SCLK; break;
1938     case PP_MCLK:
1939         clk_type = SMU_MCLK; break;
1940     case PP_PCIE:
1941         clk_type = SMU_PCIE; break;
1942     case PP_SOCCLK:
1943         clk_type = SMU_SOCCLK; break;
1944     case PP_FCLK:
1945         clk_type = SMU_FCLK; break;
1946     case PP_DCEFCLK:
1947         clk_type = SMU_DCEFCLK; break;
1948     case PP_VCLK:
1949         clk_type = SMU_VCLK; break;
1950     case PP_DCLK:
1951         clk_type = SMU_DCLK; break;
1952     case OD_SCLK:
1953         clk_type = SMU_OD_SCLK; break;
1954     case OD_MCLK:
1955         clk_type = SMU_OD_MCLK; break;
1956     case OD_VDDC_CURVE:
1957         clk_type = SMU_OD_VDDC_CURVE; break;
1958     case OD_RANGE:
1959         clk_type = SMU_OD_RANGE; break;
1960     default:
1961         return -EINVAL;
1962     }
1963
1964     return smu_force_smuclk_levels(smu, clk_type, mask);
1965 }
1966
1967 /*
1968  * On system suspending or resetting, the dpm_enabled
1969  * flag will be cleared. So that those SMU services which
1970  * are not supported will be gated.
1971  * However, the mp1 state setting should still be granted
1972  * even if the dpm_enabled cleared.
1973  */
1974 static int smu_set_mp1_state(void *handle,
1975                  enum pp_mp1_state mp1_state)
1976 {
1977     struct smu_context *smu = handle;
1978     int ret = 0;
1979
1980     if (!smu->pm_enabled)
1981         return -EOPNOTSUPP;
1982
1983     if (smu->ppt_funcs &&
1984         smu->ppt_funcs->set_mp1_state)
1985         ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
1986
1987     return ret;
1988 }
1989
1990 static int smu_set_df_cstate(void *handle,
1991                  enum pp_df_cstate state)
1992 {
1993     struct smu_context *smu = handle;
1994     int ret = 0;
1995
1996     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1997         return -EOPNOTSUPP;
1998
1999     if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2000         return 0;
2001
2002     ret = smu->ppt_funcs->set_df_cstate(smu, state);
2003     if (ret)
2004         dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2005
2006     return ret;
2007 }
2008
2009 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2010 {
2011     int ret = 0;
2012
2013     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2014         return -EOPNOTSUPP;
2015
2016     if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2017         return 0;
2018
2019     ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2020     if (ret)
2021         dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2022
2023     return ret;
2024 }
2025
2026 int smu_write_watermarks_table(struct smu_context *smu)
2027 {
2028     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2029         return -EOPNOTSUPP;
2030
2031     return smu_set_watermarks_table(smu, NULL);
2032 }
2033
2034 static int smu_set_watermarks_for_clock_ranges(void *handle,
2035                            struct pp_smu_wm_range_sets *clock_ranges)
2036 {
2037     struct smu_context *smu = handle;
2038
2039     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2040         return -EOPNOTSUPP;
2041
2042     if (smu->disable_watermark)
2043         return 0;
2044
2045     return smu_set_watermarks_table(smu, clock_ranges);
2046 }
2047
2048 int smu_set_ac_dc(struct smu_context *smu)
2049 {
2050     int ret = 0;
2051
2052     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2053         return -EOPNOTSUPP;
2054
2055     /* controlled by firmware */
2056     if (smu->dc_controlled_by_gpio)
2057         return 0;
2058
2059     ret = smu_set_power_source(smu,
2060                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2061                    SMU_POWER_SOURCE_DC);
2062     if (ret)
2063         dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2064                smu->adev->pm.ac_power ? "AC" : "DC");
2065
2066     return ret;
2067 }
2068
2069 const struct amd_ip_funcs smu_ip_funcs = {
2070     .name = "smu",
2071     .early_init = smu_early_init,
2072     .late_init = smu_late_init,
2073     .sw_init = smu_sw_init,
2074     .sw_fini = smu_sw_fini,
2075     .hw_init = smu_hw_init,
2076     .hw_fini = smu_hw_fini,
2077     .late_fini = smu_late_fini,
2078     .suspend = smu_suspend,
2079     .resume = smu_resume,
2080     .is_idle = NULL,
2081     .check_soft_reset = NULL,
2082     .wait_for_idle = NULL,
2083     .soft_reset = NULL,
2084     .set_clockgating_state = smu_set_clockgating_state,
2085     .set_powergating_state = smu_set_powergating_state,
2086 };
2087
2088 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2089 {
2090     .type = AMD_IP_BLOCK_TYPE_SMC,
2091     .major = 11,
2092     .minor = 0,
2093     .rev = 0,
2094     .funcs = &smu_ip_funcs,
2095 };
2096
2097 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2098 {
2099     .type = AMD_IP_BLOCK_TYPE_SMC,
2100     .major = 12,
2101     .minor = 0,
2102     .rev = 0,
2103     .funcs = &smu_ip_funcs,
2104 };
2105
2106 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2107 {
2108     .type = AMD_IP_BLOCK_TYPE_SMC,
2109     .major = 13,
2110     .minor = 0,
2111     .rev = 0,
2112     .funcs = &smu_ip_funcs,
2113 };
2114
2115 static int smu_load_microcode(void *handle)
2116 {
2117     struct smu_context *smu = handle;
2118     struct amdgpu_device *adev = smu->adev;
2119     int ret = 0;
2120
2121     if (!smu->pm_enabled)
2122         return -EOPNOTSUPP;
2123
2124     /* This should be used for non PSP loading */
2125     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2126         return 0;
2127
2128     if (smu->ppt_funcs->load_microcode) {
2129         ret = smu->ppt_funcs->load_microcode(smu);
2130         if (ret) {
2131             dev_err(adev->dev, "Load microcode failed\n");
2132             return ret;
2133         }
2134     }
2135
2136     if (smu->ppt_funcs->check_fw_status) {
2137         ret = smu->ppt_funcs->check_fw_status(smu);
2138         if (ret) {
2139             dev_err(adev->dev, "SMC is not ready\n");
2140             return ret;
2141         }
2142     }
2143
2144     return ret;
2145 }
2146
2147 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2148 {
2149     int ret = 0;
2150
2151     if (smu->ppt_funcs->set_gfx_cgpg)
2152         ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2153
2154     return ret;
2155 }
2156
2157 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2158 {
2159     struct smu_context *smu = handle;
2160     int ret = 0;
2161
2162     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2163         return -EOPNOTSUPP;
2164
2165     if (!smu->ppt_funcs->set_fan_speed_rpm)
2166         return -EOPNOTSUPP;
2167
2168     if (speed == U32_MAX)
2169         return -EINVAL;
2170
2171     ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2172     if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2173         smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2174         smu->user_dpm_profile.fan_speed_rpm = speed;
2175
2176         /* Override custom PWM setting as they cannot co-exist */
2177         smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2178         smu->user_dpm_profile.fan_speed_pwm = 0;
2179     }
2180
2181     return ret;
2182 }
2183
2184 /**
2185  * smu_get_power_limit - Request one of the SMU Power Limits
2186  *
2187  * @handle: pointer to smu context
2188  * @limit: requested limit is written back to this variable
2189  * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2190  * @pp_power_type: &pp_power_type type of power
2191  * Return:  0 on success, <0 on error
2192  *
2193  */
2194 int smu_get_power_limit(void *handle,
2195             uint32_t *limit,
2196             enum pp_power_limit_level pp_limit_level,
2197             enum pp_power_type pp_power_type)
2198 {
2199     struct smu_context *smu = handle;
2200     struct amdgpu_device *adev = smu->adev;
2201     enum smu_ppt_limit_level limit_level;
2202     uint32_t limit_type;
2203     int ret = 0;
2204
2205     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2206         return -EOPNOTSUPP;
2207
2208     switch(pp_power_type) {
2209     case PP_PWR_TYPE_SUSTAINED:
2210         limit_type = SMU_DEFAULT_PPT_LIMIT;
2211         break;
2212     case PP_PWR_TYPE_FAST:
2213         limit_type = SMU_FAST_PPT_LIMIT;
2214         break;
2215     default:
2216         return -EOPNOTSUPP;
2217         break;
2218     }
2219
2220     switch(pp_limit_level){
2221     case PP_PWR_LIMIT_CURRENT:
2222         limit_level = SMU_PPT_LIMIT_CURRENT;
2223         break;
2224     case PP_PWR_LIMIT_DEFAULT:
2225         limit_level = SMU_PPT_LIMIT_DEFAULT;
2226         break;
2227     case PP_PWR_LIMIT_MAX:
2228         limit_level = SMU_PPT_LIMIT_MAX;
2229         break;
2230     case PP_PWR_LIMIT_MIN:
2231     default:
2232         return -EOPNOTSUPP;
2233         break;
2234     }
2235
2236     if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2237         if (smu->ppt_funcs->get_ppt_limit)
2238             ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2239     } else {
2240         switch (limit_level) {
2241         case SMU_PPT_LIMIT_CURRENT:
2242             switch (adev->ip_versions[MP1_HWIP][0]) {
2243             case IP_VERSION(13, 0, 2):
2244             case IP_VERSION(11, 0, 7):
2245             case IP_VERSION(11, 0, 11):
2246             case IP_VERSION(11, 0, 12):
2247             case IP_VERSION(11, 0, 13):
2248                 ret = smu_get_asic_power_limits(smu,
2249                                 &smu->current_power_limit,
2250                                 NULL,
2251                                 NULL);
2252                 break;
2253             default:
2254                 break;
2255             }
2256             *limit = smu->current_power_limit;
2257             break;
2258         case SMU_PPT_LIMIT_DEFAULT:
2259             *limit = smu->default_power_limit;
2260             break;
2261         case SMU_PPT_LIMIT_MAX:
2262             *limit = smu->max_power_limit;
2263             break;
2264         default:
2265             break;
2266         }
2267     }
2268
2269     return ret;
2270 }
2271
2272 static int smu_set_power_limit(void *handle, uint32_t limit)
2273 {
2274     struct smu_context *smu = handle;
2275     uint32_t limit_type = limit >> 24;
2276     int ret = 0;
2277
2278     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2279         return -EOPNOTSUPP;
2280
2281     limit &= (1<<24)-1;
2282     if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2283         if (smu->ppt_funcs->set_power_limit)
2284             return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2285
2286     if (limit > smu->max_power_limit) {
2287         dev_err(smu->adev->dev,
2288             "New power limit (%d) is over the max allowed %d\n",
2289             limit, smu->max_power_limit);
2290         return -EINVAL;
2291     }
2292
2293     if (!limit)
2294         limit = smu->current_power_limit;
2295
2296     if (smu->ppt_funcs->set_power_limit) {
2297         ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2298         if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2299             smu->user_dpm_profile.power_limit = limit;
2300     }
2301
2302     return ret;
2303 }
2304
2305 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2306 {
2307     int ret = 0;
2308
2309     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2310         return -EOPNOTSUPP;
2311
2312     if (smu->ppt_funcs->print_clk_levels)
2313         ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2314
2315     return ret;
2316 }
2317
2318 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2319 {
2320     enum smu_clk_type clk_type;
2321
2322     switch (type) {
2323     case PP_SCLK:
2324         clk_type = SMU_SCLK; break;
2325     case PP_MCLK:
2326         clk_type = SMU_MCLK; break;
2327     case PP_PCIE:
2328         clk_type = SMU_PCIE; break;
2329     case PP_SOCCLK:
2330         clk_type = SMU_SOCCLK; break;
2331     case PP_FCLK:
2332         clk_type = SMU_FCLK; break;
2333     case PP_DCEFCLK:
2334         clk_type = SMU_DCEFCLK; break;
2335     case PP_VCLK:
2336         clk_type = SMU_VCLK; break;
2337     case PP_DCLK:
2338         clk_type = SMU_DCLK; break;
2339     case OD_SCLK:
2340         clk_type = SMU_OD_SCLK; break;
2341     case OD_MCLK:
2342         clk_type = SMU_OD_MCLK; break;
2343     case OD_VDDC_CURVE:
2344         clk_type = SMU_OD_VDDC_CURVE; break;
2345     case OD_RANGE:
2346         clk_type = SMU_OD_RANGE; break;
2347     case OD_VDDGFX_OFFSET:
2348         clk_type = SMU_OD_VDDGFX_OFFSET; break;
2349     case OD_CCLK:
2350         clk_type = SMU_OD_CCLK; break;
2351     default:
2352         clk_type = SMU_CLK_COUNT; break;
2353     }
2354
2355     return clk_type;
2356 }
2357
2358 static int smu_print_ppclk_levels(void *handle,
2359                   enum pp_clock_type type,
2360                   char *buf)
2361 {
2362     struct smu_context *smu = handle;
2363     enum smu_clk_type clk_type;
2364
2365     clk_type = smu_convert_to_smuclk(type);
2366     if (clk_type == SMU_CLK_COUNT)
2367         return -EINVAL;
2368
2369     return smu_print_smuclk_levels(smu, clk_type, buf);
2370 }
2371
2372 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2373 {
2374     struct smu_context *smu = handle;
2375     enum smu_clk_type clk_type;
2376
2377     clk_type = smu_convert_to_smuclk(type);
2378     if (clk_type == SMU_CLK_COUNT)
2379         return -EINVAL;
2380
2381     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2382         return -EOPNOTSUPP;
2383
2384     if (!smu->ppt_funcs->emit_clk_levels)
2385         return -ENOENT;
2386
2387     return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2388
2389 }
2390
2391 static int smu_od_edit_dpm_table(void *handle,
2392                  enum PP_OD_DPM_TABLE_COMMAND type,
2393                  long *input, uint32_t size)
2394 {
2395     struct smu_context *smu = handle;
2396     int ret = 0;
2397
2398     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2399         return -EOPNOTSUPP;
2400
2401     if (smu->ppt_funcs->od_edit_dpm_table) {
2402         ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2403     }
2404
2405     return ret;
2406 }
2407
2408 static int smu_read_sensor(void *handle,
2409                int sensor,
2410                void *data,
2411                int *size_arg)
2412 {
2413     struct smu_context *smu = handle;
2414     struct smu_umd_pstate_table *pstate_table =
2415                 &smu->pstate_table;
2416     int ret = 0;
2417     uint32_t *size, size_val;
2418
2419     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2420         return -EOPNOTSUPP;
2421
2422     if (!data || !size_arg)
2423         return -EINVAL;
2424
2425     size_val = *size_arg;
2426     size = &size_val;
2427
2428     if (smu->ppt_funcs->read_sensor)
2429         if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2430             goto unlock;
2431
2432     switch (sensor) {
2433     case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2434         *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2435         *size = 4;
2436         break;
2437     case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2438         *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2439         *size = 4;
2440         break;
2441     case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2442         ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2443         *size = 8;
2444         break;
2445     case AMDGPU_PP_SENSOR_UVD_POWER:
2446         *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2447         *size = 4;
2448         break;
2449     case AMDGPU_PP_SENSOR_VCE_POWER:
2450         *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2451         *size = 4;
2452         break;
2453     case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2454         *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2455         *size = 4;
2456         break;
2457     case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2458         *(uint32_t *)data = 0;
2459         *size = 4;
2460         break;
2461     default:
2462         *size = 0;
2463         ret = -EOPNOTSUPP;
2464         break;
2465     }
2466
2467 unlock:
2468     // assign uint32_t to int
2469     *size_arg = size_val;
2470
2471     return ret;
2472 }
2473
2474 static int smu_get_power_profile_mode(void *handle, char *buf)
2475 {
2476     struct smu_context *smu = handle;
2477
2478     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2479         !smu->ppt_funcs->get_power_profile_mode)
2480         return -EOPNOTSUPP;
2481     if (!buf)
2482         return -EINVAL;
2483
2484     return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2485 }
2486
2487 static int smu_set_power_profile_mode(void *handle,
2488                       long *param,
2489                       uint32_t param_size)
2490 {
2491     struct smu_context *smu = handle;
2492
2493     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2494         !smu->ppt_funcs->set_power_profile_mode)
2495         return -EOPNOTSUPP;
2496
2497     return smu_bump_power_profile_mode(smu, param, param_size);
2498 }
2499
2500 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2501 {
2502     struct smu_context *smu = handle;
2503
2504     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2505         return -EOPNOTSUPP;
2506
2507     if (!smu->ppt_funcs->get_fan_control_mode)
2508         return -EOPNOTSUPP;
2509
2510     if (!fan_mode)
2511         return -EINVAL;
2512
2513     *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2514
2515     return 0;
2516 }
2517
2518 static int smu_set_fan_control_mode(void *handle, u32 value)
2519 {
2520     struct smu_context *smu = handle;
2521     int ret = 0;
2522
2523     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2524         return -EOPNOTSUPP;
2525
2526     if (!smu->ppt_funcs->set_fan_control_mode)
2527         return -EOPNOTSUPP;
2528
2529     if (value == U32_MAX)
2530         return -EINVAL;
2531
2532     ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2533     if (ret)
2534         goto out;
2535
2536     if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2537         smu->user_dpm_profile.fan_mode = value;
2538
2539         /* reset user dpm fan speed */
2540         if (value != AMD_FAN_CTRL_MANUAL) {
2541             smu->user_dpm_profile.fan_speed_pwm = 0;
2542             smu->user_dpm_profile.fan_speed_rpm = 0;
2543             smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2544         }
2545     }
2546
2547 out:
2548     return ret;
2549 }
2550
2551 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2552 {
2553     struct smu_context *smu = handle;
2554     int ret = 0;
2555
2556     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2557         return -EOPNOTSUPP;
2558
2559     if (!smu->ppt_funcs->get_fan_speed_pwm)
2560         return -EOPNOTSUPP;
2561
2562     if (!speed)
2563         return -EINVAL;
2564
2565     ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2566
2567     return ret;
2568 }
2569
2570 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2571 {
2572     struct smu_context *smu = handle;
2573     int ret = 0;
2574
2575     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2576         return -EOPNOTSUPP;
2577
2578     if (!smu->ppt_funcs->set_fan_speed_pwm)
2579         return -EOPNOTSUPP;
2580
2581     if (speed == U32_MAX)
2582         return -EINVAL;
2583
2584     ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2585     if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2586         smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2587         smu->user_dpm_profile.fan_speed_pwm = speed;
2588
2589         /* Override custom RPM setting as they cannot co-exist */
2590         smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2591         smu->user_dpm_profile.fan_speed_rpm = 0;
2592     }
2593
2594     return ret;
2595 }
2596
2597 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2598 {
2599     struct smu_context *smu = handle;
2600     int ret = 0;
2601
2602     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2603         return -EOPNOTSUPP;
2604
2605     if (!smu->ppt_funcs->get_fan_speed_rpm)
2606         return -EOPNOTSUPP;
2607
2608     if (!speed)
2609         return -EINVAL;
2610
2611     ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2612
2613     return ret;
2614 }
2615
2616 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2617 {
2618     struct smu_context *smu = handle;
2619
2620     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2621         return -EOPNOTSUPP;
2622
2623     return smu_set_min_dcef_deep_sleep(smu, clk);
2624 }
2625
2626 static int smu_get_clock_by_type_with_latency(void *handle,
2627                           enum amd_pp_clock_type type,
2628                           struct pp_clock_levels_with_latency *clocks)
2629 {
2630     struct smu_context *smu = handle;
2631     enum smu_clk_type clk_type;
2632     int ret = 0;
2633
2634     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2635         return -EOPNOTSUPP;
2636
2637     if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2638         switch (type) {
2639         case amd_pp_sys_clock:
2640             clk_type = SMU_GFXCLK;
2641             break;
2642         case amd_pp_mem_clock:
2643             clk_type = SMU_MCLK;
2644             break;
2645         case amd_pp_dcef_clock:
2646             clk_type = SMU_DCEFCLK;
2647             break;
2648         case amd_pp_disp_clock:
2649             clk_type = SMU_DISPCLK;
2650             break;
2651         default:
2652             dev_err(smu->adev->dev, "Invalid clock type!\n");
2653             return -EINVAL;
2654         }
2655
2656         ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2657     }
2658
2659     return ret;
2660 }
2661
2662 static int smu_display_clock_voltage_request(void *handle,
2663                          struct pp_display_clock_request *clock_req)
2664 {
2665     struct smu_context *smu = handle;
2666     int ret = 0;
2667
2668     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2669         return -EOPNOTSUPP;
2670
2671     if (smu->ppt_funcs->display_clock_voltage_request)
2672         ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2673
2674     return ret;
2675 }
2676
2677
2678 static int smu_display_disable_memory_clock_switch(void *handle,
2679                            bool disable_memory_clock_switch)
2680 {
2681     struct smu_context *smu = handle;
2682     int ret = -EINVAL;
2683
2684     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2685         return -EOPNOTSUPP;
2686
2687     if (smu->ppt_funcs->display_disable_memory_clock_switch)
2688         ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2689
2690     return ret;
2691 }
2692
2693 static int smu_set_xgmi_pstate(void *handle,
2694                    uint32_t pstate)
2695 {
2696     struct smu_context *smu = handle;
2697     int ret = 0;
2698
2699     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2700         return -EOPNOTSUPP;
2701
2702     if (smu->ppt_funcs->set_xgmi_pstate)
2703         ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2704
2705     if(ret)
2706         dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2707
2708     return ret;
2709 }
2710
2711 static int smu_get_baco_capability(void *handle, bool *cap)
2712 {
2713     struct smu_context *smu = handle;
2714
2715     *cap = false;
2716
2717     if (!smu->pm_enabled)
2718         return 0;
2719
2720     if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2721         *cap = smu->ppt_funcs->baco_is_support(smu);
2722
2723     return 0;
2724 }
2725
2726 static int smu_baco_set_state(void *handle, int state)
2727 {
2728     struct smu_context *smu = handle;
2729     int ret = 0;
2730
2731     if (!smu->pm_enabled)
2732         return -EOPNOTSUPP;
2733
2734     if (state == 0) {
2735         if (smu->ppt_funcs->baco_exit)
2736             ret = smu->ppt_funcs->baco_exit(smu);
2737     } else if (state == 1) {
2738         if (smu->ppt_funcs->baco_enter)
2739             ret = smu->ppt_funcs->baco_enter(smu);
2740     } else {
2741         return -EINVAL;
2742     }
2743
2744     if (ret)
2745         dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2746                 (state)?"enter":"exit");
2747
2748     return ret;
2749 }
2750
2751 bool smu_mode1_reset_is_support(struct smu_context *smu)
2752 {
2753     bool ret = false;
2754
2755     if (!smu->pm_enabled)
2756         return false;
2757
2758     if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2759         ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2760
2761     return ret;
2762 }
2763
2764 bool smu_mode2_reset_is_support(struct smu_context *smu)
2765 {
2766     bool ret = false;
2767
2768     if (!smu->pm_enabled)
2769         return false;
2770
2771     if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2772         ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2773
2774     return ret;
2775 }
2776
2777 int smu_mode1_reset(struct smu_context *smu)
2778 {
2779     int ret = 0;
2780
2781     if (!smu->pm_enabled)
2782         return -EOPNOTSUPP;
2783
2784     if (smu->ppt_funcs->mode1_reset)
2785         ret = smu->ppt_funcs->mode1_reset(smu);
2786
2787     return ret;
2788 }
2789
2790 static int smu_mode2_reset(void *handle)
2791 {
2792     struct smu_context *smu = handle;
2793     int ret = 0;
2794
2795     if (!smu->pm_enabled)
2796         return -EOPNOTSUPP;
2797
2798     if (smu->ppt_funcs->mode2_reset)
2799         ret = smu->ppt_funcs->mode2_reset(smu);
2800
2801     if (ret)
2802         dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2803
2804     return ret;
2805 }
2806
2807 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2808                         struct pp_smu_nv_clock_table *max_clocks)
2809 {
2810     struct smu_context *smu = handle;
2811     int ret = 0;
2812
2813     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2814         return -EOPNOTSUPP;
2815
2816     if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2817         ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2818
2819     return ret;
2820 }
2821
2822 static int smu_get_uclk_dpm_states(void *handle,
2823                    unsigned int *clock_values_in_khz,
2824                    unsigned int *num_states)
2825 {
2826     struct smu_context *smu = handle;
2827     int ret = 0;
2828
2829     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2830         return -EOPNOTSUPP;
2831
2832     if (smu->ppt_funcs->get_uclk_dpm_states)
2833         ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2834
2835     return ret;
2836 }
2837
2838 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2839 {
2840     struct smu_context *smu = handle;
2841     enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2842
2843     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2844         return -EOPNOTSUPP;
2845
2846     if (smu->ppt_funcs->get_current_power_state)
2847         pm_state = smu->ppt_funcs->get_current_power_state(smu);
2848
2849     return pm_state;
2850 }
2851
2852 static int smu_get_dpm_clock_table(void *handle,
2853                    struct dpm_clocks *clock_table)
2854 {
2855     struct smu_context *smu = handle;
2856     int ret = 0;
2857
2858     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2859         return -EOPNOTSUPP;
2860
2861     if (smu->ppt_funcs->get_dpm_clock_table)
2862         ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2863
2864     return ret;
2865 }
2866
2867 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2868 {
2869     struct smu_context *smu = handle;
2870
2871     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2872         return -EOPNOTSUPP;
2873
2874     if (!smu->ppt_funcs->get_gpu_metrics)
2875         return -EOPNOTSUPP;
2876
2877     return smu->ppt_funcs->get_gpu_metrics(smu, table);
2878 }
2879
2880 static int smu_enable_mgpu_fan_boost(void *handle)
2881 {
2882     struct smu_context *smu = handle;
2883     int ret = 0;
2884
2885     if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2886         return -EOPNOTSUPP;
2887
2888     if (smu->ppt_funcs->enable_mgpu_fan_boost)
2889         ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2890
2891     return ret;
2892 }
2893
2894 static int smu_gfx_state_change_set(void *handle,
2895                     uint32_t state)
2896 {
2897     struct smu_context *smu = handle;
2898     int ret = 0;
2899
2900     if (smu->ppt_funcs->gfx_state_change_set)
2901         ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2902
2903     return ret;
2904 }
2905
2906 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
2907 {
2908     int ret = 0;
2909
2910     if (smu->ppt_funcs->smu_handle_passthrough_sbr)
2911         ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
2912
2913     return ret;
2914 }
2915
2916 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
2917 {
2918     int ret = -EOPNOTSUPP;
2919
2920     if (smu->ppt_funcs &&
2921         smu->ppt_funcs->get_ecc_info)
2922         ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
2923
2924     return ret;
2925
2926 }
2927
2928 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
2929 {
2930     struct smu_context *smu = handle;
2931     struct smu_table_context *smu_table = &smu->smu_table;
2932     struct smu_table *memory_pool = &smu_table->memory_pool;
2933
2934     if (!addr || !size)
2935         return -EINVAL;
2936
2937     *addr = NULL;
2938     *size = 0;
2939     if (memory_pool->bo) {
2940         *addr = memory_pool->cpu_addr;
2941         *size = memory_pool->size;
2942     }
2943
2944     return 0;
2945 }
2946
2947 static const struct amd_pm_funcs swsmu_pm_funcs = {
2948     /* export for sysfs */
2949     .set_fan_control_mode    = smu_set_fan_control_mode,
2950     .get_fan_control_mode    = smu_get_fan_control_mode,
2951     .set_fan_speed_pwm   = smu_set_fan_speed_pwm,
2952     .get_fan_speed_pwm   = smu_get_fan_speed_pwm,
2953     .force_clock_level       = smu_force_ppclk_levels,
2954     .print_clock_levels      = smu_print_ppclk_levels,
2955     .emit_clock_levels       = smu_emit_ppclk_levels,
2956     .force_performance_level = smu_force_performance_level,
2957     .read_sensor             = smu_read_sensor,
2958     .get_performance_level   = smu_get_performance_level,
2959     .get_current_power_state = smu_get_current_power_state,
2960     .get_fan_speed_rpm       = smu_get_fan_speed_rpm,
2961     .set_fan_speed_rpm       = smu_set_fan_speed_rpm,
2962     .get_pp_num_states       = smu_get_power_num_states,
2963     .get_pp_table            = smu_sys_get_pp_table,
2964     .set_pp_table            = smu_sys_set_pp_table,
2965     .switch_power_profile    = smu_switch_power_profile,
2966     /* export to amdgpu */
2967     .dispatch_tasks          = smu_handle_dpm_task,
2968     .load_firmware           = smu_load_microcode,
2969     .set_powergating_by_smu  = smu_dpm_set_power_gate,
2970     .set_power_limit         = smu_set_power_limit,
2971     .get_power_limit         = smu_get_power_limit,
2972     .get_power_profile_mode  = smu_get_power_profile_mode,
2973     .set_power_profile_mode  = smu_set_power_profile_mode,
2974     .odn_edit_dpm_table      = smu_od_edit_dpm_table,
2975     .set_mp1_state           = smu_set_mp1_state,
2976     .gfx_state_change_set    = smu_gfx_state_change_set,
2977     /* export to DC */
2978     .get_sclk                         = smu_get_sclk,
2979     .get_mclk                         = smu_get_mclk,
2980     .display_configuration_change     = smu_display_configuration_change,
2981     .get_clock_by_type_with_latency   = smu_get_clock_by_type_with_latency,
2982     .display_clock_voltage_request    = smu_display_clock_voltage_request,
2983     .enable_mgpu_fan_boost            = smu_enable_mgpu_fan_boost,
2984     .set_active_display_count         = smu_set_display_count,
2985     .set_min_deep_sleep_dcefclk       = smu_set_deep_sleep_dcefclk,
2986     .get_asic_baco_capability         = smu_get_baco_capability,
2987     .set_asic_baco_state              = smu_baco_set_state,
2988     .get_ppfeature_status             = smu_sys_get_pp_feature_mask,
2989     .set_ppfeature_status             = smu_sys_set_pp_feature_mask,
2990     .asic_reset_mode_2                = smu_mode2_reset,
2991     .set_df_cstate                    = smu_set_df_cstate,
2992     .set_xgmi_pstate                  = smu_set_xgmi_pstate,
2993     .get_gpu_metrics                  = smu_sys_get_gpu_metrics,
2994     .set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,
2995     .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
2996     .get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,
2997     .get_uclk_dpm_states              = smu_get_uclk_dpm_states,
2998     .get_dpm_clock_table              = smu_get_dpm_clock_table,
2999     .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3000 };
3001
3002 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3003                uint64_t event_arg)
3004 {
3005     int ret = -EINVAL;
3006
3007     if (smu->ppt_funcs->wait_for_event)
3008         ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3009
3010     return ret;
3011 }
3012
3013 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3014 {
3015
3016     if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3017         return -EOPNOTSUPP;
3018
3019     /* Confirm the buffer allocated is of correct size */
3020     if (size != smu->stb_context.stb_buf_size)
3021         return -EINVAL;
3022
3023     /*
3024      * No need to lock smu mutex as we access STB directly through MMIO
3025      * and not going through SMU messaging route (for now at least).
3026      * For registers access rely on implementation internal locking.
3027      */
3028     return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3029 }
3030
3031 #if defined(CONFIG_DEBUG_FS)
3032
3033 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3034 {
3035     struct amdgpu_device *adev = filp->f_inode->i_private;
3036     struct smu_context *smu = adev->powerplay.pp_handle;
3037     unsigned char *buf;
3038     int r;
3039
3040     buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3041     if (!buf)
3042         return -ENOMEM;
3043
3044     r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3045     if (r)
3046         goto out;
3047
3048     filp->private_data = buf;
3049
3050     return 0;
3051
3052 out:
3053     kvfree(buf);
3054     return r;
3055 }
3056
3057 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3058                 loff_t *pos)
3059 {
3060     struct amdgpu_device *adev = filp->f_inode->i_private;
3061     struct smu_context *smu = adev->powerplay.pp_handle;
3062
3063
3064     if (!filp->private_data)
3065         return -EINVAL;
3066
3067     return simple_read_from_buffer(buf,
3068                        size,
3069                        pos, filp->private_data,
3070                        smu->stb_context.stb_buf_size);
3071 }
3072
3073 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3074 {
3075     kvfree(filp->private_data);
3076     filp->private_data = NULL;
3077
3078     return 0;
3079 }
3080
3081 /*
3082  * We have to define not only read method but also
3083  * open and release because .read takes up to PAGE_SIZE
3084  * data each time so and so is invoked multiple times.
3085  *  We allocate the STB buffer in .open and release it
3086  *  in .release
3087  */
3088 static const struct file_operations smu_stb_debugfs_fops = {
3089     .owner = THIS_MODULE,
3090     .open = smu_stb_debugfs_open,
3091     .read = smu_stb_debugfs_read,
3092     .release = smu_stb_debugfs_release,
3093     .llseek = default_llseek,
3094 };
3095
3096 #endif
3097
3098 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3099 {
3100 #if defined(CONFIG_DEBUG_FS)
3101
3102     struct smu_context *smu = adev->powerplay.pp_handle;
3103
3104     if (!smu || (!smu->stb_context.stb_buf_size))
3105         return;
3106
3107     debugfs_create_file_size("amdgpu_smu_stb_dump",
3108                 S_IRUSR,
3109                 adev_to_drm(adev)->primary->debugfs_root,
3110                 adev,
3111                 &smu_stb_debugfs_fops,
3112                 smu->stb_context.stb_buf_size);
3113 #endif
3114 }
3115
3116 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3117 {
3118     int ret = 0;
3119
3120     if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3121         ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3122
3123     return ret;
3124 }
3125
3126 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3127 {
3128     int ret = 0;
3129
3130     if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3131         ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3132
3133     return ret;
3134 }