powerplay/smumgr/vegam_smumgr.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _VEGAM_SMUMANAGER_H
0025 #define _VEGAM_SMUMANAGER_H
0026
0027
0028 #include <pp_endian.h>
0029 #include "smu75_discrete.h"
0030 #include "smu7_smumgr.h"
0031
0032 #define SMC_RAM_END 0x40000
0033
0034 #define DPMTuning_Uphyst_Shift    0
0035 #define DPMTuning_Downhyst_Shift  8
0036 #define DPMTuning_Activity_Shift  16
0037
0038 #define GraphicsDPMTuning_VEGAM    0x001e6400
0039 #define MemoryDPMTuning_VEGAM      0x000f3c0a
0040 #define SclkDPMTuning_VEGAM        0x002d000a
0041 #define MclkDPMTuning_VEGAM        0x001f100a
0042
0043
0044 struct vegam_pt_defaults {
0045     uint8_t   SviLoadLineEn;
0046     uint8_t   SviLoadLineVddC;
0047     uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
0048     uint8_t   TDC_MAWt;
0049     uint8_t   TdcWaterfallCtl;
0050     uint8_t   DTEAmbientTempBase;
0051
0052     uint32_t  DisplayCac;
0053     uint32_t  BAPM_TEMP_GRADIENT;
0054     uint16_t  BAPMTI_R[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
0055     uint16_t  BAPMTI_RC[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
0056 };
0057
0058 struct vegam_range_table {
0059     uint32_t trans_lower_frequency; /* in 10khz */
0060     uint32_t trans_upper_frequency;
0061 };
0062
0063 struct vegam_smumgr {
0064     struct smu7_smumgr smu7_data;
0065     uint8_t protected_mode;
0066     SMU75_Discrete_DpmTable              smc_state_table;
0067     struct SMU75_Discrete_Ulv            ulv_setting;
0068     struct SMU75_Discrete_PmFuses  power_tune_table;
0069     struct vegam_range_table                range_table[NUM_SCLK_RANGE];
0070     const struct vegam_pt_defaults       *power_tune_defaults;
0071     uint32_t               bif_sclk_table[SMU75_MAX_LEVELS_LINK];
0072 };
0073
0074
0075 #endif