powerplay/smumgr/smumgr.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include <linux/delay.h>
0025 #include <linux/kernel.h>
0026 #include <linux/module.h>
0027 #include <linux/slab.h>
0028 #include <linux/types.h>
0029 #include <drm/amdgpu_drm.h>
0030 #include "smumgr.h"
0031
0032 MODULE_FIRMWARE("amdgpu/bonaire_smc.bin");
0033 MODULE_FIRMWARE("amdgpu/bonaire_k_smc.bin");
0034 MODULE_FIRMWARE("amdgpu/hawaii_smc.bin");
0035 MODULE_FIRMWARE("amdgpu/hawaii_k_smc.bin");
0036 MODULE_FIRMWARE("amdgpu/topaz_smc.bin");
0037 MODULE_FIRMWARE("amdgpu/topaz_k_smc.bin");
0038 MODULE_FIRMWARE("amdgpu/tonga_smc.bin");
0039 MODULE_FIRMWARE("amdgpu/tonga_k_smc.bin");
0040 MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
0041 MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
0042 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
0043 MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
0044 MODULE_FIRMWARE("amdgpu/polaris10_k2_smc.bin");
0045 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
0046 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
0047 MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
0048 MODULE_FIRMWARE("amdgpu/polaris11_k2_smc.bin");
0049 MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
0050 MODULE_FIRMWARE("amdgpu/polaris12_k_smc.bin");
0051 MODULE_FIRMWARE("amdgpu/vegam_smc.bin");
0052 MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
0053 MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
0054 MODULE_FIRMWARE("amdgpu/vega12_smc.bin");
0055 MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
0056
0057 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
0058 {
0059     if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable)
0060         return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
0061
0062     return 0;
0063 }
0064
0065 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
0066 {
0067     if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table)
0068         return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
0069
0070     return 0;
0071 }
0072
0073 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
0074 {
0075
0076     if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold)
0077         return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr);
0078
0079     return 0;
0080 }
0081
0082 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
0083 {
0084
0085     if (NULL != hwmgr->smumgr_funcs->update_smc_table)
0086         return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type);
0087
0088     return 0;
0089 }
0090
0091 uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
0092 {
0093     if (NULL != hwmgr->smumgr_funcs->get_offsetof)
0094         return hwmgr->smumgr_funcs->get_offsetof(type, member);
0095
0096     return 0;
0097 }
0098
0099 int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
0100 {
0101     if (NULL != hwmgr->smumgr_funcs->process_firmware_header)
0102         return hwmgr->smumgr_funcs->process_firmware_header(hwmgr);
0103     return 0;
0104 }
0105
0106 uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
0107 {
0108     if (NULL != hwmgr->smumgr_funcs->get_mac_definition)
0109         return hwmgr->smumgr_funcs->get_mac_definition(value);
0110
0111     return 0;
0112 }
0113
0114 int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
0115 {
0116     if (NULL != hwmgr->smumgr_funcs->download_pptable_settings)
0117         return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr,
0118                                     table);
0119     return 0;
0120 }
0121
0122 int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
0123 {
0124     if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings)
0125         return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr);
0126
0127     return 0;
0128 }
0129
0130 int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp)
0131 {
0132     int ret = 0;
0133
0134     if (hwmgr == NULL ||
0135         hwmgr->smumgr_funcs->send_msg_to_smc == NULL ||
0136         (resp && !hwmgr->smumgr_funcs->get_argument))
0137         return -EINVAL;
0138
0139     mutex_lock(&hwmgr->msg_lock);
0140
0141     ret = hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
0142     if (ret) {
0143         mutex_unlock(&hwmgr->msg_lock);
0144         return ret;
0145     }
0146
0147     if (resp)
0148         *resp = hwmgr->smumgr_funcs->get_argument(hwmgr);
0149
0150     mutex_unlock(&hwmgr->msg_lock);
0151
0152     return ret;
0153 }
0154
0155 int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
0156                     uint16_t msg,
0157                     uint32_t parameter,
0158                     uint32_t *resp)
0159 {
0160     int ret = 0;
0161
0162     if (hwmgr == NULL ||
0163         hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL ||
0164         (resp && !hwmgr->smumgr_funcs->get_argument))
0165         return -EINVAL;
0166
0167     mutex_lock(&hwmgr->msg_lock);
0168
0169     ret = hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter(
0170                         hwmgr, msg, parameter);
0171     if (ret) {
0172         mutex_unlock(&hwmgr->msg_lock);
0173         return ret;
0174     }
0175
0176     if (resp)
0177         *resp = hwmgr->smumgr_funcs->get_argument(hwmgr);
0178
0179     mutex_unlock(&hwmgr->msg_lock);
0180
0181     return ret;
0182 }
0183
0184 int smum_init_smc_table(struct pp_hwmgr *hwmgr)
0185 {
0186     if (NULL != hwmgr->smumgr_funcs->init_smc_table)
0187         return hwmgr->smumgr_funcs->init_smc_table(hwmgr);
0188
0189     return 0;
0190 }
0191
0192 int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
0193 {
0194     if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels)
0195         return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
0196
0197     return 0;
0198 }
0199
0200 int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
0201 {
0202     if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels)
0203         return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
0204
0205     return 0;
0206 }
0207
0208 /*this interface is needed by island ci/vi */
0209 int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
0210 {
0211     if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table)
0212         return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
0213
0214     return 0;
0215 }
0216
0217 bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
0218 {
0219     if (NULL != hwmgr->smumgr_funcs->is_dpm_running)
0220         return hwmgr->smumgr_funcs->is_dpm_running(hwmgr);
0221
0222     return true;
0223 }
0224
0225 bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
0226 {
0227     if (hwmgr->smumgr_funcs->is_hw_avfs_present)
0228         return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
0229
0230     return false;
0231 }
0232
0233 int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting)
0234 {
0235     if (hwmgr->smumgr_funcs->update_dpm_settings)
0236         return hwmgr->smumgr_funcs->update_dpm_settings(hwmgr, profile_setting);
0237
0238     return -EINVAL;
0239 }
0240
0241 int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
0242 {
0243     if (hwmgr->smumgr_funcs->smc_table_manager)
0244         return hwmgr->smumgr_funcs->smc_table_manager(hwmgr, table, table_id, rw);
0245
0246     return -EINVAL;
0247 }
0248
0249 int smum_stop_smc(struct pp_hwmgr *hwmgr)
0250 {
0251     if (hwmgr->smumgr_funcs->stop_smc)
0252         return hwmgr->smumgr_funcs->stop_smc(hwmgr);
0253
0254     return 0;
0255 }