powerplay/smumgr/smu7_smumgr.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _SMU7_SMUMANAGER_H
0025 #define _SMU7_SMUMANAGER_H
0026
0027
0028 #include <pp_endian.h>
0029
0030 #define SMC_RAM_END 0x40000
0031
0032 struct smu7_buffer_entry {
0033     uint32_t data_size;
0034     uint64_t mc_addr;
0035     void *kaddr;
0036     struct amdgpu_bo *handle;
0037 };
0038
0039 struct smu7_smumgr {
0040     struct smu7_buffer_entry smu_buffer;
0041     struct smu7_buffer_entry header_buffer;
0042     struct SMU_DRAMData_TOC *toc;
0043
0044     uint32_t                             soft_regs_start;
0045     uint32_t                             dpm_table_start;
0046     uint32_t                             mc_reg_table_start;
0047     uint32_t                             fan_table_start;
0048     uint32_t                             arb_table_start;
0049     uint32_t                             ulv_setting_starts;
0050     uint8_t                              security_hard_key;
0051     uint32_t                             acpi_optimization;
0052     uint32_t                             avfs_btc_param;
0053 };
0054
0055
0056 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
0057                 uint32_t *dest, uint32_t byte_count, uint32_t limit);
0058 int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
0059             const uint8_t *src, uint32_t byte_count, uint32_t limit);
0060 int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
0061 bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
0062 int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
0063 int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
0064                         uint32_t parameter);
0065 uint32_t smu7_get_argument(struct pp_hwmgr *hwmgr);
0066 int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
0067
0068 enum cgs_ucode_id smu7_convert_fw_type_to_cgs(uint32_t fw_type);
0069 int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
0070                         uint32_t *value, uint32_t limit);
0071 int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
0072                         uint32_t value, uint32_t limit);
0073
0074 int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
0075 int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
0076 int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
0077 int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
0078 int smu7_init(struct pp_hwmgr *hwmgr);
0079 int smu7_smu_fini(struct pp_hwmgr *hwmgr);
0080
0081 int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr);
0082
0083 #endif