powerplay/smumgr/polaris10_smumgr.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include <linux/pci.h>
0025
0026 #include "pp_debug.h"
0027 #include "smumgr.h"
0028 #include "smu74.h"
0029 #include "smu_ucode_xfer_vi.h"
0030 #include "polaris10_smumgr.h"
0031 #include "smu74_discrete.h"
0032 #include "smu/smu_7_1_3_d.h"
0033 #include "smu/smu_7_1_3_sh_mask.h"
0034 #include "gmc/gmc_8_1_d.h"
0035 #include "gmc/gmc_8_1_sh_mask.h"
0036 #include "oss/oss_3_0_d.h"
0037 #include "gca/gfx_8_0_d.h"
0038 #include "bif/bif_5_0_d.h"
0039 #include "bif/bif_5_0_sh_mask.h"
0040 #include "ppatomctrl.h"
0041 #include "cgs_common.h"
0042 #include "smu7_ppsmc.h"
0043 #include "smu7_smumgr.h"
0044
0045 #include "smu7_dyn_defaults.h"
0046
0047 #include "smu7_hwmgr.h"
0048 #include "hardwaremanager.h"
0049 #include "atombios.h"
0050 #include "pppcielanes.h"
0051
0052 #include "dce/dce_10_0_d.h"
0053 #include "dce/dce_10_0_sh_mask.h"
0054
0055 #define POLARIS10_SMC_SIZE 0x20000
0056 #define POWERTUNE_DEFAULT_SET_MAX    1
0057 #define VDDC_VDDCI_DELTA            200
0058 #define MC_CG_ARB_FREQ_F1           0x0b
0059
0060 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
0061     /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
0062      * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
0063     { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
0064     { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
0065     { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
0066 };
0067
0068 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
0069             {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
0070             {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
0071             {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
0072             {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
0073             {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
0074             {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
0075             {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
0076             {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
0077
0078 #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
0079
0080 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
0081     /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
0082     /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
0083     { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
0084     { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
0085     { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
0086     { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
0087     { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
0088     { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
0089     { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
0090     { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
0091 };
0092
0093 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
0094     0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
0095
0096 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
0097 {
0098     int result = 0;
0099     struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
0100
0101     if (0 != smu_data->avfs_btc_param) {
0102         if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
0103                     NULL)) {
0104             pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
0105             result = -1;
0106         }
0107     }
0108     if (smu_data->avfs_btc_param > 1) {
0109         /* Soft-Reset to reset the engine before loading uCode */
0110         /* halt */
0111         cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
0112         /* reset everything */
0113         cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
0114         cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
0115     }
0116     return result;
0117 }
0118
0119
0120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
0121 {
0122     uint32_t vr_config;
0123     uint32_t dpm_table_start;
0124
0125     uint16_t u16_boot_mvdd;
0126     uint32_t graphics_level_address, vr_config_address, graphics_level_size;
0127
0128     graphics_level_size = sizeof(avfs_graphics_level_polaris10);
0129     u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
0130
0131     PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
0132                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
0133                 &dpm_table_start, 0x40000),
0134             "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
0135             return -1);
0136
0137     /*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
0138     vr_config = 0x01000500; /* Real value:0x50001 */
0139
0140     vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
0141
0142     PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
0143                 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
0144             "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
0145             return -1);
0146
0147     graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
0148
0149     PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
0150                 (uint8_t *)(&avfs_graphics_level_polaris10),
0151                 graphics_level_size, 0x40000),
0152             "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
0153             return -1);
0154
0155     graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
0156
0157     PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
0158                 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
0159                 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
0160             return -1);
0161
0162     /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
0163
0164     graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
0165
0166     PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
0167             (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
0168             "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
0169             return -1);
0170
0171     return 0;
0172 }
0173
0174
0175 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
0176 {
0177     struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
0178
0179     if (!hwmgr->avfs_supported)
0180         return 0;
0181
0182     PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
0183         "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
0184         return -EINVAL);
0185
0186     if (smu_data->avfs_btc_param > 1) {
0187         pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
0188         PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
0189         "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
0190         return -EINVAL);
0191     }
0192
0193     PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
0194                 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
0195              return -EINVAL);
0196
0197     return 0;
0198 }
0199
0200 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
0201 {
0202     int result = 0;
0203
0204     /* Wait for smc boot up */
0205     /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
0206
0207     /* Assert reset */
0208     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0209                     SMC_SYSCON_RESET_CNTL, rst_reg, 1);
0210
0211     result = smu7_upload_smu_firmware_image(hwmgr);
0212     if (result != 0)
0213         return result;
0214
0215     /* Clear status */
0216     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
0217
0218     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0219                     SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
0220
0221     /* De-assert reset */
0222     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0223                     SMC_SYSCON_RESET_CNTL, rst_reg, 0);
0224
0225
0226     PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
0227
0228
0229     /* Call Test SMU message with 0x20000 offset to trigger SMU start */
0230     smu7_send_msg_to_smc_offset(hwmgr);
0231
0232     /* Wait done bit to be set */
0233     /* Check pass/failed indicator */
0234
0235     PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
0236
0237     if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0238                         SMU_STATUS, SMU_PASS))
0239         PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
0240
0241     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
0242
0243     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0244                     SMC_SYSCON_RESET_CNTL, rst_reg, 1);
0245
0246     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0247                     SMC_SYSCON_RESET_CNTL, rst_reg, 0);
0248
0249     /* Wait for firmware to initialize */
0250     PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
0251
0252     return result;
0253 }
0254
0255 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
0256 {
0257     int result = 0;
0258
0259     /* wait for smc boot up */
0260     PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
0261
0262     /* Clear firmware interrupt enable flag */
0263     /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
0264     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
0265                 ixFIRMWARE_FLAGS, 0);
0266
0267     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0268                     SMC_SYSCON_RESET_CNTL,
0269                     rst_reg, 1);
0270
0271     result = smu7_upload_smu_firmware_image(hwmgr);
0272     if (result != 0)
0273         return result;
0274
0275     /* Set smc instruct start point at 0x0 */
0276     smu7_program_jump_on_start(hwmgr);
0277
0278     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0279                     SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
0280
0281     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0282                     SMC_SYSCON_RESET_CNTL, rst_reg, 0);
0283
0284     /* Wait for firmware to initialize */
0285
0286     PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
0287                     FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
0288
0289     return result;
0290 }
0291
0292 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
0293 {
0294     int result = 0;
0295     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0296
0297     /* Only start SMC if SMC RAM is not running */
0298     if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
0299         smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
0300         smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
0301
0302         /* Check if SMU is running in protected mode */
0303         if (smu_data->protected_mode == 0)
0304             result = polaris10_start_smu_in_non_protection_mode(hwmgr);
0305         else
0306             result = polaris10_start_smu_in_protection_mode(hwmgr);
0307
0308         if (result != 0)
0309             PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
0310
0311         polaris10_avfs_event_mgr(hwmgr);
0312     }
0313
0314     /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
0315     smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
0316                     &(smu_data->smu7_data.soft_regs_start), 0x40000);
0317
0318     result = smu7_request_smu_load_fw(hwmgr);
0319
0320     return result;
0321 }
0322
0323 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
0324 {
0325     uint32_t efuse;
0326
0327     efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
0328     efuse &= 0x00000001;
0329     if (efuse)
0330         return true;
0331
0332     return false;
0333 }
0334
0335 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
0336 {
0337     struct polaris10_smumgr *smu_data;
0338
0339     smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
0340     if (smu_data == NULL)
0341         return -ENOMEM;
0342
0343     hwmgr->smu_backend = smu_data;
0344
0345     if (smu7_init(hwmgr)) {
0346         kfree(smu_data);
0347         return -EINVAL;
0348     }
0349
0350     return 0;
0351 }
0352
0353 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
0354         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
0355         uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
0356 {
0357     uint32_t i;
0358     uint16_t vddci;
0359     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0360
0361     *voltage = *mvdd = 0;
0362
0363     /* clock - voltage dependency table is empty table */
0364     if (dep_table->count == 0)
0365         return -EINVAL;
0366
0367     for (i = 0; i < dep_table->count; i++) {
0368         /* find first sclk bigger than request */
0369         if (dep_table->entries[i].clk >= clock) {
0370             *voltage |= (dep_table->entries[i].vddc *
0371                     VOLTAGE_SCALE) << VDDC_SHIFT;
0372             if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
0373                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
0374                         VOLTAGE_SCALE) << VDDCI_SHIFT;
0375             else if (dep_table->entries[i].vddci)
0376                 *voltage |= (dep_table->entries[i].vddci *
0377                         VOLTAGE_SCALE) << VDDCI_SHIFT;
0378             else {
0379                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
0380                         (dep_table->entries[i].vddc -
0381                                 (uint16_t)VDDC_VDDCI_DELTA));
0382                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
0383             }
0384
0385             if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
0386                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
0387                     VOLTAGE_SCALE;
0388             else if (dep_table->entries[i].mvdd)
0389                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
0390                     VOLTAGE_SCALE;
0391
0392             *voltage |= 1 << PHASES_SHIFT;
0393             return 0;
0394         }
0395     }
0396
0397     /* sclk is bigger than max sclk in the dependence table */
0398     *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
0399
0400     if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
0401         *voltage |= (data->vbios_boot_state.vddci_bootup_value *
0402                 VOLTAGE_SCALE) << VDDCI_SHIFT;
0403     else if (dep_table->entries[i-1].vddci) {
0404         *voltage |= (dep_table->entries[i - 1].vddci * VOLTAGE_SCALE) << VDDC_SHIFT;
0405     } else {
0406         vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
0407                 (dep_table->entries[i].vddc -
0408                         (uint16_t)VDDC_VDDCI_DELTA));
0409         *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
0410     }
0411
0412     if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
0413         *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
0414     else if (dep_table->entries[i].mvdd)
0415         *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
0416
0417     return 0;
0418 }
0419
0420 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
0421 {
0422     uint32_t tmp;
0423     tmp = raw_setting * 4096 / 100;
0424     return (uint16_t)tmp;
0425 }
0426
0427 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
0428 {
0429     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0430
0431     const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
0432     SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
0433     struct phm_ppt_v1_information *table_info =
0434             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0435     struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
0436     struct pp_advance_fan_control_parameters *fan_table =
0437             &hwmgr->thermal_controller.advanceFanControlParameters;
0438     int i, j, k;
0439     const uint16_t *pdef1;
0440     const uint16_t *pdef2;
0441
0442     table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
0443     table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
0444
0445     PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
0446                 "Target Operating Temp is out of Range!",
0447                 );
0448
0449     table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
0450             cac_dtp_table->usTargetOperatingTemp * 256);
0451     table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
0452             cac_dtp_table->usTemperatureLimitHotspot * 256);
0453     table->FanGainEdge = PP_HOST_TO_SMC_US(
0454             scale_fan_gain_settings(fan_table->usFanGainEdge));
0455     table->FanGainHotspot = PP_HOST_TO_SMC_US(
0456             scale_fan_gain_settings(fan_table->usFanGainHotspot));
0457
0458     pdef1 = defaults->BAPMTI_R;
0459     pdef2 = defaults->BAPMTI_RC;
0460
0461     for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
0462         for (j = 0; j < SMU74_DTE_SOURCES; j++) {
0463             for (k = 0; k < SMU74_DTE_SINKS; k++) {
0464                 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
0465                 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
0466                 pdef1++;
0467                 pdef2++;
0468             }
0469         }
0470     }
0471
0472     return 0;
0473 }
0474
0475 static void polaris10_populate_zero_rpm_parameters(struct pp_hwmgr *hwmgr)
0476 {
0477     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0478     SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
0479     uint16_t fan_stop_temp =
0480         ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature) << 8;
0481     uint16_t fan_start_temp =
0482         ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature) << 8;
0483
0484     if (hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM) {
0485         table->FanStartTemperature = PP_HOST_TO_SMC_US(fan_start_temp);
0486         table->FanStopTemperature = PP_HOST_TO_SMC_US(fan_stop_temp);
0487     }
0488 }
0489
0490 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
0491 {
0492     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0493     const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
0494
0495     smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
0496     smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
0497     smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
0498     smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
0499
0500     return 0;
0501 }
0502
0503 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
0504 {
0505     uint16_t tdc_limit;
0506     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0507     struct phm_ppt_v1_information *table_info =
0508             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0509     const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
0510
0511     tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
0512     smu_data->power_tune_table.TDC_VDDC_PkgLimit =
0513             CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
0514     smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
0515             defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
0516     smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
0517
0518     return 0;
0519 }
0520
0521 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
0522 {
0523     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0524     const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
0525     uint32_t temp;
0526
0527     if (smu7_read_smc_sram_dword(hwmgr,
0528             fuse_table_offset +
0529             offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
0530             (uint32_t *)&temp, SMC_RAM_END))
0531         PP_ASSERT_WITH_CODE(false,
0532                 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
0533                 return -EINVAL);
0534     else {
0535         smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
0536         smu_data->power_tune_table.LPMLTemperatureMin =
0537                 (uint8_t)((temp >> 16) & 0xff);
0538         smu_data->power_tune_table.LPMLTemperatureMax =
0539                 (uint8_t)((temp >> 8) & 0xff);
0540         smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
0541     }
0542     return 0;
0543 }
0544
0545 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
0546 {
0547     int i;
0548     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0549
0550     /* Currently not used. Set all to zero. */
0551     for (i = 0; i < 16; i++)
0552         smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
0553
0554     return 0;
0555 }
0556
0557 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
0558 {
0559     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0560
0561 /* TO DO move to hwmgr */
0562     if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
0563         || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
0564         hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
0565             hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
0566
0567     smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
0568                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
0569     return 0;
0570 }
0571
0572 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
0573 {
0574     int i;
0575     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0576
0577     /* Currently not used. Set all to zero. */
0578     for (i = 0; i < 16; i++)
0579         smu_data->power_tune_table.GnbLPML[i] = 0;
0580
0581     return 0;
0582 }
0583
0584 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
0585 {
0586     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0587     struct phm_ppt_v1_information *table_info =
0588             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0589     uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
0590     uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
0591     struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
0592
0593     hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
0594     lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
0595
0596     smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
0597             CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
0598     smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
0599             CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
0600
0601     return 0;
0602 }
0603
0604 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
0605 {
0606     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0607     uint32_t pm_fuse_table_offset;
0608
0609     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
0610             PHM_PlatformCaps_PowerContainment)) {
0611         if (smu7_read_smc_sram_dword(hwmgr,
0612                 SMU7_FIRMWARE_HEADER_LOCATION +
0613                 offsetof(SMU74_Firmware_Header, PmFuseTable),
0614                 &pm_fuse_table_offset, SMC_RAM_END))
0615             PP_ASSERT_WITH_CODE(false,
0616                     "Attempt to get pm_fuse_table_offset Failed!",
0617                     return -EINVAL);
0618
0619         if (polaris10_populate_svi_load_line(hwmgr))
0620             PP_ASSERT_WITH_CODE(false,
0621                     "Attempt to populate SviLoadLine Failed!",
0622                     return -EINVAL);
0623
0624         if (polaris10_populate_tdc_limit(hwmgr))
0625             PP_ASSERT_WITH_CODE(false,
0626                     "Attempt to populate TDCLimit Failed!", return -EINVAL);
0627
0628         if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
0629             PP_ASSERT_WITH_CODE(false,
0630                     "Attempt to populate TdcWaterfallCtl, "
0631                     "LPMLTemperature Min and Max Failed!",
0632                     return -EINVAL);
0633
0634         if (0 != polaris10_populate_temperature_scaler(hwmgr))
0635             PP_ASSERT_WITH_CODE(false,
0636                     "Attempt to populate LPMLTemperatureScaler Failed!",
0637                     return -EINVAL);
0638
0639         if (polaris10_populate_fuzzy_fan(hwmgr))
0640             PP_ASSERT_WITH_CODE(false,
0641                     "Attempt to populate Fuzzy Fan Control parameters Failed!",
0642                     return -EINVAL);
0643
0644         if (polaris10_populate_gnb_lpml(hwmgr))
0645             PP_ASSERT_WITH_CODE(false,
0646                     "Attempt to populate GnbLPML Failed!",
0647                     return -EINVAL);
0648
0649         if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
0650             PP_ASSERT_WITH_CODE(false,
0651                     "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
0652                     "Sidd Failed!", return -EINVAL);
0653
0654         if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
0655                 (uint8_t *)&smu_data->power_tune_table,
0656                 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
0657             PP_ASSERT_WITH_CODE(false,
0658                     "Attempt to download PmFuseTable Failed!",
0659                     return -EINVAL);
0660     }
0661     return 0;
0662 }
0663
0664 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
0665             SMU74_Discrete_DpmTable *table)
0666 {
0667     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0668     uint32_t count, level;
0669
0670     if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
0671         count = data->mvdd_voltage_table.count;
0672         if (count > SMU_MAX_SMIO_LEVELS)
0673             count = SMU_MAX_SMIO_LEVELS;
0674         for (level = 0; level < count; level++) {
0675             table->SmioTable2.Pattern[level].Voltage =
0676                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
0677             /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
0678             table->SmioTable2.Pattern[level].Smio =
0679                 (uint8_t) level;
0680             table->Smio[level] |=
0681                 data->mvdd_voltage_table.entries[level].smio_low;
0682         }
0683         table->SmioMask2 = data->mvdd_voltage_table.mask_low;
0684
0685         table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
0686     }
0687
0688     return 0;
0689 }
0690
0691 static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
0692                     struct SMU74_Discrete_DpmTable *table)
0693 {
0694     uint32_t count, level;
0695     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0696
0697     count = data->vddc_voltage_table.count;
0698
0699     if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
0700         if (count > SMU_MAX_SMIO_LEVELS)
0701             count = SMU_MAX_SMIO_LEVELS;
0702         for (level = 0; level < count; ++level) {
0703             table->SmioTable1.Pattern[level].Voltage =
0704                 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE);
0705             table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
0706
0707             table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low;
0708         }
0709
0710         table->SmioMask1 = data->vddc_voltage_table.mask_low;
0711     }
0712
0713     return 0;
0714 }
0715
0716 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
0717                     struct SMU74_Discrete_DpmTable *table)
0718 {
0719     uint32_t count, level;
0720     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0721
0722     count = data->vddci_voltage_table.count;
0723
0724     if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
0725         if (count > SMU_MAX_SMIO_LEVELS)
0726             count = SMU_MAX_SMIO_LEVELS;
0727         for (level = 0; level < count; ++level) {
0728             table->SmioTable1.Pattern[level].Voltage =
0729                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
0730             table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
0731
0732             table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
0733         }
0734
0735         table->SmioMask1 = data->vddci_voltage_table.mask_low;
0736     }
0737
0738     return 0;
0739 }
0740
0741 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
0742         struct SMU74_Discrete_DpmTable *table)
0743 {
0744     uint32_t count;
0745     uint8_t index;
0746     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0747     struct phm_ppt_v1_information *table_info =
0748             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0749     struct phm_ppt_v1_voltage_lookup_table *lookup_table =
0750             table_info->vddc_lookup_table;
0751     /* tables is already swapped, so in order to use the value from it,
0752      * we need to swap it back.
0753      * We are populating vddc CAC data to BapmVddc table
0754      * in split and merged mode
0755      */
0756     for (count = 0; count < lookup_table->count; count++) {
0757         index = phm_get_voltage_index(lookup_table,
0758                 data->vddc_voltage_table.entries[count].value);
0759         table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
0760         table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
0761         table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
0762     }
0763
0764     return 0;
0765 }
0766
0767 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
0768         struct SMU74_Discrete_DpmTable *table)
0769 {
0770     polaris10_populate_smc_vddc_table(hwmgr, table);
0771     polaris10_populate_smc_vddci_table(hwmgr, table);
0772     polaris10_populate_smc_mvdd_table(hwmgr, table);
0773     polaris10_populate_cac_table(hwmgr, table);
0774
0775     return 0;
0776 }
0777
0778 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
0779         struct SMU74_Discrete_Ulv *state)
0780 {
0781     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0782     struct phm_ppt_v1_information *table_info =
0783             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0784     struct amdgpu_device *adev = hwmgr->adev;
0785
0786     state->CcPwrDynRm = 0;
0787     state->CcPwrDynRm1 = 0;
0788
0789     state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
0790     state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
0791             VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
0792
0793     if ((hwmgr->chip_id == CHIP_POLARIS12) ||
0794         ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
0795         ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
0796         ASICID_IS_P30(adev->pdev->device, adev->pdev->revision) ||
0797         ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
0798         state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
0799     else
0800         state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
0801
0802     CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
0803     CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
0804     CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
0805
0806     return 0;
0807 }
0808
0809 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
0810         struct SMU74_Discrete_DpmTable *table)
0811 {
0812     return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
0813 }
0814
0815 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
0816         struct SMU74_Discrete_DpmTable *table)
0817 {
0818     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0819     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0820     struct smu7_dpm_table *dpm_table = &data->dpm_table;
0821     int i;
0822
0823     /* Index (dpm_table->pcie_speed_table.count)
0824      * is reserved for PCIE boot level. */
0825     for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
0826         table->LinkLevel[i].PcieGenSpeed  =
0827                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
0828         table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
0829                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
0830         table->LinkLevel[i].EnabledForActivity = 1;
0831         table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
0832         table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
0833         table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
0834     }
0835
0836     smu_data->smc_state_table.LinkLevelCount =
0837             (uint8_t)dpm_table->pcie_speed_table.count;
0838
0839 /* To Do move to hwmgr */
0840     data->dpm_level_enable_mask.pcie_dpm_enable_mask =
0841             phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
0842
0843     return 0;
0844 }
0845
0846
0847 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
0848                    SMU74_Discrete_DpmTable  *table)
0849 {
0850     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0851     uint32_t i, ref_clk;
0852
0853     struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
0854
0855     ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
0856
0857     if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
0858         for (i = 0; i < NUM_SCLK_RANGE; i++) {
0859             table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
0860             table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
0861             table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
0862
0863             table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
0864             table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
0865
0866             CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
0867             CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
0868             CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
0869         }
0870         return;
0871     }
0872
0873     for (i = 0; i < NUM_SCLK_RANGE; i++) {
0874         smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
0875         smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
0876
0877         table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
0878         table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
0879         table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
0880
0881         table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
0882         table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
0883
0884         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
0885         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
0886         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
0887     }
0888 }
0889
0890 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
0891         uint32_t clock, SMU_SclkSetting *sclk_setting)
0892 {
0893     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
0894     const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
0895     struct pp_atomctrl_clock_dividers_ai dividers;
0896     uint32_t ref_clock;
0897     uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
0898     uint8_t i;
0899     int result;
0900     uint64_t temp;
0901
0902     sclk_setting->SclkFrequency = clock;
0903     /* get the engine clock dividers for this clock value */
0904     result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
0905     if (result == 0) {
0906         sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
0907         sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
0908         sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
0909         sclk_setting->PllRange = dividers.ucSclkPllRange;
0910         sclk_setting->Sclk_slew_rate = 0x400;
0911         sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
0912         sclk_setting->Pcc_down_slew_rate = 0xffff;
0913         sclk_setting->SSc_En = dividers.ucSscEnable;
0914         sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
0915         sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
0916         sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
0917         return result;
0918     }
0919
0920     ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
0921
0922     for (i = 0; i < NUM_SCLK_RANGE; i++) {
0923         if (clock > smu_data->range_table[i].trans_lower_frequency
0924         && clock <= smu_data->range_table[i].trans_upper_frequency) {
0925             sclk_setting->PllRange = i;
0926             break;
0927         }
0928     }
0929
0930     sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
0931     temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
0932     temp <<= 0x10;
0933     do_div(temp, ref_clock);
0934     sclk_setting->Fcw_frac = temp & 0xffff;
0935
0936     pcc_target_percent = 10; /*  Hardcode 10% for now. */
0937     pcc_target_freq = clock - (clock * pcc_target_percent / 100);
0938     sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
0939
0940     ss_target_percent = 2; /*  Hardcode 2% for now. */
0941     sclk_setting->SSc_En = 0;
0942     if (ss_target_percent) {
0943         sclk_setting->SSc_En = 1;
0944         ss_target_freq = clock - (clock * ss_target_percent / 100);
0945         sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
0946         temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
0947         temp <<= 0x10;
0948         do_div(temp, ref_clock);
0949         sclk_setting->Fcw1_frac = temp & 0xffff;
0950     }
0951
0952     return 0;
0953 }
0954
0955 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
0956         uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
0957 {
0958     int result;
0959     /* PP_Clocks minClocks; */
0960     uint32_t mvdd;
0961     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0962     struct phm_ppt_v1_information *table_info =
0963             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0964     SMU_SclkSetting curr_sclk_setting = { 0 };
0965     phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
0966
0967     result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
0968
0969     if (hwmgr->od_enabled)
0970         vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
0971     else
0972         vdd_dep_table = table_info->vdd_dep_on_sclk;
0973
0974     /* populate graphics levels */
0975     result = polaris10_get_dependency_volt_by_clk(hwmgr,
0976             vdd_dep_table, clock,
0977             &level->MinVoltage, &mvdd);
0978
0979     PP_ASSERT_WITH_CODE((0 == result),
0980             "can not find VDDC voltage value for "
0981             "VDDC engine clock dependency table",
0982             return result);
0983     level->ActivityLevel = data->current_profile_setting.sclk_activity;
0984
0985     level->CcPwrDynRm = 0;
0986     level->CcPwrDynRm1 = 0;
0987     level->EnabledForActivity = 0;
0988     level->EnabledForThrottle = 1;
0989     level->UpHyst = data->current_profile_setting.sclk_up_hyst;
0990     level->DownHyst = data->current_profile_setting.sclk_down_hyst;
0991     level->VoltageDownHyst = 0;
0992     level->PowerThrottle = 0;
0993     data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
0994
0995     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
0996         level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
0997                                 hwmgr->display_config->min_core_set_clock_in_sr);
0998
0999     /* Default to slow, highest DPM level will be
1000      * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1001      */
1002     if (data->update_up_hyst)
1003         level->UpHyst = (uint8_t)data->up_hyst;
1004     if (data->update_down_hyst)
1005         level->DownHyst = (uint8_t)data->down_hyst;
1006
1007     level->SclkSetting = curr_sclk_setting;
1008
1009     CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1010     CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1011     CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1012     CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1013     CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1014     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1015     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1016     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1017     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1018     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1019     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1020     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1021     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1022     CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1023     return 0;
1024 }
1025
1026 static void polaris10_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr)
1027 {
1028     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1029     SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1030     uint8_t shared_rail;
1031
1032     if (!atomctrl_get_vddc_shared_railinfo(hwmgr, &shared_rail))
1033         table->SharedRails = shared_rail;
1034 }
1035
1036 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1037 {
1038     struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1039     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1040     struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1041     struct phm_ppt_v1_information *table_info =
1042             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1043     struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1044     uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1045     int result = 0;
1046     uint32_t array = smu_data->smu7_data.dpm_table_start +
1047             offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1048     uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1049             SMU74_MAX_LEVELS_GRAPHICS;
1050     struct SMU74_Discrete_GraphicsLevel *levels =
1051             smu_data->smc_state_table.GraphicsLevel;
1052     uint32_t i, max_entry;
1053     uint8_t hightest_pcie_level_enabled = 0,
1054         lowest_pcie_level_enabled = 0,
1055         mid_pcie_level_enabled = 0,
1056         count = 0;
1057     struct amdgpu_device *adev = hwmgr->adev;
1058     pp_atomctrl_clock_dividers_vi dividers;
1059     uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;
1060
1061     if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1062         ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
1063         polaris10_get_vddc_shared_railinfo(hwmgr);
1064
1065     polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1066
1067     for (i = 0; i < dpm_table->sclk_table.count; i++) {
1068
1069         result = polaris10_populate_single_graphic_level(hwmgr,
1070                 dpm_table->sclk_table.dpm_levels[i].value,
1071                 &(smu_data->smc_state_table.GraphicsLevel[i]));
1072         if (result)
1073             return result;
1074
1075         /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1076         if (i > 1)
1077             levels[i].DeepSleepDivId = 0;
1078     }
1079     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1080                     PHM_PlatformCaps_SPLLShutdownSupport)) {
1081         smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1082         if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) {
1083             result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1084                     dpm_table->sclk_table.dpm_levels[0].value,
1085                     &dividers);
1086             PP_ASSERT_WITH_CODE((0 == result),
1087                     "can not find divide id for sclk",
1088                     return result);
1089             smum_send_msg_to_smc_with_parameter(hwmgr,
1090                     PPSMC_MSG_SetGpuPllDfsForSclk,
1091                     dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?
1092                     dividers.pll_post_divider - 1 : dividers.pll_post_divider,
1093                     NULL);
1094         }
1095     }
1096
1097     smu_data->smc_state_table.GraphicsDpmLevelCount =
1098             (uint8_t)dpm_table->sclk_table.count;
1099     hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1100             phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1101
1102     for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++)
1103         smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity =
1104             (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;
1105
1106     if (pcie_table != NULL) {
1107         PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1108                 "There must be 1 or more PCIE levels defined in PPTable.",
1109                 return -EINVAL);
1110         max_entry = pcie_entry_cnt - 1;
1111         for (i = 0; i < dpm_table->sclk_table.count; i++)
1112             levels[i].pcieDpmLevel =
1113                     (uint8_t) ((i < max_entry) ? i : max_entry);
1114     } else {
1115         while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1116                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1117                         (1 << (hightest_pcie_level_enabled + 1))) != 0))
1118             hightest_pcie_level_enabled++;
1119
1120         while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1121                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1122                         (1 << lowest_pcie_level_enabled)) == 0))
1123             lowest_pcie_level_enabled++;
1124
1125         while ((count < hightest_pcie_level_enabled) &&
1126                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1127                         (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1128             count++;
1129
1130         mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1131                 hightest_pcie_level_enabled ?
1132                         (lowest_pcie_level_enabled + 1 + count) :
1133                         hightest_pcie_level_enabled;
1134
1135         /* set pcieDpmLevel to hightest_pcie_level_enabled */
1136         for (i = 2; i < dpm_table->sclk_table.count; i++)
1137             levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1138
1139         /* set pcieDpmLevel to lowest_pcie_level_enabled */
1140         levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1141
1142         /* set pcieDpmLevel to mid_pcie_level_enabled */
1143         levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1144     }
1145     /* level count will send to smc once at init smc table and never change */
1146     result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1147             (uint32_t)array_size, SMC_RAM_END);
1148
1149     return result;
1150 }
1151
1152
1153 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1154         uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1155 {
1156     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1157     struct phm_ppt_v1_information *table_info =
1158             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1159     int result = 0;
1160     uint32_t mclk_stutter_mode_threshold = 40000;
1161     phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1162
1163
1164     if (hwmgr->od_enabled)
1165         vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1166     else
1167         vdd_dep_table = table_info->vdd_dep_on_mclk;
1168
1169     if (vdd_dep_table) {
1170         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1171                 vdd_dep_table, clock,
1172                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1173         PP_ASSERT_WITH_CODE((0 == result),
1174                 "can not find MinVddc voltage value from memory "
1175                 "VDDC voltage dependency table", return result);
1176     }
1177
1178     mem_level->MclkFrequency = clock;
1179     mem_level->EnabledForThrottle = 1;
1180     mem_level->EnabledForActivity = 0;
1181     mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1182     mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1183     mem_level->VoltageDownHyst = 0;
1184     mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1185     mem_level->StutterEnable = false;
1186     mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1187
1188     data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1189     data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1190
1191     if (mclk_stutter_mode_threshold &&
1192         (clock <= mclk_stutter_mode_threshold) &&
1193         (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1194                 STUTTER_ENABLE) & 0x1) &&
1195         (data->display_timing.num_existing_displays <= 2) &&
1196         data->display_timing.num_existing_displays)
1197         mem_level->StutterEnable = true;
1198
1199     if (!result) {
1200         CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1201         CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1202         CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1203         CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1204     }
1205     return result;
1206 }
1207
1208 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1209 {
1210     struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1211     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1212     struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1213     int result;
1214     /* populate MCLK dpm table to SMU7 */
1215     uint32_t array = smu_data->smu7_data.dpm_table_start +
1216             offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1217     uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1218             SMU74_MAX_LEVELS_MEMORY;
1219     struct SMU74_Discrete_MemoryLevel *levels =
1220             smu_data->smc_state_table.MemoryLevel;
1221     uint32_t i;
1222
1223     for (i = 0; i < dpm_table->mclk_table.count; i++) {
1224         PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1225                 "can not populate memory level as memory clock is zero",
1226                 return -EINVAL);
1227         result = polaris10_populate_single_memory_level(hwmgr,
1228                 dpm_table->mclk_table.dpm_levels[i].value,
1229                 &levels[i]);
1230         if (i == dpm_table->mclk_table.count - 1)
1231             levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1232         if (result)
1233             return result;
1234     }
1235
1236     smu_data->smc_state_table.MemoryDpmLevelCount =
1237             (uint8_t)dpm_table->mclk_table.count;
1238     hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1239             phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1240
1241     for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++)
1242         smu_data->smc_state_table.MemoryLevel[i].EnabledForActivity =
1243             (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i;
1244
1245     /* level count will send to smc once at init smc table and never change */
1246     result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1247             (uint32_t)array_size, SMC_RAM_END);
1248
1249     return result;
1250 }
1251
1252 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1253         uint32_t mclk, SMIO_Pattern *smio_pat)
1254 {
1255     const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1256     struct phm_ppt_v1_information *table_info =
1257             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1258     uint32_t i = 0;
1259
1260     if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1261         /* find mvdd value which clock is more than request */
1262         for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1263             if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1264                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1265                 break;
1266             }
1267         }
1268         PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1269                 "MVDD Voltage is outside the supported range.",
1270                 return -EINVAL);
1271     } else
1272         return -EINVAL;
1273
1274     return 0;
1275 }
1276
1277 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1278         SMU74_Discrete_DpmTable *table)
1279 {
1280     int result = 0;
1281     uint32_t sclk_frequency;
1282     const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1283     struct phm_ppt_v1_information *table_info =
1284             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1285     SMIO_Pattern vol_level;
1286     uint32_t mvdd;
1287
1288     table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1289
1290     /* Get MinVoltage and Frequency from DPM0,
1291      * already converted to SMC_UL */
1292     sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1293     result = polaris10_get_dependency_volt_by_clk(hwmgr,
1294             table_info->vdd_dep_on_sclk,
1295             sclk_frequency,
1296             &table->ACPILevel.MinVoltage, &mvdd);
1297     PP_ASSERT_WITH_CODE((0 == result),
1298             "Cannot find ACPI VDDC voltage value "
1299             "in Clock Dependency Table",
1300             );
1301
1302     result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1303     PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1304
1305     table->ACPILevel.DeepSleepDivId = 0;
1306     table->ACPILevel.CcPwrDynRm = 0;
1307     table->ACPILevel.CcPwrDynRm1 = 0;
1308
1309     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1310     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1311     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1312     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1313
1314     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1315     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1316     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1317     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1318     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1319     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1320     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1321     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1322     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1323     CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1324
1325
1326     /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1327     table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1328     result = polaris10_get_dependency_volt_by_clk(hwmgr,
1329             table_info->vdd_dep_on_mclk,
1330             table->MemoryACPILevel.MclkFrequency,
1331             &table->MemoryACPILevel.MinVoltage, &mvdd);
1332     PP_ASSERT_WITH_CODE((0 == result),
1333             "Cannot find ACPI VDDCI voltage value "
1334             "in Clock Dependency Table",
1335             );
1336
1337     if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1338             (data->mclk_dpm_key_disabled)))
1339         polaris10_populate_mvdd_value(hwmgr,
1340                 data->dpm_table.mclk_table.dpm_levels[0].value,
1341                 &vol_level);
1342
1343     if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1344         table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1345     else
1346         table->MemoryACPILevel.MinMvdd = 0;
1347
1348     table->MemoryACPILevel.StutterEnable = false;
1349
1350     table->MemoryACPILevel.EnabledForThrottle = 0;
1351     table->MemoryACPILevel.EnabledForActivity = 0;
1352     table->MemoryACPILevel.UpHyst = 0;
1353     table->MemoryACPILevel.DownHyst = 100;
1354     table->MemoryACPILevel.VoltageDownHyst = 0;
1355     /* To align with the settings from other OSes */
1356     table->MemoryACPILevel.ActivityLevel =
1357             PP_HOST_TO_SMC_US(data->current_profile_setting.sclk_activity);
1358
1359     CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1360     CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1361
1362     return result;
1363 }
1364
1365 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1366         SMU74_Discrete_DpmTable *table)
1367 {
1368     int result = -EINVAL;
1369     uint8_t count;
1370     struct pp_atomctrl_clock_dividers_vi dividers;
1371     struct phm_ppt_v1_information *table_info =
1372             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1373     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1374             table_info->mm_dep_table;
1375     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1376     uint32_t vddci;
1377
1378     table->VceLevelCount = (uint8_t)(mm_table->count);
1379     table->VceBootLevel = 0;
1380
1381     for (count = 0; count < table->VceLevelCount; count++) {
1382         table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1383         table->VceLevel[count].MinVoltage = 0;
1384         table->VceLevel[count].MinVoltage |=
1385                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1386
1387         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1388             vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1389                         mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1390         else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1391             vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1392         else
1393             vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1394
1395
1396         table->VceLevel[count].MinVoltage |=
1397                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1398         table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1399
1400         /*retrieve divider value for VBIOS */
1401         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1402                 table->VceLevel[count].Frequency, &dividers);
1403         PP_ASSERT_WITH_CODE((0 == result),
1404                 "can not find divide id for VCE engine clock",
1405                 return result);
1406
1407         table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1408
1409         CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1410         CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1411     }
1412     return result;
1413 }
1414
1415 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1416         SMU74_Discrete_DpmTable *table)
1417 {
1418     int result = -EINVAL;
1419     uint8_t count;
1420     struct pp_atomctrl_clock_dividers_vi dividers;
1421     struct phm_ppt_v1_information *table_info =
1422             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1423     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1424             table_info->mm_dep_table;
1425     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1426     uint32_t vddci;
1427
1428     table->SamuLevelCount = (uint8_t)(mm_table->count);
1429     table->SamuBootLevel = 0;
1430
1431     for (count = 0; count < table->SamuLevelCount; count++) {
1432         table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1433         table->SamuLevel[count].MinVoltage |=
1434                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1435
1436         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1437             vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1438                         mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1439         else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1440             vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1441         else
1442             vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1443
1444
1445         table->SamuLevel[count].MinVoltage |=
1446                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1447         table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1448
1449         /*retrieve divider value for VBIOS */
1450         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1451                 table->SamuLevel[count].Frequency, &dividers);
1452         PP_ASSERT_WITH_CODE((0 == result),
1453                 "can not find divide id for VCE engine clock",
1454                 return result);
1455
1456         table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1457
1458         CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1459         CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1460     }
1461     return result;
1462 }
1463
1464 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1465         int32_t eng_clock, int32_t mem_clock,
1466         SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1467 {
1468     uint32_t dram_timing;
1469     uint32_t dram_timing2;
1470     uint32_t burst_time;
1471     int result;
1472
1473     result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1474             eng_clock, mem_clock);
1475     PP_ASSERT_WITH_CODE(result == 0,
1476             "Error calling VBIOS to set DRAM_TIMING.", return result);
1477
1478     dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1479     dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1480     burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1481
1482
1483     arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1484     arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1485     arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1486
1487     return 0;
1488 }
1489
1490 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1491 {
1492     struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1493     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1494     struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1495     uint32_t i, j;
1496     int result = 0;
1497
1498     for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1499         for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1500             result = polaris10_populate_memory_timing_parameters(hwmgr,
1501                     hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1502                     hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1503                     &arb_regs.entries[i][j]);
1504             if (result == 0 && i == 0)
1505                 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1506             if (result != 0)
1507                 return result;
1508         }
1509     }
1510
1511     result = smu7_copy_bytes_to_smc(
1512             hwmgr,
1513             smu_data->smu7_data.arb_table_start,
1514             (uint8_t *)&arb_regs,
1515             sizeof(SMU74_Discrete_MCArbDramTimingTable),
1516             SMC_RAM_END);
1517     return result;
1518 }
1519
1520 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1521         struct SMU74_Discrete_DpmTable *table)
1522 {
1523     int result = -EINVAL;
1524     uint8_t count;
1525     struct pp_atomctrl_clock_dividers_vi dividers;
1526     struct phm_ppt_v1_information *table_info =
1527             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1528     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1529             table_info->mm_dep_table;
1530     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1531     uint32_t vddci;
1532
1533     table->UvdLevelCount = (uint8_t)(mm_table->count);
1534     table->UvdBootLevel = 0;
1535
1536     for (count = 0; count < table->UvdLevelCount; count++) {
1537         table->UvdLevel[count].MinVoltage = 0;
1538         table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1539         table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1540         table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1541                 VOLTAGE_SCALE) << VDDC_SHIFT;
1542
1543         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1544             vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1545                         mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1546         else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1547             vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1548         else
1549             vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1550
1551         table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1552         table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1553
1554         /* retrieve divider value for VBIOS */
1555         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1556                 table->UvdLevel[count].VclkFrequency, &dividers);
1557         PP_ASSERT_WITH_CODE((0 == result),
1558                 "can not find divide id for Vclk clock", return result);
1559
1560         table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1561
1562         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1563                 table->UvdLevel[count].DclkFrequency, &dividers);
1564         PP_ASSERT_WITH_CODE((0 == result),
1565                 "can not find divide id for Dclk clock", return result);
1566
1567         table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1568
1569         CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1570         CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1571         CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1572     }
1573
1574     return result;
1575 }
1576
1577 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1578         struct SMU74_Discrete_DpmTable *table)
1579 {
1580     int result = 0;
1581     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1582
1583     table->GraphicsBootLevel = 0;
1584     table->MemoryBootLevel = 0;
1585
1586     /* find boot level from dpm table */
1587     result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1588             data->vbios_boot_state.sclk_bootup_value,
1589             (uint32_t *)&(table->GraphicsBootLevel));
1590     if (result) {
1591         table->GraphicsBootLevel = 0;
1592         result = 0;
1593     }
1594
1595     result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1596             data->vbios_boot_state.mclk_bootup_value,
1597             (uint32_t *)&(table->MemoryBootLevel));
1598     if (result) {
1599         table->MemoryBootLevel = 0;
1600         result = 0;
1601     }
1602
1603     table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1604             VOLTAGE_SCALE;
1605     table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1606             VOLTAGE_SCALE;
1607     table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1608             VOLTAGE_SCALE;
1609
1610     CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1611     CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1612     CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1613
1614     return 0;
1615 }
1616
1617 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1618 {
1619     struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1620     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1621     struct phm_ppt_v1_information *table_info =
1622             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1623     uint8_t count, level;
1624
1625     count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1626
1627     for (level = 0; level < count; level++) {
1628         if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1629                 hw_data->vbios_boot_state.sclk_bootup_value) {
1630             smu_data->smc_state_table.GraphicsBootLevel = level;
1631             break;
1632         }
1633     }
1634
1635     count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1636     for (level = 0; level < count; level++) {
1637         if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1638                 hw_data->vbios_boot_state.mclk_bootup_value) {
1639             smu_data->smc_state_table.MemoryBootLevel = level;
1640             break;
1641         }
1642     }
1643
1644     return 0;
1645 }
1646
1647 #define STRAP_ASIC_RO_LSB    2168
1648 #define STRAP_ASIC_RO_MSB    2175
1649
1650 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1651 {
1652     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1653     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1654     struct phm_ppt_v1_information *table_info =
1655             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1656     struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1657             table_info->vdd_dep_on_sclk;
1658     uint32_t ro, efuse, volt_without_cks, volt_with_cks, value;
1659     uint8_t i, stretch_amount, volt_offset = 0;
1660
1661     stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1662
1663     /* Read SMU_Eefuse to read and calculate RO and determine
1664      * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1665      */
1666     atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, &efuse);
1667     ro = ((efuse * (data->ro_range_maximum - data->ro_range_minimum)) / 255) +
1668         data->ro_range_minimum;
1669
1670     /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1671     for (i = 0; i < sclk_table->count; i++) {
1672         smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1673                 sclk_table->entries[i].cks_enable << i;
1674         if (hwmgr->chip_id == CHIP_POLARIS10) {
1675             volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1676                         (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1677             volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1678                     (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1679         } else {
1680             volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1681                         (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1682             volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1683                     (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1684         }
1685
1686         if (volt_without_cks >= volt_with_cks)
1687             volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1688                     sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1689
1690         smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1691     }
1692
1693     smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1694
1695     /* Populate CKS Lookup Table */
1696     if (stretch_amount == 0 || stretch_amount > 5) {
1697         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1698                 PHM_PlatformCaps_ClockStretcher);
1699         PP_ASSERT_WITH_CODE(false,
1700                 "Stretch Amount in PPTable not supported",
1701                 return -EINVAL);
1702     }
1703
1704     value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1705     value &= 0xFFFFFFFE;
1706     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1707
1708     return 0;
1709 }
1710
1711 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1712         struct SMU74_Discrete_DpmTable *table)
1713 {
1714     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1715     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1716     uint16_t config;
1717
1718     config = VR_MERGED_WITH_VDDC;
1719     table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1720
1721     /* Set Vddc Voltage Controller */
1722     if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1723         config = VR_SVI2_PLANE_1;
1724         table->VRConfig |= config;
1725     } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
1726         config = VR_SMIO_PATTERN_1;
1727         table->VRConfig |= config;
1728     } else {
1729         PP_ASSERT_WITH_CODE(false,
1730                 "VDDC should be on SVI2 control in merged mode!",
1731                 );
1732     }
1733     /* Set Vddci Voltage Controller */
1734     if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1735         config = VR_SVI2_PLANE_2;  /* only in merged mode */
1736         table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1737     } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1738         config = VR_SMIO_PATTERN_1;
1739         table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1740     } else {
1741         config = VR_STATIC_VOLTAGE;
1742         table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1743     }
1744     /* Set Mvdd Voltage Controller */
1745     if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1746         if (config != VR_SVI2_PLANE_2) {
1747             config = VR_SVI2_PLANE_2;
1748             table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1749             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1750                 offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1751         } else {
1752             config = VR_STATIC_VOLTAGE;
1753             table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1754         }
1755     } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1756         config = VR_SMIO_PATTERN_2;
1757         table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1758         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1759             offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1760     } else {
1761         config = VR_STATIC_VOLTAGE;
1762         table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1763     }
1764
1765     return 0;
1766 }
1767
1768
1769 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1770 {
1771     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1772     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1773     struct amdgpu_device *adev = hwmgr->adev;
1774
1775     SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
1776     int result = 0;
1777     struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1778     AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1779     AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1780     uint32_t tmp, i;
1781
1782     struct phm_ppt_v1_information *table_info =
1783             (struct phm_ppt_v1_information *)hwmgr->pptable;
1784     struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1785             table_info->vdd_dep_on_sclk;
1786
1787
1788     if (!hwmgr->avfs_supported)
1789         return 0;
1790
1791
1792     if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
1793         hwmgr->avfs_supported = 0;
1794         return 0;
1795     }
1796
1797     result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1798
1799     if (0 == result) {
1800         if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision) ||
1801             ((hwmgr->chip_id == CHIP_POLARIS12) && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) ||
1802             ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)) {
1803             avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1804             if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1805                 (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1806                 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1807                     (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1808                     (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1809                     (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1810                     (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1811                     (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1812                     avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF718F1D4;
1813                     avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x323FD;
1814                     avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0x1E455;
1815                     avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1816                     avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1817                     avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x23;
1818                 }
1819             } else if (hwmgr->chip_id == CHIP_POLARIS12 && !ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
1820                 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF6B024DD;
1821                 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x3005E;
1822                 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0x18A5F;
1823                 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1824                 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1825                 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x3B;
1826             } else if (ASICID_IS_P20(adev->pdev->device, adev->pdev->revision)) {
1827                 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF843B66B;
1828                 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x59CB5;
1829                 avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0xFFFF287F;
1830                 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1831                 avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1832                 avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x58;
1833             }
1834         }
1835     }
1836
1837     if (0 == result) {
1838         table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1839         table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1840         table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1841         table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1842         table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1843         table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1844         table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1845         table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1846         table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1847         table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1848         table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1849         table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1850         table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1851         table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1852         table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1853         table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1854         table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1855         AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1856         AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1857         AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1858         AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1859         AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1860         AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1861         AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1862
1863         for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1864             AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1865             AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1866         }
1867
1868         result = smu7_read_smc_sram_dword(hwmgr,
1869                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1870                 &tmp, SMC_RAM_END);
1871
1872         smu7_copy_bytes_to_smc(hwmgr,
1873                     tmp,
1874                     (uint8_t *)&AVFS_meanNsigma,
1875                     sizeof(AVFS_meanNsigma_t),
1876                     SMC_RAM_END);
1877
1878         result = smu7_read_smc_sram_dword(hwmgr,
1879                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1880                 &tmp, SMC_RAM_END);
1881         smu7_copy_bytes_to_smc(hwmgr,
1882                     tmp,
1883                     (uint8_t *)&AVFS_SclkOffset,
1884                     sizeof(AVFS_Sclk_Offset_t),
1885                     SMC_RAM_END);
1886
1887         data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1888                         (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1889                         (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1890                         (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1891         data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1892     }
1893     return result;
1894 }
1895
1896 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1897 {
1898     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1899     struct  phm_ppt_v1_information *table_info =
1900             (struct  phm_ppt_v1_information *)(hwmgr->pptable);
1901
1902     if (table_info &&
1903             table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1904             table_info->cac_dtp_table->usPowerTuneDataSetID)
1905         smu_data->power_tune_defaults =
1906                 &polaris10_power_tune_data_set_array
1907                 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1908     else
1909         smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1910
1911 }
1912
1913 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1914 {
1915     int result;
1916     struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1917     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1918
1919     struct phm_ppt_v1_information *table_info =
1920             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1921     struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1922     uint8_t i;
1923     struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1924     pp_atomctrl_clock_dividers_vi dividers;
1925     struct phm_ppt_v1_gpio_table *gpio_table = table_info->gpio_table;
1926
1927     polaris10_initialize_power_tune_defaults(hwmgr);
1928
1929     if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1930         polaris10_populate_smc_voltage_tables(hwmgr, table);
1931
1932     table->SystemFlags = 0;
1933     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1934             PHM_PlatformCaps_AutomaticDCTransition))
1935         table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1936
1937     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1938             PHM_PlatformCaps_StepVddc))
1939         table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1940
1941     if (hw_data->is_memory_gddr5)
1942         table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1943
1944     if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1945         result = polaris10_populate_ulv_state(hwmgr, table);
1946         PP_ASSERT_WITH_CODE(0 == result,
1947                 "Failed to initialize ULV state!", return result);
1948         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1949                 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1950     }
1951
1952     result = polaris10_populate_smc_link_level(hwmgr, table);
1953     PP_ASSERT_WITH_CODE(0 == result,
1954             "Failed to initialize Link Level!", return result);
1955
1956     result = polaris10_populate_all_graphic_levels(hwmgr);
1957     PP_ASSERT_WITH_CODE(0 == result,
1958             "Failed to initialize Graphics Level!", return result);
1959
1960     result = polaris10_populate_all_memory_levels(hwmgr);
1961     PP_ASSERT_WITH_CODE(0 == result,
1962             "Failed to initialize Memory Level!", return result);
1963
1964     result = polaris10_populate_smc_acpi_level(hwmgr, table);
1965     PP_ASSERT_WITH_CODE(0 == result,
1966             "Failed to initialize ACPI Level!", return result);
1967
1968     result = polaris10_populate_smc_vce_level(hwmgr, table);
1969     PP_ASSERT_WITH_CODE(0 == result,
1970             "Failed to initialize VCE Level!", return result);
1971
1972     result = polaris10_populate_smc_samu_level(hwmgr, table);
1973     PP_ASSERT_WITH_CODE(0 == result,
1974             "Failed to initialize SAMU Level!", return result);
1975
1976     /* Since only the initial state is completely set up at this point
1977      * (the other states are just copies of the boot state) we only
1978      * need to populate the  ARB settings for the initial state.
1979      */
1980     result = polaris10_program_memory_timing_parameters(hwmgr);
1981     PP_ASSERT_WITH_CODE(0 == result,
1982             "Failed to Write ARB settings for the initial state.", return result);
1983
1984     result = polaris10_populate_smc_uvd_level(hwmgr, table);
1985     PP_ASSERT_WITH_CODE(0 == result,
1986             "Failed to initialize UVD Level!", return result);
1987
1988     result = polaris10_populate_smc_boot_level(hwmgr, table);
1989     PP_ASSERT_WITH_CODE(0 == result,
1990             "Failed to initialize Boot Level!", return result);
1991
1992     result = polaris10_populate_smc_initailial_state(hwmgr);
1993     PP_ASSERT_WITH_CODE(0 == result,
1994             "Failed to initialize Boot State!", return result);
1995
1996     result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1997     PP_ASSERT_WITH_CODE(0 == result,
1998             "Failed to populate BAPM Parameters!", return result);
1999
2000     polaris10_populate_zero_rpm_parameters(hwmgr);
2001
2002     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2003             PHM_PlatformCaps_ClockStretcher)) {
2004         result = polaris10_populate_clock_stretcher_data_table(hwmgr);
2005         PP_ASSERT_WITH_CODE(0 == result,
2006                 "Failed to populate Clock Stretcher Data Table!",
2007                 return result);
2008     }
2009
2010     result = polaris10_populate_avfs_parameters(hwmgr);
2011     PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
2012
2013     table->CurrSclkPllRange = 0xff;
2014     table->GraphicsVoltageChangeEnable  = 1;
2015     table->GraphicsThermThrottleEnable  = 1;
2016     table->GraphicsInterval = 1;
2017     table->VoltageInterval  = 1;
2018     table->ThermalInterval  = 1;
2019     table->TemperatureLimitHigh =
2020             table_info->cac_dtp_table->usTargetOperatingTemp *
2021             SMU7_Q88_FORMAT_CONVERSION_UNIT;
2022     table->TemperatureLimitLow  =
2023             (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2024             SMU7_Q88_FORMAT_CONVERSION_UNIT;
2025     table->MemoryVoltageChangeEnable = 1;
2026     table->MemoryInterval = 1;
2027     table->VoltageResponseTime = 0;
2028     table->PhaseResponseTime = 0;
2029     table->MemoryThermThrottleEnable = 1;
2030     table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
2031     table->PCIeGenInterval = 1;
2032     table->VRConfig = 0;
2033
2034     result = polaris10_populate_vr_config(hwmgr, table);
2035     PP_ASSERT_WITH_CODE(0 == result,
2036             "Failed to populate VRConfig setting!", return result);
2037     hw_data->vr_config = table->VRConfig;
2038     table->ThermGpio = 17;
2039     table->SclkStepSize = 0x4000;
2040
2041     if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2042         table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2043         if (gpio_table)
2044             table->VRHotLevel = gpio_table->vrhot_triggered_sclk_dpm_index;
2045     } else {
2046         table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2047         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2048                 PHM_PlatformCaps_RegulatorHot);
2049     }
2050
2051     if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2052             &gpio_pin)) {
2053         table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2054         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2055                 PHM_PlatformCaps_AutomaticDCTransition) &&
2056             !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
2057             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2058                     PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2059     } else {
2060         table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2061         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2062                 PHM_PlatformCaps_AutomaticDCTransition);
2063     }
2064
2065     /* Thermal Output GPIO */
2066     if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2067             &gpio_pin)) {
2068         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2069                 PHM_PlatformCaps_ThermalOutGPIO);
2070
2071         table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2072
2073         /* For porlarity read GPIOPAD_A with assigned Gpio pin
2074          * since VBIOS will program this register to set 'inactive state',
2075          * driver can then determine 'active state' from this and
2076          * program SMU with correct polarity
2077          */
2078         table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2079                     & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2080         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2081
2082         /* if required, combine VRHot/PCC with thermal out GPIO */
2083         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2084         && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2085             table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2086     } else {
2087         table->ThermOutGpio = 17;
2088         table->ThermOutPolarity = 1;
2089         table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2090     }
2091
2092     /* Populate BIF_SCLK levels into SMC DPM table */
2093     for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2094         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
2095         PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2096
2097         if (i == 0)
2098             table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2099         else
2100             table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2101     }
2102
2103     for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2104         table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2105
2106     CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2107     CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2108     CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2109     CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2110     CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2111     CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2112     CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2113     CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2114     CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2115     CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2116
2117     /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2118     result = smu7_copy_bytes_to_smc(hwmgr,
2119             smu_data->smu7_data.dpm_table_start +
2120             offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2121             (uint8_t *)&(table->SystemFlags),
2122             sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2123             SMC_RAM_END);
2124     PP_ASSERT_WITH_CODE(0 == result,
2125             "Failed to upload dpm data to SMC memory!", return result);
2126
2127     result = polaris10_populate_pm_fuses(hwmgr);
2128     PP_ASSERT_WITH_CODE(0 == result,
2129             "Failed to  populate PM fuses to SMC memory!", return result);
2130
2131     return 0;
2132 }
2133
2134 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2135 {
2136     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2137
2138     if (data->need_update_smu7_dpm_table &
2139         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2140         return polaris10_program_memory_timing_parameters(hwmgr);
2141
2142     return 0;
2143 }
2144
2145 static int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2146 {
2147     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2148
2149     if (!hwmgr->avfs_supported)
2150         return 0;
2151
2152     smum_send_msg_to_smc_with_parameter(hwmgr,
2153             PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting,
2154             NULL);
2155
2156     smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2157
2158     /* Apply avfs cks-off voltages to avoid the overshoot
2159      * when switching to the highest sclk frequency
2160      */
2161     if (data->apply_avfs_cks_off_voltage)
2162         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL);
2163
2164     return 0;
2165 }
2166
2167 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2168 {
2169     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2170     SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2171     uint32_t duty100;
2172     uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2173     uint16_t fdo_min, slope1, slope2;
2174     uint32_t reference_clock;
2175     int res;
2176     uint64_t tmp64;
2177
2178     if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2179         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2180             PHM_PlatformCaps_MicrocodeFanControl);
2181         return 0;
2182     }
2183
2184     if (smu_data->smu7_data.fan_table_start == 0) {
2185         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2186                 PHM_PlatformCaps_MicrocodeFanControl);
2187         return 0;
2188     }
2189
2190     duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2191             CG_FDO_CTRL1, FMAX_DUTY100);
2192
2193     if (duty100 == 0) {
2194         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2195                 PHM_PlatformCaps_MicrocodeFanControl);
2196         return 0;
2197     }
2198
2199     /* use hardware fan control */
2200     if (hwmgr->thermal_controller.use_hw_fan_control)
2201         return 0;
2202
2203     tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2204             usPWMMin * duty100;
2205     do_div(tmp64, 10000);
2206     fdo_min = (uint16_t)tmp64;
2207
2208     t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2209             hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2210     t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2211             hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2212
2213     pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2214             hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2215     pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2216             hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2217
2218     slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2219     slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2220
2221     fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2222             thermal_controller.advanceFanControlParameters.usTMin) / 100);
2223     fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2224             thermal_controller.advanceFanControlParameters.usTMed) / 100);
2225     fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2226             thermal_controller.advanceFanControlParameters.usTMax) / 100);
2227
2228     fan_table.Slope1 = cpu_to_be16(slope1);
2229     fan_table.Slope2 = cpu_to_be16(slope2);
2230
2231     fan_table.FdoMin = cpu_to_be16(fdo_min);
2232
2233     fan_table.HystDown = cpu_to_be16(hwmgr->
2234             thermal_controller.advanceFanControlParameters.ucTHyst);
2235
2236     fan_table.HystUp = cpu_to_be16(1);
2237
2238     fan_table.HystSlope = cpu_to_be16(1);
2239
2240     fan_table.TempRespLim = cpu_to_be16(5);
2241
2242     reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2243
2244     fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2245             thermal_controller.advanceFanControlParameters.ulCycleDelay *
2246             reference_clock) / 1600);
2247
2248     fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2249
2250     fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2251             hwmgr->device, CGS_IND_REG__SMC,
2252             CG_MULT_THERMAL_CTRL, TEMP_SEL);
2253
2254     res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2255             (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2256             SMC_RAM_END);
2257
2258     if (!res && hwmgr->thermal_controller.
2259             advanceFanControlParameters.ucMinimumPWMLimit)
2260         res = smum_send_msg_to_smc_with_parameter(hwmgr,
2261                 PPSMC_MSG_SetFanMinPwm,
2262                 hwmgr->thermal_controller.
2263                 advanceFanControlParameters.ucMinimumPWMLimit,
2264                 NULL);
2265
2266     if (!res && hwmgr->thermal_controller.
2267             advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2268         res = smum_send_msg_to_smc_with_parameter(hwmgr,
2269                 PPSMC_MSG_SetFanSclkTarget,
2270                 hwmgr->thermal_controller.
2271                 advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2272                 NULL);
2273
2274     if (res)
2275         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2276                 PHM_PlatformCaps_MicrocodeFanControl);
2277
2278     return 0;
2279 }
2280
2281 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2282 {
2283     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2284     uint32_t mm_boot_level_offset, mm_boot_level_value;
2285     struct phm_ppt_v1_information *table_info =
2286             (struct phm_ppt_v1_information *)(hwmgr->pptable);
2287
2288     smu_data->smc_state_table.UvdBootLevel = 0;
2289     if (table_info->mm_dep_table->count > 0)
2290         smu_data->smc_state_table.UvdBootLevel =
2291                 (uint8_t) (table_info->mm_dep_table->count - 1);
2292     mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2293                         UvdBootLevel);
2294     mm_boot_level_offset /= 4;
2295     mm_boot_level_offset *= 4;
2296     mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2297             CGS_IND_REG__SMC, mm_boot_level_offset);
2298     mm_boot_level_value &= 0x00FFFFFF;
2299     mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2300     cgs_write_ind_register(hwmgr->device,
2301             CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2302
2303     if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2304             PHM_PlatformCaps_UVDDPM) ||
2305         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2306             PHM_PlatformCaps_StablePState))
2307         smum_send_msg_to_smc_with_parameter(hwmgr,
2308                 PPSMC_MSG_UVDDPM_SetEnabledMask,
2309                 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2310                 NULL);
2311     return 0;
2312 }
2313
2314 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2315 {
2316     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2317     uint32_t mm_boot_level_offset, mm_boot_level_value;
2318     struct phm_ppt_v1_information *table_info =
2319             (struct phm_ppt_v1_information *)(hwmgr->pptable);
2320
2321     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2322                     PHM_PlatformCaps_StablePState))
2323         smu_data->smc_state_table.VceBootLevel =
2324             (uint8_t) (table_info->mm_dep_table->count - 1);
2325     else
2326         smu_data->smc_state_table.VceBootLevel = 0;
2327
2328     mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2329                     offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2330     mm_boot_level_offset /= 4;
2331     mm_boot_level_offset *= 4;
2332     mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2333             CGS_IND_REG__SMC, mm_boot_level_offset);
2334     mm_boot_level_value &= 0xFF00FFFF;
2335     mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2336     cgs_write_ind_register(hwmgr->device,
2337             CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2338
2339     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2340         smum_send_msg_to_smc_with_parameter(hwmgr,
2341                 PPSMC_MSG_VCEDPM_SetEnabledMask,
2342                 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2343                 NULL);
2344     return 0;
2345 }
2346
2347 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2348 {
2349     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2350     struct phm_ppt_v1_information *table_info =
2351             (struct phm_ppt_v1_information *)(hwmgr->pptable);
2352     struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2353     int max_entry, i;
2354
2355     max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2356                         SMU74_MAX_LEVELS_LINK :
2357                         pcie_table->count;
2358     /* Setup BIF_SCLK levels */
2359     for (i = 0; i < max_entry; i++)
2360         smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2361     return 0;
2362 }
2363
2364 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2365 {
2366     switch (type) {
2367     case SMU_UVD_TABLE:
2368         polaris10_update_uvd_smc_table(hwmgr);
2369         break;
2370     case SMU_VCE_TABLE:
2371         polaris10_update_vce_smc_table(hwmgr);
2372         break;
2373     case SMU_BIF_TABLE:
2374         polaris10_update_bif_smc_table(hwmgr);
2375         break;
2376     default:
2377         break;
2378     }
2379     return 0;
2380 }
2381
2382 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2383 {
2384     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2385     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2386
2387     int result = 0;
2388     uint32_t low_sclk_interrupt_threshold = 0;
2389
2390     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2391             PHM_PlatformCaps_SclkThrottleLowNotification)
2392         && (data->low_sclk_interrupt_threshold != 0)) {
2393         low_sclk_interrupt_threshold =
2394                 data->low_sclk_interrupt_threshold;
2395
2396         CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2397
2398         result = smu7_copy_bytes_to_smc(
2399                 hwmgr,
2400                 smu_data->smu7_data.dpm_table_start +
2401                 offsetof(SMU74_Discrete_DpmTable,
2402                     LowSclkInterruptThreshold),
2403                 (uint8_t *)&low_sclk_interrupt_threshold,
2404                 sizeof(uint32_t),
2405                 SMC_RAM_END);
2406     }
2407     PP_ASSERT_WITH_CODE((result == 0),
2408             "Failed to update SCLK threshold!", return result);
2409
2410     result = polaris10_program_mem_timing_parameters(hwmgr);
2411     PP_ASSERT_WITH_CODE((result == 0),
2412             "Failed to program memory timing parameters!",
2413             );
2414
2415     return result;
2416 }
2417
2418 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2419 {
2420     switch (type) {
2421     case SMU_SoftRegisters:
2422         switch (member) {
2423         case HandshakeDisables:
2424             return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2425         case VoltageChangeTimeout:
2426             return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2427         case AverageGraphicsActivity:
2428             return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2429         case AverageMemoryActivity:
2430             return offsetof(SMU74_SoftRegisters, AverageMemoryActivity);
2431         case PreVBlankGap:
2432             return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2433         case VBlankTimeout:
2434             return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2435         case UcodeLoadStatus:
2436             return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2437         case DRAM_LOG_ADDR_H:
2438             return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2439         case DRAM_LOG_ADDR_L:
2440             return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2441         case DRAM_LOG_PHY_ADDR_H:
2442             return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2443         case DRAM_LOG_PHY_ADDR_L:
2444             return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2445         case DRAM_LOG_BUFF_SIZE:
2446             return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2447         }
2448         break;
2449     case SMU_Discrete_DpmTable:
2450         switch (member) {
2451         case UvdBootLevel:
2452             return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2453         case VceBootLevel:
2454             return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2455         case LowSclkInterruptThreshold:
2456             return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2457         }
2458         break;
2459     }
2460     pr_warn("can't get the offset of type %x member %x\n", type, member);
2461     return 0;
2462 }
2463
2464 static uint32_t polaris10_get_mac_definition(uint32_t value)
2465 {
2466     switch (value) {
2467     case SMU_MAX_LEVELS_GRAPHICS:
2468         return SMU74_MAX_LEVELS_GRAPHICS;
2469     case SMU_MAX_LEVELS_MEMORY:
2470         return SMU74_MAX_LEVELS_MEMORY;
2471     case SMU_MAX_LEVELS_LINK:
2472         return SMU74_MAX_LEVELS_LINK;
2473     case SMU_MAX_ENTRIES_SMIO:
2474         return SMU74_MAX_ENTRIES_SMIO;
2475     case SMU_MAX_LEVELS_VDDC:
2476         return SMU74_MAX_LEVELS_VDDC;
2477     case SMU_MAX_LEVELS_VDDGFX:
2478         return SMU74_MAX_LEVELS_VDDGFX;
2479     case SMU_MAX_LEVELS_VDDCI:
2480         return SMU74_MAX_LEVELS_VDDCI;
2481     case SMU_MAX_LEVELS_MVDD:
2482         return SMU74_MAX_LEVELS_MVDD;
2483     case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2484         return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
2485                 SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
2486     }
2487
2488     pr_warn("can't get the mac of %x\n", value);
2489     return 0;
2490 }
2491
2492 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2493 {
2494     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2495     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2496     uint32_t tmp;
2497     int result;
2498     bool error = false;
2499
2500     result = smu7_read_smc_sram_dword(hwmgr,
2501             SMU7_FIRMWARE_HEADER_LOCATION +
2502             offsetof(SMU74_Firmware_Header, DpmTable),
2503             &tmp, SMC_RAM_END);
2504
2505     if (0 == result)
2506         smu_data->smu7_data.dpm_table_start = tmp;
2507
2508     error |= (0 != result);
2509
2510     result = smu7_read_smc_sram_dword(hwmgr,
2511             SMU7_FIRMWARE_HEADER_LOCATION +
2512             offsetof(SMU74_Firmware_Header, SoftRegisters),
2513             &tmp, SMC_RAM_END);
2514
2515     if (!result) {
2516         data->soft_regs_start = tmp;
2517         smu_data->smu7_data.soft_regs_start = tmp;
2518     }
2519
2520     error |= (0 != result);
2521
2522     result = smu7_read_smc_sram_dword(hwmgr,
2523             SMU7_FIRMWARE_HEADER_LOCATION +
2524             offsetof(SMU74_Firmware_Header, mcRegisterTable),
2525             &tmp, SMC_RAM_END);
2526
2527     if (!result)
2528         smu_data->smu7_data.mc_reg_table_start = tmp;
2529
2530     result = smu7_read_smc_sram_dword(hwmgr,
2531             SMU7_FIRMWARE_HEADER_LOCATION +
2532             offsetof(SMU74_Firmware_Header, FanTable),
2533             &tmp, SMC_RAM_END);
2534
2535     if (!result)
2536         smu_data->smu7_data.fan_table_start = tmp;
2537
2538     error |= (0 != result);
2539
2540     result = smu7_read_smc_sram_dword(hwmgr,
2541             SMU7_FIRMWARE_HEADER_LOCATION +
2542             offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2543             &tmp, SMC_RAM_END);
2544
2545     if (!result)
2546         smu_data->smu7_data.arb_table_start = tmp;
2547
2548     error |= (0 != result);
2549
2550     result = smu7_read_smc_sram_dword(hwmgr,
2551             SMU7_FIRMWARE_HEADER_LOCATION +
2552             offsetof(SMU74_Firmware_Header, Version),
2553             &tmp, SMC_RAM_END);
2554
2555     if (!result)
2556         hwmgr->microcode_version_info.SMC = tmp;
2557
2558     error |= (0 != result);
2559
2560     return error ? -1 : 0;
2561 }
2562
2563 static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2564 {
2565     return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2566 }
2567
2568 static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2569 {
2570     int result;
2571     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2572     pp_atomctrl_mc_reg_table *mc_reg_table = &smu_data->mc_reg_table;
2573     uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
2574
2575     memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table));
2576     result = atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index, mc_reg_table);
2577
2578     return result;
2579 }
2580
2581 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2582 {
2583     return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2584             CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2585             ? true : false;
2586 }
2587
2588 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2589                 void *profile_setting)
2590 {
2591     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2592     struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2593             (hwmgr->smu_backend);
2594     struct profile_mode_setting *setting;
2595     struct SMU74_Discrete_GraphicsLevel *levels =
2596             smu_data->smc_state_table.GraphicsLevel;
2597     uint32_t array = smu_data->smu7_data.dpm_table_start +
2598             offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2599
2600     uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2601             offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2602     struct SMU74_Discrete_MemoryLevel *mclk_levels =
2603             smu_data->smc_state_table.MemoryLevel;
2604     uint32_t i;
2605     uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2606
2607     if (profile_setting == NULL)
2608         return -EINVAL;
2609
2610     setting = (struct profile_mode_setting *)profile_setting;
2611
2612     if (setting->bupdate_sclk) {
2613         if (!data->sclk_dpm_key_disabled)
2614             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2615         for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2616             if (levels[i].ActivityLevel !=
2617                 cpu_to_be16(setting->sclk_activity)) {
2618                 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2619
2620                 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2621                         + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
2622                 offset = clk_activity_offset & ~0x3;
2623                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2624                 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2625                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2626
2627             }
2628             if (levels[i].UpHyst != setting->sclk_up_hyst ||
2629                 levels[i].DownHyst != setting->sclk_down_hyst) {
2630                 levels[i].UpHyst = setting->sclk_up_hyst;
2631                 levels[i].DownHyst = setting->sclk_down_hyst;
2632                 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2633                         + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2634                 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2635                         + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2636                 offset = up_hyst_offset & ~0x3;
2637                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2638                 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2639                 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2640                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2641             }
2642         }
2643         if (!data->sclk_dpm_key_disabled)
2644             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2645     }
2646
2647     if (setting->bupdate_mclk) {
2648         if (!data->mclk_dpm_key_disabled)
2649             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2650         for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2651             if (mclk_levels[i].ActivityLevel !=
2652                 cpu_to_be16(setting->mclk_activity)) {
2653                 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2654
2655                 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2656                         + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2657                 offset = clk_activity_offset & ~0x3;
2658                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2659                 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2660                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2661
2662             }
2663             if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2664                 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2665                 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2666                 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2667                 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2668                         + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2669                 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2670                         + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2671                 offset = up_hyst_offset & ~0x3;
2672                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2673                 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2674                 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2675                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2676             }
2677         }
2678         if (!data->mclk_dpm_key_disabled)
2679             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
2680     }
2681     return 0;
2682 }
2683
2684 const struct pp_smumgr_func polaris10_smu_funcs = {
2685     .name = "polaris10_smu",
2686     .smu_init = polaris10_smu_init,
2687     .smu_fini = smu7_smu_fini,
2688     .start_smu = polaris10_start_smu,
2689     .check_fw_load_finish = smu7_check_fw_load_finish,
2690     .request_smu_load_fw = smu7_reload_firmware,
2691     .request_smu_load_specific_fw = NULL,
2692     .send_msg_to_smc = smu7_send_msg_to_smc,
2693     .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2694     .get_argument = smu7_get_argument,
2695     .download_pptable_settings = NULL,
2696     .upload_pptable_settings = NULL,
2697     .update_smc_table = polaris10_update_smc_table,
2698     .get_offsetof = polaris10_get_offsetof,
2699     .process_firmware_header = polaris10_process_firmware_header,
2700     .init_smc_table = polaris10_init_smc_table,
2701     .update_sclk_threshold = polaris10_update_sclk_threshold,
2702     .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2703     .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2704     .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2705     .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2706     .get_mac_definition = polaris10_get_mac_definition,
2707     .initialize_mc_reg_table = polaris10_initialize_mc_reg_table,
2708     .is_dpm_running = polaris10_is_dpm_running,
2709     .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2710     .update_dpm_settings = polaris10_update_dpm_settings,
2711 };