powerplay/smumgr/fiji_smumgr.c

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "pp_debug.h"
0025 #include "smumgr.h"
0026 #include "smu7_dyn_defaults.h"
0027 #include "smu73.h"
0028 #include "smu_ucode_xfer_vi.h"
0029 #include "fiji_smumgr.h"
0030 #include "fiji_ppsmc.h"
0031 #include "smu73_discrete.h"
0032 #include "ppatomctrl.h"
0033 #include "smu/smu_7_1_3_d.h"
0034 #include "smu/smu_7_1_3_sh_mask.h"
0035 #include "gmc/gmc_8_1_d.h"
0036 #include "gmc/gmc_8_1_sh_mask.h"
0037 #include "oss/oss_3_0_d.h"
0038 #include "gca/gfx_8_0_d.h"
0039 #include "bif/bif_5_0_d.h"
0040 #include "bif/bif_5_0_sh_mask.h"
0041 #include "dce/dce_10_0_d.h"
0042 #include "dce/dce_10_0_sh_mask.h"
0043 #include "hardwaremanager.h"
0044 #include "cgs_common.h"
0045 #include "atombios.h"
0046 #include "pppcielanes.h"
0047 #include "hwmgr.h"
0048 #include "smu7_hwmgr.h"
0049
0050
0051 #define AVFS_EN_MSB                                        1568
0052 #define AVFS_EN_LSB                                        1568
0053
0054 #define FIJI_SMC_SIZE 0x20000
0055
0056 #define POWERTUNE_DEFAULT_SET_MAX    1
0057 #define VDDC_VDDCI_DELTA            300
0058 #define MC_CG_ARB_FREQ_F1           0x0b
0059
0060 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
0061  * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
0062  */
0063 static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = {
0064                 {600, 1050, 3, 0}, {600, 1050, 6, 1} };
0065
0066 /* [FF, SS] type, [] 4 voltage ranges, and
0067  * [Floor Freq, Boundary Freq, VID min , VID max]
0068  */
0069 static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = {
0070     { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
0071     { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
0072
0073 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
0074  * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
0075  */
0076 static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = {
0077                 {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
0078
0079 static const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
0080         /*sviLoadLIneEn,  SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc */
0081         {1,               0xF,             0xFD,
0082         /* TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase */
0083         0x19,        5,               45}
0084 };
0085
0086 static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = {
0087         /*  Min        Sclk       pcie     DeepSleep Activity  CgSpll      CgSpll    spllSpread  SpllSpread   CcPwr  CcPwr  Sclk   Display     Enabled     Enabled                       Voltage    Power */
0088         /* Voltage,  Frequency,  DpmLevel,  DivId,    Level,  FuncCntl3,  FuncCntl4,  Spectrum,   Spectrum2,  DynRm, DynRm1  Did, Watermark, ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
0089         { 0x3c0fd047, 0x30750000,   0x00,     0x03,   0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0090         { 0xa00fd047, 0x409c0000,   0x01,     0x04,   0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x16,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0091         { 0x0410d047, 0x50c30000,   0x01,     0x00,   0x1e00, 0x00600410, 0x87020000, 0x21680000, 0x0d000000,   0,      0,   0x0e,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0092         { 0x6810d047, 0x60ea0000,   0x01,     0x00,   0x1e00, 0x00800410, 0x87020000, 0x21680000, 0x0e000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0093         { 0xcc10d047, 0xe8fd0000,   0x01,     0x00,   0x1e00, 0x00e00410, 0x87020000, 0x21680000, 0x0f000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0094         { 0x3011d047, 0x70110100,   0x01,     0x00,   0x1e00, 0x00400510, 0x87020000, 0x21680000, 0x10000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0095         { 0x9411d047, 0xf8240100,   0x01,     0x00,   0x1e00, 0x00a00510, 0x87020000, 0x21680000, 0x11000000,   0,      0,   0x0c,   0x00,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 },
0096         { 0xf811d047, 0x80380100,   0x01,     0x00,   0x1e00, 0x00000610, 0x87020000, 0x21680000, 0x12000000,   0,      0,   0x0c,   0x01,       0x01,        0x01,      0x00,   0x00,      0x00,     0x00 }
0097 };
0098
0099 static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
0100 {
0101     int result = 0;
0102
0103     /* Wait for smc boot up */
0104     /* PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
0105         RCU_UC_EVENTS, boot_seq_done, 0); */
0106
0107     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0108             SMC_SYSCON_RESET_CNTL, rst_reg, 1);
0109
0110     result = smu7_upload_smu_firmware_image(hwmgr);
0111     if (result)
0112         return result;
0113
0114     /* Clear status */
0115     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
0116             ixSMU_STATUS, 0);
0117
0118     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0119             SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
0120
0121     /* De-assert reset */
0122     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0123             SMC_SYSCON_RESET_CNTL, rst_reg, 0);
0124
0125     /* Wait for ROM firmware to initialize interrupt hendler */
0126     /*SMUM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, SMC_IND,
0127             SMC_INTR_CNTL_MASK_0, 0x10040, 0xFFFFFFFF); */
0128
0129     /* Set SMU Auto Start */
0130     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0131             SMU_INPUT_DATA, AUTO_START, 1);
0132
0133     /* Clear firmware interrupt enable flag */
0134     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
0135             ixFIRMWARE_FLAGS, 0);
0136
0137     PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
0138             INTERRUPTS_ENABLED, 1);
0139
0140     smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Test, 0x20000, NULL);
0141
0142     /* Wait for done bit to be set */
0143     PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
0144             SMU_STATUS, SMU_DONE, 0);
0145
0146     /* Check pass/failed indicator */
0147     if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0148             SMU_STATUS, SMU_PASS) != 1) {
0149         PP_ASSERT_WITH_CODE(false,
0150                 "SMU Firmware start failed!", return -1);
0151     }
0152
0153     /* Wait for firmware to initialize */
0154     PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
0155             FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
0156
0157     return result;
0158 }
0159
0160 static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
0161 {
0162     int result = 0;
0163
0164     /* wait for smc boot up */
0165     PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
0166             RCU_UC_EVENTS, boot_seq_done, 0);
0167
0168     /* Clear firmware interrupt enable flag */
0169     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
0170             ixFIRMWARE_FLAGS, 0);
0171
0172     /* Assert reset */
0173     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0174             SMC_SYSCON_RESET_CNTL, rst_reg, 1);
0175
0176     result = smu7_upload_smu_firmware_image(hwmgr);
0177     if (result)
0178         return result;
0179
0180     /* Set smc instruct start point at 0x0 */
0181     smu7_program_jump_on_start(hwmgr);
0182
0183     /* Enable clock */
0184     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0185             SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
0186
0187     /* De-assert reset */
0188     PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
0189             SMC_SYSCON_RESET_CNTL, rst_reg, 0);
0190
0191     /* Wait for firmware to initialize */
0192     PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
0193             FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
0194
0195     return result;
0196 }
0197
0198 static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
0199 {
0200     int result = 0;
0201     struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
0202
0203     if (0 != smu_data->avfs_btc_param) {
0204         if (0 != smum_send_msg_to_smc_with_parameter(hwmgr,
0205                 PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
0206                 NULL)) {
0207             pr_info("[AVFS][Fiji_PerformBtc] PerformBTC SMU msg failed");
0208             result = -EINVAL;
0209         }
0210     }
0211     /* Soft-Reset to reset the engine before loading uCode */
0212      /* halt */
0213     cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
0214     /* reset everything */
0215     cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
0216     /* clear reset */
0217     cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
0218
0219     return result;
0220 }
0221
0222 static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
0223 {
0224     int32_t vr_config;
0225     uint32_t table_start;
0226     uint32_t level_addr, vr_config_addr;
0227     uint32_t level_size = sizeof(avfs_graphics_level);
0228
0229     PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
0230             SMU7_FIRMWARE_HEADER_LOCATION +
0231             offsetof(SMU73_Firmware_Header, DpmTable),
0232             &table_start, 0x40000),
0233             "[AVFS][Fiji_SetupGfxLvlStruct] SMU could not "
0234             "communicate starting address of DPM table",
0235             return -1;);
0236
0237     /* Default value for vr_config =
0238      * VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
0239     vr_config = 0x01000500;   /* Real value:0x50001 */
0240
0241     vr_config_addr = table_start +
0242             offsetof(SMU73_Discrete_DpmTable, VRConfig);
0243
0244     PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
0245             (uint8_t *)&vr_config, sizeof(int32_t), 0x40000),
0246             "[AVFS][Fiji_SetupGfxLvlStruct] Problems copying "
0247             "vr_config value over to SMC",
0248             return -1;);
0249
0250     level_addr = table_start + offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
0251
0252     PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
0253             (uint8_t *)(&avfs_graphics_level), level_size, 0x40000),
0254             "[AVFS][Fiji_SetupGfxLvlStruct] Copying of DPM table failed!",
0255             return -1;);
0256
0257     return 0;
0258 }
0259
0260 static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr)
0261 {
0262     if (!hwmgr->avfs_supported)
0263         return 0;
0264
0265     PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
0266             "[AVFS][fiji_avfs_event_mgr] Could not Copy Graphics Level"
0267             " table over to SMU",
0268             return -EINVAL);
0269     PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
0270             "[AVFS][fiji_avfs_event_mgr] Could not setup "
0271             "Pwr Virus for AVFS ",
0272             return -EINVAL);
0273     PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
0274             "[AVFS][fiji_avfs_event_mgr] Failure at "
0275             "fiji_start_avfs_btc. AVFS Disabled",
0276             return -EINVAL);
0277
0278     return 0;
0279 }
0280
0281 static int fiji_start_smu(struct pp_hwmgr *hwmgr)
0282 {
0283     int result = 0;
0284     struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
0285
0286     /* Only start SMC if SMC RAM is not running */
0287     if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
0288         /* Check if SMU is running in protected mode */
0289         if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
0290                 CGS_IND_REG__SMC,
0291                 SMU_FIRMWARE, SMU_MODE)) {
0292             result = fiji_start_smu_in_non_protection_mode(hwmgr);
0293             if (result)
0294                 return result;
0295         } else {
0296             result = fiji_start_smu_in_protection_mode(hwmgr);
0297             if (result)
0298                 return result;
0299         }
0300         if (fiji_avfs_event_mgr(hwmgr))
0301             hwmgr->avfs_supported = false;
0302     }
0303
0304     /* Setup SoftRegsStart here for register lookup in case
0305      * DummyBackEnd is used and ProcessFirmwareHeader is not executed
0306      */
0307     smu7_read_smc_sram_dword(hwmgr,
0308             SMU7_FIRMWARE_HEADER_LOCATION +
0309             offsetof(SMU73_Firmware_Header, SoftRegisters),
0310             &(priv->smu7_data.soft_regs_start), 0x40000);
0311
0312     result = smu7_request_smu_load_fw(hwmgr);
0313
0314     return result;
0315 }
0316
0317 static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
0318 {
0319
0320     uint32_t efuse = 0;
0321
0322     if (!hwmgr->not_vf)
0323         return false;
0324
0325     if (!atomctrl_read_efuse(hwmgr, AVFS_EN_LSB, AVFS_EN_MSB,
0326             &efuse)) {
0327         if (efuse)
0328             return true;
0329     }
0330     return false;
0331 }
0332
0333 static int fiji_smu_init(struct pp_hwmgr *hwmgr)
0334 {
0335     struct fiji_smumgr *fiji_priv = NULL;
0336
0337     fiji_priv = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL);
0338
0339     if (fiji_priv == NULL)
0340         return -ENOMEM;
0341
0342     hwmgr->smu_backend = fiji_priv;
0343
0344     if (smu7_init(hwmgr)) {
0345         kfree(fiji_priv);
0346         return -EINVAL;
0347     }
0348
0349     return 0;
0350 }
0351
0352 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
0353         struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
0354         uint32_t clock, uint32_t *voltage, uint32_t *mvdd)
0355 {
0356     uint32_t i;
0357     uint16_t vddci;
0358     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0359     *voltage = *mvdd = 0;
0360
0361
0362     /* clock - voltage dependency table is empty table */
0363     if (dep_table->count == 0)
0364         return -EINVAL;
0365
0366     for (i = 0; i < dep_table->count; i++) {
0367         /* find first sclk bigger than request */
0368         if (dep_table->entries[i].clk >= clock) {
0369             *voltage |= (dep_table->entries[i].vddc *
0370                     VOLTAGE_SCALE) << VDDC_SHIFT;
0371             if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
0372                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
0373                         VOLTAGE_SCALE) << VDDCI_SHIFT;
0374             else if (dep_table->entries[i].vddci)
0375                 *voltage |= (dep_table->entries[i].vddci *
0376                         VOLTAGE_SCALE) << VDDCI_SHIFT;
0377             else {
0378                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
0379                         (dep_table->entries[i].vddc -
0380                                 VDDC_VDDCI_DELTA));
0381                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
0382             }
0383
0384             if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
0385                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
0386                     VOLTAGE_SCALE;
0387             else if (dep_table->entries[i].mvdd)
0388                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
0389                     VOLTAGE_SCALE;
0390
0391             *voltage |= 1 << PHASES_SHIFT;
0392             return 0;
0393         }
0394     }
0395
0396     /* sclk is bigger than max sclk in the dependence table */
0397     *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
0398
0399     if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
0400         *voltage |= (data->vbios_boot_state.vddci_bootup_value *
0401                 VOLTAGE_SCALE) << VDDCI_SHIFT;
0402     else if (dep_table->entries[i-1].vddci) {
0403         vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
0404                 (dep_table->entries[i].vddc -
0405                         VDDC_VDDCI_DELTA));
0406         *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
0407     }
0408
0409     if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
0410         *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
0411     else if (dep_table->entries[i].mvdd)
0412         *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
0413
0414     return 0;
0415 }
0416
0417
0418 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
0419 {
0420     uint32_t tmp;
0421     tmp = raw_setting * 4096 / 100;
0422     return (uint16_t)tmp;
0423 }
0424
0425 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda)
0426 {
0427     switch (line) {
0428     case SMU7_I2CLineID_DDC1:
0429         *scl = SMU7_I2C_DDC1CLK;
0430         *sda = SMU7_I2C_DDC1DATA;
0431         break;
0432     case SMU7_I2CLineID_DDC2:
0433         *scl = SMU7_I2C_DDC2CLK;
0434         *sda = SMU7_I2C_DDC2DATA;
0435         break;
0436     case SMU7_I2CLineID_DDC3:
0437         *scl = SMU7_I2C_DDC3CLK;
0438         *sda = SMU7_I2C_DDC3DATA;
0439         break;
0440     case SMU7_I2CLineID_DDC4:
0441         *scl = SMU7_I2C_DDC4CLK;
0442         *sda = SMU7_I2C_DDC4DATA;
0443         break;
0444     case SMU7_I2CLineID_DDC5:
0445         *scl = SMU7_I2C_DDC5CLK;
0446         *sda = SMU7_I2C_DDC5DATA;
0447         break;
0448     case SMU7_I2CLineID_DDC6:
0449         *scl = SMU7_I2C_DDC6CLK;
0450         *sda = SMU7_I2C_DDC6DATA;
0451         break;
0452     case SMU7_I2CLineID_SCLSDA:
0453         *scl = SMU7_I2C_SCL;
0454         *sda = SMU7_I2C_SDA;
0455         break;
0456     case SMU7_I2CLineID_DDCVGA:
0457         *scl = SMU7_I2C_DDCVGACLK;
0458         *sda = SMU7_I2C_DDCVGADATA;
0459         break;
0460     default:
0461         *scl = 0;
0462         *sda = 0;
0463         break;
0464     }
0465 }
0466
0467 static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
0468 {
0469     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0470     struct phm_ppt_v1_information *table_info =
0471             (struct  phm_ppt_v1_information *)(hwmgr->pptable);
0472
0473     if (table_info &&
0474             table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
0475             table_info->cac_dtp_table->usPowerTuneDataSetID)
0476         smu_data->power_tune_defaults =
0477                 &fiji_power_tune_data_set_array
0478                 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
0479     else
0480         smu_data->power_tune_defaults = &fiji_power_tune_data_set_array[0];
0481
0482 }
0483
0484 static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
0485 {
0486
0487     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0488     const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
0489
0490     SMU73_Discrete_DpmTable  *dpm_table = &(smu_data->smc_state_table);
0491
0492     struct phm_ppt_v1_information *table_info =
0493             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0494     struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
0495     struct pp_advance_fan_control_parameters *fan_table =
0496             &hwmgr->thermal_controller.advanceFanControlParameters;
0497     uint8_t uc_scl, uc_sda;
0498
0499     /* TDP number of fraction bits are changed from 8 to 7 for Fiji
0500      * as requested by SMC team
0501      */
0502     dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
0503             (uint16_t)(cac_dtp_table->usTDP * 128));
0504     dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
0505             (uint16_t)(cac_dtp_table->usTDP * 128));
0506
0507     PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
0508             "Target Operating Temp is out of Range!",
0509             );
0510
0511     dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
0512     dpm_table->GpuTjHyst = 8;
0513
0514     dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase;
0515
0516     /* The following are for new Fiji Multi-input fan/thermal control */
0517     dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
0518             cac_dtp_table->usTargetOperatingTemp * 256);
0519     dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
0520             cac_dtp_table->usTemperatureLimitHotspot * 256);
0521     dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US(
0522             cac_dtp_table->usTemperatureLimitLiquid1 * 256);
0523     dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US(
0524             cac_dtp_table->usTemperatureLimitLiquid2 * 256);
0525     dpm_table->TemperatureLimitVrVddc = PP_HOST_TO_SMC_US(
0526             cac_dtp_table->usTemperatureLimitVrVddc * 256);
0527     dpm_table->TemperatureLimitVrMvdd = PP_HOST_TO_SMC_US(
0528             cac_dtp_table->usTemperatureLimitVrMvdd * 256);
0529     dpm_table->TemperatureLimitPlx = PP_HOST_TO_SMC_US(
0530             cac_dtp_table->usTemperatureLimitPlx * 256);
0531
0532     dpm_table->FanGainEdge = PP_HOST_TO_SMC_US(
0533             scale_fan_gain_settings(fan_table->usFanGainEdge));
0534     dpm_table->FanGainHotspot = PP_HOST_TO_SMC_US(
0535             scale_fan_gain_settings(fan_table->usFanGainHotspot));
0536     dpm_table->FanGainLiquid = PP_HOST_TO_SMC_US(
0537             scale_fan_gain_settings(fan_table->usFanGainLiquid));
0538     dpm_table->FanGainVrVddc = PP_HOST_TO_SMC_US(
0539             scale_fan_gain_settings(fan_table->usFanGainVrVddc));
0540     dpm_table->FanGainVrMvdd = PP_HOST_TO_SMC_US(
0541             scale_fan_gain_settings(fan_table->usFanGainVrMvdd));
0542     dpm_table->FanGainPlx = PP_HOST_TO_SMC_US(
0543             scale_fan_gain_settings(fan_table->usFanGainPlx));
0544     dpm_table->FanGainHbm = PP_HOST_TO_SMC_US(
0545             scale_fan_gain_settings(fan_table->usFanGainHbm));
0546
0547     dpm_table->Liquid1_I2C_address = cac_dtp_table->ucLiquid1_I2C_address;
0548     dpm_table->Liquid2_I2C_address = cac_dtp_table->ucLiquid2_I2C_address;
0549     dpm_table->Vr_I2C_address = cac_dtp_table->ucVr_I2C_address;
0550     dpm_table->Plx_I2C_address = cac_dtp_table->ucPlx_I2C_address;
0551
0552     get_scl_sda_value(cac_dtp_table->ucLiquid_I2C_Line, &uc_scl, &uc_sda);
0553     dpm_table->Liquid_I2C_LineSCL = uc_scl;
0554     dpm_table->Liquid_I2C_LineSDA = uc_sda;
0555
0556     get_scl_sda_value(cac_dtp_table->ucVr_I2C_Line, &uc_scl, &uc_sda);
0557     dpm_table->Vr_I2C_LineSCL = uc_scl;
0558     dpm_table->Vr_I2C_LineSDA = uc_sda;
0559
0560     get_scl_sda_value(cac_dtp_table->ucPlx_I2C_Line, &uc_scl, &uc_sda);
0561     dpm_table->Plx_I2C_LineSCL = uc_scl;
0562     dpm_table->Plx_I2C_LineSDA = uc_sda;
0563
0564     return 0;
0565 }
0566
0567
0568 static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
0569 {
0570     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0571     const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
0572
0573     smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
0574     smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
0575     smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
0576     smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
0577
0578     return 0;
0579 }
0580
0581
0582 static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
0583 {
0584     uint16_t tdc_limit;
0585     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0586     struct phm_ppt_v1_information *table_info =
0587             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0588     const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
0589
0590     /* TDC number of fraction bits are changed from 8 to 7
0591      * for Fiji as requested by SMC team
0592      */
0593     tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
0594     smu_data->power_tune_table.TDC_VDDC_PkgLimit =
0595             CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
0596     smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
0597             defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
0598     smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
0599
0600     return 0;
0601 }
0602
0603 static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
0604 {
0605     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0606     const struct fiji_pt_defaults *defaults = smu_data->power_tune_defaults;
0607     uint32_t temp;
0608
0609     if (smu7_read_smc_sram_dword(hwmgr,
0610             fuse_table_offset +
0611             offsetof(SMU73_Discrete_PmFuses, TdcWaterfallCtl),
0612             (uint32_t *)&temp, SMC_RAM_END))
0613         PP_ASSERT_WITH_CODE(false,
0614                 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
0615                 return -EINVAL);
0616     else {
0617         smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
0618         smu_data->power_tune_table.LPMLTemperatureMin =
0619                 (uint8_t)((temp >> 16) & 0xff);
0620         smu_data->power_tune_table.LPMLTemperatureMax =
0621                 (uint8_t)((temp >> 8) & 0xff);
0622         smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
0623     }
0624     return 0;
0625 }
0626
0627 static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
0628 {
0629     int i;
0630     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0631
0632     /* Currently not used. Set all to zero. */
0633     for (i = 0; i < 16; i++)
0634         smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
0635
0636     return 0;
0637 }
0638
0639 static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
0640 {
0641     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0642
0643     if ((hwmgr->thermal_controller.advanceFanControlParameters.
0644             usFanOutputSensitivity & (1 << 15)) ||
0645             0 == hwmgr->thermal_controller.advanceFanControlParameters.
0646             usFanOutputSensitivity)
0647         hwmgr->thermal_controller.advanceFanControlParameters.
0648         usFanOutputSensitivity = hwmgr->thermal_controller.
0649             advanceFanControlParameters.usDefaultFanOutputSensitivity;
0650
0651     smu_data->power_tune_table.FuzzyFan_PwmSetDelta =
0652             PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
0653                     advanceFanControlParameters.usFanOutputSensitivity);
0654     return 0;
0655 }
0656
0657 static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
0658 {
0659     int i;
0660     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0661
0662     /* Currently not used. Set all to zero. */
0663     for (i = 0; i < 16; i++)
0664         smu_data->power_tune_table.GnbLPML[i] = 0;
0665
0666     return 0;
0667 }
0668
0669 static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
0670 {
0671     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0672     struct phm_ppt_v1_information *table_info =
0673             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0674     uint16_t HiSidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
0675     uint16_t LoSidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
0676     struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
0677
0678     HiSidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
0679     LoSidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
0680
0681     smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
0682             CONVERT_FROM_HOST_TO_SMC_US(HiSidd);
0683     smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
0684             CONVERT_FROM_HOST_TO_SMC_US(LoSidd);
0685
0686     return 0;
0687 }
0688
0689 static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
0690 {
0691     uint32_t pm_fuse_table_offset;
0692     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0693
0694     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
0695             PHM_PlatformCaps_PowerContainment)) {
0696         if (smu7_read_smc_sram_dword(hwmgr,
0697                 SMU7_FIRMWARE_HEADER_LOCATION +
0698                 offsetof(SMU73_Firmware_Header, PmFuseTable),
0699                 &pm_fuse_table_offset, SMC_RAM_END))
0700             PP_ASSERT_WITH_CODE(false,
0701                     "Attempt to get pm_fuse_table_offset Failed!",
0702                     return -EINVAL);
0703
0704         /* DW6 */
0705         if (fiji_populate_svi_load_line(hwmgr))
0706             PP_ASSERT_WITH_CODE(false,
0707                     "Attempt to populate SviLoadLine Failed!",
0708                     return -EINVAL);
0709         /* DW7 */
0710         if (fiji_populate_tdc_limit(hwmgr))
0711             PP_ASSERT_WITH_CODE(false,
0712                     "Attempt to populate TDCLimit Failed!", return -EINVAL);
0713         /* DW8 */
0714         if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
0715             PP_ASSERT_WITH_CODE(false,
0716                     "Attempt to populate TdcWaterfallCtl, "
0717                     "LPMLTemperature Min and Max Failed!",
0718                     return -EINVAL);
0719
0720         /* DW9-DW12 */
0721         if (0 != fiji_populate_temperature_scaler(hwmgr))
0722             PP_ASSERT_WITH_CODE(false,
0723                     "Attempt to populate LPMLTemperatureScaler Failed!",
0724                     return -EINVAL);
0725
0726         /* DW13-DW14 */
0727         if (fiji_populate_fuzzy_fan(hwmgr))
0728             PP_ASSERT_WITH_CODE(false,
0729                     "Attempt to populate Fuzzy Fan Control parameters Failed!",
0730                     return -EINVAL);
0731
0732         /* DW15-DW18 */
0733         if (fiji_populate_gnb_lpml(hwmgr))
0734             PP_ASSERT_WITH_CODE(false,
0735                     "Attempt to populate GnbLPML Failed!",
0736                     return -EINVAL);
0737
0738         /* DW20 */
0739         if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
0740             PP_ASSERT_WITH_CODE(false,
0741                     "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
0742                     "Sidd Failed!", return -EINVAL);
0743
0744         if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
0745                 (uint8_t *)&smu_data->power_tune_table,
0746                 sizeof(struct SMU73_Discrete_PmFuses), SMC_RAM_END))
0747             PP_ASSERT_WITH_CODE(false,
0748                     "Attempt to download PmFuseTable Failed!",
0749                     return -EINVAL);
0750     }
0751     return 0;
0752 }
0753
0754 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
0755         struct SMU73_Discrete_DpmTable *table)
0756 {
0757     uint32_t count;
0758     uint8_t index;
0759     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0760     struct phm_ppt_v1_information *table_info =
0761             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0762     struct phm_ppt_v1_voltage_lookup_table *lookup_table =
0763             table_info->vddc_lookup_table;
0764     /* tables is already swapped, so in order to use the value from it,
0765      * we need to swap it back.
0766      * We are populating vddc CAC data to BapmVddc table
0767      * in split and merged mode
0768      */
0769
0770     for (count = 0; count < lookup_table->count; count++) {
0771         index = phm_get_voltage_index(lookup_table,
0772                 data->vddc_voltage_table.entries[count].value);
0773         table->BapmVddcVidLoSidd[count] =
0774             convert_to_vid(lookup_table->entries[index].us_cac_low);
0775         table->BapmVddcVidHiSidd[count] =
0776             convert_to_vid(lookup_table->entries[index].us_cac_high);
0777     }
0778
0779     return 0;
0780 }
0781
0782 static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
0783         struct SMU73_Discrete_DpmTable *table)
0784 {
0785     int result;
0786
0787     result = fiji_populate_cac_table(hwmgr, table);
0788     PP_ASSERT_WITH_CODE(0 == result,
0789             "can not populate CAC voltage tables to SMC",
0790             return -EINVAL);
0791
0792     return 0;
0793 }
0794
0795 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
0796         struct SMU73_Discrete_Ulv *state)
0797 {
0798     int result = 0;
0799
0800     struct phm_ppt_v1_information *table_info =
0801             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0802
0803     state->CcPwrDynRm = 0;
0804     state->CcPwrDynRm1 = 0;
0805
0806     state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
0807     state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
0808             VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
0809
0810     state->VddcPhase = 1;
0811
0812     if (!result) {
0813         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
0814         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
0815         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
0816     }
0817     return result;
0818 }
0819
0820 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
0821         struct SMU73_Discrete_DpmTable *table)
0822 {
0823     return fiji_populate_ulv_level(hwmgr, &table->Ulv);
0824 }
0825
0826 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
0827         struct SMU73_Discrete_DpmTable *table)
0828 {
0829     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0830     struct smu7_dpm_table *dpm_table = &data->dpm_table;
0831     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
0832     int i;
0833
0834     /* Index (dpm_table->pcie_speed_table.count)
0835      * is reserved for PCIE boot level. */
0836     for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
0837         table->LinkLevel[i].PcieGenSpeed  =
0838                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
0839         table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
0840                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
0841         table->LinkLevel[i].EnabledForActivity = 1;
0842         table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
0843         table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
0844         table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
0845     }
0846
0847     smu_data->smc_state_table.LinkLevelCount =
0848             (uint8_t)dpm_table->pcie_speed_table.count;
0849     data->dpm_level_enable_mask.pcie_dpm_enable_mask =
0850             phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
0851
0852     return 0;
0853 }
0854
0855 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
0856         uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
0857 {
0858     const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0859     struct pp_atomctrl_clock_dividers_vi dividers;
0860     uint32_t spll_func_cntl            = data->clock_registers.vCG_SPLL_FUNC_CNTL;
0861     uint32_t spll_func_cntl_3          = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
0862     uint32_t spll_func_cntl_4          = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
0863     uint32_t cg_spll_spread_spectrum   = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
0864     uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
0865     uint32_t ref_clock;
0866     uint32_t ref_divider;
0867     uint32_t fbdiv;
0868     int result;
0869
0870     /* get the engine clock dividers for this clock value */
0871     result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
0872
0873     PP_ASSERT_WITH_CODE(result == 0,
0874             "Error retrieving Engine Clock dividers from VBIOS.",
0875             return result);
0876
0877     /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
0878     ref_clock = atomctrl_get_reference_clock(hwmgr);
0879     ref_divider = 1 + dividers.uc_pll_ref_div;
0880
0881     /* low 14 bits is fraction and high 12 bits is divider */
0882     fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
0883
0884     /* SPLL_FUNC_CNTL setup */
0885     spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
0886             SPLL_REF_DIV, dividers.uc_pll_ref_div);
0887     spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
0888             SPLL_PDIV_A,  dividers.uc_pll_post_div);
0889
0890     /* SPLL_FUNC_CNTL_3 setup*/
0891     spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
0892             SPLL_FB_DIV, fbdiv);
0893
0894     /* set to use fractional accumulation*/
0895     spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
0896             SPLL_DITHEN, 1);
0897
0898     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
0899                 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
0900         struct pp_atomctrl_internal_ss_info ssInfo;
0901
0902         uint32_t vco_freq = clock * dividers.uc_pll_post_div;
0903         if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
0904                 vco_freq, &ssInfo)) {
0905             /*
0906              * ss_info.speed_spectrum_percentage -- in unit of 0.01%
0907              * ss_info.speed_spectrum_rate -- in unit of khz
0908              *
0909              * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
0910              */
0911             uint32_t clk_s = ref_clock * 5 /
0912                     (ref_divider * ssInfo.speed_spectrum_rate);
0913             /* clkv = 2 * D * fbdiv / NS */
0914             uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
0915                     fbdiv / (clk_s * 10000);
0916
0917             cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
0918                     CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
0919             cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
0920                     CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
0921             cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
0922                     CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
0923         }
0924     }
0925
0926     sclk->SclkFrequency        = clock;
0927     sclk->CgSpllFuncCntl3      = spll_func_cntl_3;
0928     sclk->CgSpllFuncCntl4      = spll_func_cntl_4;
0929     sclk->SpllSpreadSpectrum   = cg_spll_spread_spectrum;
0930     sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
0931     sclk->SclkDid              = (uint8_t)dividers.pll_post_divider;
0932
0933     return 0;
0934 }
0935
0936 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
0937         uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)
0938 {
0939     int result;
0940     /* PP_Clocks minClocks; */
0941     uint32_t mvdd;
0942     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
0943     struct phm_ppt_v1_information *table_info =
0944             (struct phm_ppt_v1_information *)(hwmgr->pptable);
0945     phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
0946
0947     result = fiji_calculate_sclk_params(hwmgr, clock, level);
0948
0949     if (hwmgr->od_enabled)
0950         vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
0951     else
0952         vdd_dep_table = table_info->vdd_dep_on_sclk;
0953
0954     /* populate graphics levels */
0955     result = fiji_get_dependency_volt_by_clk(hwmgr,
0956             vdd_dep_table, clock,
0957             (uint32_t *)(&level->MinVoltage), &mvdd);
0958     PP_ASSERT_WITH_CODE((0 == result),
0959             "can not find VDDC voltage value for "
0960             "VDDC engine clock dependency table",
0961             return result);
0962
0963     level->SclkFrequency = clock;
0964     level->ActivityLevel = data->current_profile_setting.sclk_activity;
0965     level->CcPwrDynRm = 0;
0966     level->CcPwrDynRm1 = 0;
0967     level->EnabledForActivity = 0;
0968     level->EnabledForThrottle = 1;
0969     level->UpHyst = data->current_profile_setting.sclk_up_hyst;
0970     level->DownHyst = data->current_profile_setting.sclk_down_hyst;
0971     level->VoltageDownHyst = 0;
0972     level->PowerThrottle = 0;
0973
0974     data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
0975
0976     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
0977         level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
0978                                 hwmgr->display_config->min_core_set_clock_in_sr);
0979
0980
0981     /* Default to slow, highest DPM level will be
0982      * set to PPSMC_DISPLAY_WATERMARK_LOW later.
0983      */
0984     level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
0985
0986     CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
0987     CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
0988     CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
0989     CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
0990     CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
0991     CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
0992     CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
0993     CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
0994     CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
0995
0996     return 0;
0997 }
0998
0999 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1000 {
1001     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1002     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1003
1004     struct smu7_dpm_table *dpm_table = &data->dpm_table;
1005     struct phm_ppt_v1_information *table_info =
1006             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1007     struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1008     uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1009     int result = 0;
1010     uint32_t array = smu_data->smu7_data.dpm_table_start +
1011             offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1012     uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1013             SMU73_MAX_LEVELS_GRAPHICS;
1014     struct SMU73_Discrete_GraphicsLevel *levels =
1015             smu_data->smc_state_table.GraphicsLevel;
1016     uint32_t i, max_entry;
1017     uint8_t hightest_pcie_level_enabled = 0,
1018             lowest_pcie_level_enabled = 0,
1019             mid_pcie_level_enabled = 0,
1020             count = 0;
1021
1022     for (i = 0; i < dpm_table->sclk_table.count; i++) {
1023         result = fiji_populate_single_graphic_level(hwmgr,
1024                 dpm_table->sclk_table.dpm_levels[i].value,
1025                 &levels[i]);
1026         if (result)
1027             return result;
1028
1029         /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1030         if (i > 1)
1031             levels[i].DeepSleepDivId = 0;
1032     }
1033
1034     /* Only enable level 0 for now.*/
1035     levels[0].EnabledForActivity = 1;
1036
1037     /* set highest level watermark to high */
1038     levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
1039             PPSMC_DISPLAY_WATERMARK_HIGH;
1040
1041     smu_data->smc_state_table.GraphicsDpmLevelCount =
1042             (uint8_t)dpm_table->sclk_table.count;
1043     data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1044             phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1045
1046     if (pcie_table != NULL) {
1047         PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1048                 "There must be 1 or more PCIE levels defined in PPTable.",
1049                 return -EINVAL);
1050         max_entry = pcie_entry_cnt - 1;
1051         for (i = 0; i < dpm_table->sclk_table.count; i++)
1052             levels[i].pcieDpmLevel =
1053                     (uint8_t) ((i < max_entry) ? i : max_entry);
1054     } else {
1055         while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1056                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1057                         (1 << (hightest_pcie_level_enabled + 1))) != 0))
1058             hightest_pcie_level_enabled++;
1059
1060         while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1061                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1062                         (1 << lowest_pcie_level_enabled)) == 0))
1063             lowest_pcie_level_enabled++;
1064
1065         while ((count < hightest_pcie_level_enabled) &&
1066                 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1067                         (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1068             count++;
1069
1070         mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1071                 hightest_pcie_level_enabled ?
1072                         (lowest_pcie_level_enabled + 1 + count) :
1073                         hightest_pcie_level_enabled;
1074
1075         /* set pcieDpmLevel to hightest_pcie_level_enabled */
1076         for (i = 2; i < dpm_table->sclk_table.count; i++)
1077             levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1078
1079         /* set pcieDpmLevel to lowest_pcie_level_enabled */
1080         levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1081
1082         /* set pcieDpmLevel to mid_pcie_level_enabled */
1083         levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1084     }
1085     /* level count will send to smc once at init smc table and never change */
1086     result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1087             (uint32_t)array_size, SMC_RAM_END);
1088
1089     return result;
1090 }
1091
1092
1093 /*
1094  * MCLK Frequency Ratio
1095  * SEQ_CG_RESP  Bit[31:24] - 0x0
1096  * Bit[27:24] \96 DDR3 Frequency ratio
1097  * 0x0 <= 100MHz,       450 < 0x8 <= 500MHz
1098  * 100 < 0x1 <= 150MHz,       500 < 0x9 <= 550MHz
1099  * 150 < 0x2 <= 200MHz,       550 < 0xA <= 600MHz
1100  * 200 < 0x3 <= 250MHz,       600 < 0xB <= 650MHz
1101  * 250 < 0x4 <= 300MHz,       650 < 0xC <= 700MHz
1102  * 300 < 0x5 <= 350MHz,       700 < 0xD <= 750MHz
1103  * 350 < 0x6 <= 400MHz,       750 < 0xE <= 800MHz
1104  * 400 < 0x7 <= 450MHz,       800 < 0xF
1105  */
1106 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
1107 {
1108     if (mem_clock <= 10000)
1109         return 0x0;
1110     if (mem_clock <= 15000)
1111         return 0x1;
1112     if (mem_clock <= 20000)
1113         return 0x2;
1114     if (mem_clock <= 25000)
1115         return 0x3;
1116     if (mem_clock <= 30000)
1117         return 0x4;
1118     if (mem_clock <= 35000)
1119         return 0x5;
1120     if (mem_clock <= 40000)
1121         return 0x6;
1122     if (mem_clock <= 45000)
1123         return 0x7;
1124     if (mem_clock <= 50000)
1125         return 0x8;
1126     if (mem_clock <= 55000)
1127         return 0x9;
1128     if (mem_clock <= 60000)
1129         return 0xa;
1130     if (mem_clock <= 65000)
1131         return 0xb;
1132     if (mem_clock <= 70000)
1133         return 0xc;
1134     if (mem_clock <= 75000)
1135         return 0xd;
1136     if (mem_clock <= 80000)
1137         return 0xe;
1138     /* mem_clock > 800MHz */
1139     return 0xf;
1140 }
1141
1142 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
1143     uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
1144 {
1145     struct pp_atomctrl_memory_clock_param mem_param;
1146     int result;
1147
1148     result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
1149     PP_ASSERT_WITH_CODE((0 == result),
1150             "Failed to get Memory PLL Dividers.",
1151             );
1152
1153     /* Save the result data to outpupt memory level structure */
1154     mclk->MclkFrequency   = clock;
1155     mclk->MclkDivider     = (uint8_t)mem_param.mpll_post_divider;
1156     mclk->FreqRange       = fiji_get_mclk_frequency_ratio(clock);
1157
1158     return result;
1159 }
1160
1161 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1162         uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
1163 {
1164     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1165     struct phm_ppt_v1_information *table_info =
1166             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1167     int result = 0;
1168     uint32_t mclk_stutter_mode_threshold = 60000;
1169     phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1170
1171     if (hwmgr->od_enabled)
1172         vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1173     else
1174         vdd_dep_table = table_info->vdd_dep_on_mclk;
1175
1176     if (vdd_dep_table) {
1177         result = fiji_get_dependency_volt_by_clk(hwmgr,
1178                 vdd_dep_table, clock,
1179                 (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
1180         PP_ASSERT_WITH_CODE((0 == result),
1181                 "can not find MinVddc voltage value from memory "
1182                 "VDDC voltage dependency table", return result);
1183     }
1184
1185     mem_level->EnabledForThrottle = 1;
1186     mem_level->EnabledForActivity = 0;
1187     mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1188     mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1189     mem_level->VoltageDownHyst = 0;
1190     mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1191     mem_level->StutterEnable = false;
1192
1193     mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1194
1195     /* enable stutter mode if all the follow condition applied
1196      * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
1197      * &(data->DisplayTiming.numExistingDisplays));
1198      */
1199     data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1200     data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1201
1202     if (mclk_stutter_mode_threshold &&
1203         (clock <= mclk_stutter_mode_threshold) &&
1204         (!data->is_uvd_enabled) &&
1205         (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1206                 STUTTER_ENABLE) & 0x1))
1207         mem_level->StutterEnable = true;
1208
1209     result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
1210     if (!result) {
1211         CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1212         CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1213         CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1214         CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1215     }
1216     return result;
1217 }
1218
1219 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1220 {
1221     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1222     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1223     struct smu7_dpm_table *dpm_table = &data->dpm_table;
1224     int result;
1225     /* populate MCLK dpm table to SMU7 */
1226     uint32_t array = smu_data->smu7_data.dpm_table_start +
1227             offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
1228     uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
1229             SMU73_MAX_LEVELS_MEMORY;
1230     struct SMU73_Discrete_MemoryLevel *levels =
1231             smu_data->smc_state_table.MemoryLevel;
1232     uint32_t i;
1233
1234     for (i = 0; i < dpm_table->mclk_table.count; i++) {
1235         PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1236                 "can not populate memory level as memory clock is zero",
1237                 return -EINVAL);
1238         result = fiji_populate_single_memory_level(hwmgr,
1239                 dpm_table->mclk_table.dpm_levels[i].value,
1240                 &levels[i]);
1241         if (result)
1242             return result;
1243     }
1244
1245     /* Only enable level 0 for now. */
1246     levels[0].EnabledForActivity = 1;
1247
1248     /* in order to prevent MC activity from stutter mode to push DPM up.
1249      * the UVD change complements this by putting the MCLK in
1250      * a higher state by default such that we are not effected by
1251      * up threshold or and MCLK DPM latency.
1252      */
1253     levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
1254     CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
1255
1256     smu_data->smc_state_table.MemoryDpmLevelCount =
1257             (uint8_t)dpm_table->mclk_table.count;
1258     data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1259             phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1260     /* set highest level watermark to high */
1261     levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1262             PPSMC_DISPLAY_WATERMARK_HIGH;
1263
1264     /* level count will send to smc once at init smc table and never change */
1265     result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1266             (uint32_t)array_size, SMC_RAM_END);
1267
1268     return result;
1269 }
1270
1271 static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1272         uint32_t mclk, SMIO_Pattern *smio_pat)
1273 {
1274     const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1275     struct phm_ppt_v1_information *table_info =
1276             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1277     uint32_t i = 0;
1278
1279     if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1280         /* find mvdd value which clock is more than request */
1281         for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1282             if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1283                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1284                 break;
1285             }
1286         }
1287         PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1288                 "MVDD Voltage is outside the supported range.",
1289                 return -EINVAL);
1290     } else
1291         return -EINVAL;
1292
1293     return 0;
1294 }
1295
1296 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1297         SMU73_Discrete_DpmTable *table)
1298 {
1299     int result = 0;
1300     const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1301     struct phm_ppt_v1_information *table_info =
1302             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1303     struct pp_atomctrl_clock_dividers_vi dividers;
1304     SMIO_Pattern vol_level;
1305     uint32_t mvdd;
1306     uint16_t us_mvdd;
1307     uint32_t spll_func_cntl    = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1308     uint32_t spll_func_cntl_2  = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
1309
1310     table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1311
1312     if (!data->sclk_dpm_key_disabled) {
1313         /* Get MinVoltage and Frequency from DPM0,
1314          * already converted to SMC_UL */
1315         table->ACPILevel.SclkFrequency =
1316                 data->dpm_table.sclk_table.dpm_levels[0].value;
1317         result = fiji_get_dependency_volt_by_clk(hwmgr,
1318                 table_info->vdd_dep_on_sclk,
1319                 table->ACPILevel.SclkFrequency,
1320                 (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd);
1321         PP_ASSERT_WITH_CODE((0 == result),
1322                 "Cannot find ACPI VDDC voltage value " \
1323                 "in Clock Dependency Table",
1324                 );
1325     } else {
1326         table->ACPILevel.SclkFrequency =
1327                 data->vbios_boot_state.sclk_bootup_value;
1328         table->ACPILevel.MinVoltage =
1329                 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
1330     }
1331
1332     /* get the engine clock dividers for this clock value */
1333     result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
1334             table->ACPILevel.SclkFrequency,  &dividers);
1335     PP_ASSERT_WITH_CODE(result == 0,
1336             "Error retrieving Engine Clock dividers from VBIOS.",
1337             return result);
1338
1339     table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1340     table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1341     table->ACPILevel.DeepSleepDivId = 0;
1342
1343     spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1344             SPLL_PWRON, 0);
1345     spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1346             SPLL_RESET, 1);
1347     spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
1348             SCLK_MUX_SEL, 4);
1349
1350     table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1351     table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1352     table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1353     table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1354     table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1355     table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1356     table->ACPILevel.CcPwrDynRm = 0;
1357     table->ACPILevel.CcPwrDynRm1 = 0;
1358
1359     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1360     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1361     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1362     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1363     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1364     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1365     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1366     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1367     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1368     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1369     CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1370
1371     if (!data->mclk_dpm_key_disabled) {
1372         /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1373         table->MemoryACPILevel.MclkFrequency =
1374                 data->dpm_table.mclk_table.dpm_levels[0].value;
1375         result = fiji_get_dependency_volt_by_clk(hwmgr,
1376                 table_info->vdd_dep_on_mclk,
1377                 table->MemoryACPILevel.MclkFrequency,
1378             (uint32_t *)(&table->MemoryACPILevel.MinVoltage), &mvdd);
1379         PP_ASSERT_WITH_CODE((0 == result),
1380                 "Cannot find ACPI VDDCI voltage value in Clock Dependency Table",
1381                 );
1382     } else {
1383         table->MemoryACPILevel.MclkFrequency =
1384                 data->vbios_boot_state.mclk_bootup_value;
1385         table->MemoryACPILevel.MinVoltage =
1386                 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
1387     }
1388
1389     us_mvdd = 0;
1390     if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1391             (data->mclk_dpm_key_disabled))
1392         us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1393     else {
1394         if (!fiji_populate_mvdd_value(hwmgr,
1395                 data->dpm_table.mclk_table.dpm_levels[0].value,
1396                 &vol_level))
1397             us_mvdd = vol_level.Voltage;
1398     }
1399
1400     table->MemoryACPILevel.MinMvdd =
1401             PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
1402
1403     table->MemoryACPILevel.EnabledForThrottle = 0;
1404     table->MemoryACPILevel.EnabledForActivity = 0;
1405     table->MemoryACPILevel.UpHyst = 0;
1406     table->MemoryACPILevel.DownHyst = 100;
1407     table->MemoryACPILevel.VoltageDownHyst = 0;
1408     table->MemoryACPILevel.ActivityLevel =
1409             PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1410
1411     table->MemoryACPILevel.StutterEnable = false;
1412     CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1413     CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1414
1415     return result;
1416 }
1417
1418 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1419         SMU73_Discrete_DpmTable *table)
1420 {
1421     int result = -EINVAL;
1422     uint8_t count;
1423     struct pp_atomctrl_clock_dividers_vi dividers;
1424     struct phm_ppt_v1_information *table_info =
1425             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1426     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1427             table_info->mm_dep_table;
1428
1429     table->VceLevelCount = (uint8_t)(mm_table->count);
1430     table->VceBootLevel = 0;
1431
1432     for (count = 0; count < table->VceLevelCount; count++) {
1433         table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1434         table->VceLevel[count].MinVoltage = 0;
1435         table->VceLevel[count].MinVoltage |=
1436                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1437         table->VceLevel[count].MinVoltage |=
1438                 ((mm_table->entries[count].vddc - VDDC_VDDCI_DELTA) *
1439                         VOLTAGE_SCALE) << VDDCI_SHIFT;
1440         table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1441
1442         /*retrieve divider value for VBIOS */
1443         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1444                 table->VceLevel[count].Frequency, &dividers);
1445         PP_ASSERT_WITH_CODE((0 == result),
1446                 "can not find divide id for VCE engine clock",
1447                 return result);
1448
1449         table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1450
1451         CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1452         CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1453     }
1454     return result;
1455 }
1456
1457 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
1458         SMU73_Discrete_DpmTable *table)
1459 {
1460     int result = -EINVAL;
1461     uint8_t count;
1462     struct pp_atomctrl_clock_dividers_vi dividers;
1463     struct phm_ppt_v1_information *table_info =
1464             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1465     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1466             table_info->mm_dep_table;
1467
1468     table->AcpLevelCount = (uint8_t)(mm_table->count);
1469     table->AcpBootLevel = 0;
1470
1471     for (count = 0; count < table->AcpLevelCount; count++) {
1472         table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
1473         table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1474                 VOLTAGE_SCALE) << VDDC_SHIFT;
1475         table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1476                 VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1477         table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1478
1479         /* retrieve divider value for VBIOS */
1480         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1481                 table->AcpLevel[count].Frequency, &dividers);
1482         PP_ASSERT_WITH_CODE((0 == result),
1483                 "can not find divide id for engine clock", return result);
1484
1485         table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1486
1487         CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1488         CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
1489     }
1490     return result;
1491 }
1492
1493 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1494         int32_t eng_clock, int32_t mem_clock,
1495         struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
1496 {
1497     uint32_t dram_timing;
1498     uint32_t dram_timing2;
1499     uint32_t burstTime;
1500     ULONG trrds, trrdl;
1501     int result;
1502
1503     result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1504             eng_clock, mem_clock);
1505     PP_ASSERT_WITH_CODE(result == 0,
1506             "Error calling VBIOS to set DRAM_TIMING.", return result);
1507
1508     dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1509     dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1510     burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1511
1512     trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
1513     trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
1514
1515     arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1516     arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1517     arb_regs->McArbBurstTime   = (uint8_t)burstTime;
1518     arb_regs->TRRDS            = (uint8_t)trrds;
1519     arb_regs->TRRDL            = (uint8_t)trrdl;
1520
1521     return 0;
1522 }
1523
1524 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1525 {
1526     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1527     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1528     struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
1529     uint32_t i, j;
1530     int result = 0;
1531
1532     for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
1533         for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
1534             result = fiji_populate_memory_timing_parameters(hwmgr,
1535                     data->dpm_table.sclk_table.dpm_levels[i].value,
1536                     data->dpm_table.mclk_table.dpm_levels[j].value,
1537                     &arb_regs.entries[i][j]);
1538             if (result)
1539                 break;
1540         }
1541     }
1542
1543     if (!result)
1544         result = smu7_copy_bytes_to_smc(
1545                 hwmgr,
1546                 smu_data->smu7_data.arb_table_start,
1547                 (uint8_t *)&arb_regs,
1548                 sizeof(SMU73_Discrete_MCArbDramTimingTable),
1549                 SMC_RAM_END);
1550     return result;
1551 }
1552
1553 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1554         struct SMU73_Discrete_DpmTable *table)
1555 {
1556     int result = -EINVAL;
1557     uint8_t count;
1558     struct pp_atomctrl_clock_dividers_vi dividers;
1559     struct phm_ppt_v1_information *table_info =
1560             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1561     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1562             table_info->mm_dep_table;
1563
1564     table->UvdLevelCount = (uint8_t)(mm_table->count);
1565     table->UvdBootLevel = 0;
1566
1567     for (count = 0; count < table->UvdLevelCount; count++) {
1568         table->UvdLevel[count].MinVoltage = 0;
1569         table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1570         table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1571         table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1572                 VOLTAGE_SCALE) << VDDC_SHIFT;
1573         table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
1574                 VDDC_VDDCI_DELTA) * VOLTAGE_SCALE) << VDDCI_SHIFT;
1575         table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1576
1577         /* retrieve divider value for VBIOS */
1578         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1579                 table->UvdLevel[count].VclkFrequency, &dividers);
1580         PP_ASSERT_WITH_CODE((0 == result),
1581                 "can not find divide id for Vclk clock", return result);
1582
1583         table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1584
1585         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1586                 table->UvdLevel[count].DclkFrequency, &dividers);
1587         PP_ASSERT_WITH_CODE((0 == result),
1588                 "can not find divide id for Dclk clock", return result);
1589
1590         table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1591
1592         CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1593         CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1594         CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1595
1596     }
1597     return result;
1598 }
1599
1600 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1601         struct SMU73_Discrete_DpmTable *table)
1602 {
1603     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1604
1605     table->GraphicsBootLevel = 0;
1606     table->MemoryBootLevel = 0;
1607
1608     /* find boot level from dpm table */
1609     phm_find_boot_level(&(data->dpm_table.sclk_table),
1610                 data->vbios_boot_state.sclk_bootup_value,
1611                 (uint32_t *)&(table->GraphicsBootLevel));
1612
1613     phm_find_boot_level(&(data->dpm_table.mclk_table),
1614                 data->vbios_boot_state.mclk_bootup_value,
1615                 (uint32_t *)&(table->MemoryBootLevel));
1616
1617     table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1618             VOLTAGE_SCALE;
1619     table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1620             VOLTAGE_SCALE;
1621     table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1622             VOLTAGE_SCALE;
1623
1624     CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1625     CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1626     CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1627
1628     return 0;
1629 }
1630
1631 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1632 {
1633     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1634     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1635     struct phm_ppt_v1_information *table_info =
1636             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1637     uint8_t count, level;
1638
1639     count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1640     for (level = 0; level < count; level++) {
1641         if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1642                 data->vbios_boot_state.sclk_bootup_value) {
1643             smu_data->smc_state_table.GraphicsBootLevel = level;
1644             break;
1645         }
1646     }
1647
1648     count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1649     for (level = 0; level < count; level++) {
1650         if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1651                 data->vbios_boot_state.mclk_bootup_value) {
1652             smu_data->smc_state_table.MemoryBootLevel = level;
1653             break;
1654         }
1655     }
1656
1657     return 0;
1658 }
1659
1660 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1661 {
1662     uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
1663             volt_with_cks, value;
1664     uint16_t clock_freq_u16;
1665     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1666     uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
1667             volt_offset = 0;
1668     struct phm_ppt_v1_information *table_info =
1669             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1670     struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1671             table_info->vdd_dep_on_sclk;
1672
1673     stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1674
1675     /* Read SMU_Eefuse to read and calculate RO and determine
1676      * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1677      */
1678     efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1679             ixSMU_EFUSE_0 + (146 * 4));
1680     efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1681             ixSMU_EFUSE_0 + (148 * 4));
1682     efuse &= 0xFF000000;
1683     efuse = efuse >> 24;
1684     efuse2 &= 0xF;
1685
1686     if (efuse2 == 1)
1687         ro = (2300 - 1350) * efuse / 255 + 1350;
1688     else
1689         ro = (2500 - 1000) * efuse / 255 + 1000;
1690
1691     if (ro >= 1660)
1692         type = 0;
1693     else
1694         type = 1;
1695
1696     /* Populate Stretch amount */
1697     smu_data->smc_state_table.ClockStretcherAmount = stretch_amount;
1698
1699     /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1700     for (i = 0; i < sclk_table->count; i++) {
1701         smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1702                 sclk_table->entries[i].cks_enable << i;
1703         volt_without_cks = (uint32_t)((14041 *
1704             (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
1705             (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
1706         volt_with_cks = (uint32_t)((13946 *
1707             (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
1708             (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
1709         if (volt_without_cks >= volt_with_cks)
1710             volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1711                     sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
1712         smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1713     }
1714
1715     PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1716             STRETCH_ENABLE, 0x0);
1717     PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1718             masterReset, 0x1);
1719     PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1720             staticEnable, 0x1);
1721     PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
1722             masterReset, 0x0);
1723
1724     /* Populate CKS Lookup Table */
1725     if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1726         stretch_amount2 = 0;
1727     else if (stretch_amount == 3 || stretch_amount == 4)
1728         stretch_amount2 = 1;
1729     else {
1730         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1731                 PHM_PlatformCaps_ClockStretcher);
1732         PP_ASSERT_WITH_CODE(false,
1733                 "Stretch Amount in PPTable not supported",
1734                 return -EINVAL);
1735     }
1736
1737     value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1738             ixPWR_CKS_CNTL);
1739     value &= 0xFFC2FF87;
1740     smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
1741             fiji_clock_stretcher_lookup_table[stretch_amount2][0];
1742     smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
1743             fiji_clock_stretcher_lookup_table[stretch_amount2][1];
1744     clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table.
1745             GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1].
1746             SclkFrequency) / 100);
1747     if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
1748             clock_freq_u16 &&
1749         fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
1750             clock_freq_u16) {
1751         /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
1752         value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
1753         /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
1754         value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
1755         /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
1756         value |= (fiji_clock_stretch_amount_conversion
1757                 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
1758                  [stretch_amount]) << 3;
1759     }
1760     CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1761             CKS_LOOKUPTableEntry[0].minFreq);
1762     CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable.
1763             CKS_LOOKUPTableEntry[0].maxFreq);
1764     smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
1765             fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
1766     smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
1767             (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
1768
1769     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1770             ixPWR_CKS_CNTL, value);
1771
1772     /* Populate DDT Lookup Table */
1773     for (i = 0; i < 4; i++) {
1774         /* Assign the minimum and maximum VID stored
1775          * in the last row of Clock Stretcher Voltage Table.
1776          */
1777         smu_data->smc_state_table.ClockStretcherDataTable.
1778         ClockStretcherDataTableEntry[i].minVID =
1779                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
1780         smu_data->smc_state_table.ClockStretcherDataTable.
1781         ClockStretcherDataTableEntry[i].maxVID =
1782                 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
1783         /* Loop through each SCLK and check the frequency
1784          * to see if it lies within the frequency for clock stretcher.
1785          */
1786         for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) {
1787             cks_setting = 0;
1788             clock_freq = PP_SMC_TO_HOST_UL(
1789                     smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency);
1790             /* Check the allowed frequency against the sclk level[j].
1791              *  Sclk's endianness has already been converted,
1792              *  and it's in 10Khz unit,
1793              *  as opposed to Data table, which is in Mhz unit.
1794              */
1795             if (clock_freq >=
1796                     (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
1797                 cks_setting |= 0x2;
1798                 if (clock_freq <
1799                         (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
1800                     cks_setting |= 0x1;
1801             }
1802             smu_data->smc_state_table.ClockStretcherDataTable.
1803             ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
1804         }
1805         CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.
1806                 ClockStretcherDataTable.
1807                 ClockStretcherDataTableEntry[i].setting);
1808     }
1809
1810     value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1811     value &= 0xFFFFFFFE;
1812     cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1813
1814     return 0;
1815 }
1816
1817 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
1818         struct SMU73_Discrete_DpmTable *table)
1819 {
1820     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1821     uint16_t config;
1822
1823     config = VR_MERGED_WITH_VDDC;
1824     table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1825
1826     /* Set Vddc Voltage Controller */
1827     if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1828         config = VR_SVI2_PLANE_1;
1829         table->VRConfig |= config;
1830     } else {
1831         PP_ASSERT_WITH_CODE(false,
1832                 "VDDC should be on SVI2 control in merged mode!",
1833                 );
1834     }
1835     /* Set Vddci Voltage Controller */
1836     if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1837         config = VR_SVI2_PLANE_2;  /* only in merged mode */
1838         table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1839     } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1840         config = VR_SMIO_PATTERN_1;
1841         table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1842     } else {
1843         config = VR_STATIC_VOLTAGE;
1844         table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1845     }
1846     /* Set Mvdd Voltage Controller */
1847     if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1848         config = VR_SVI2_PLANE_2;
1849         table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1850     } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1851         config = VR_SMIO_PATTERN_2;
1852         table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1853     } else {
1854         config = VR_STATIC_VOLTAGE;
1855         table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1856     }
1857
1858     return 0;
1859 }
1860
1861 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
1862 {
1863     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1864     uint32_t tmp;
1865     int result;
1866
1867     /* This is a read-modify-write on the first byte of the ARB table.
1868      * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
1869      * is the field 'current'.
1870      * This solution is ugly, but we never write the whole table only
1871      * individual fields in it.
1872      * In reality this field should not be in that structure
1873      * but in a soft register.
1874      */
1875     result = smu7_read_smc_sram_dword(hwmgr,
1876             smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END);
1877
1878     if (result)
1879         return result;
1880
1881     tmp &= 0x00FFFFFF;
1882     tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
1883
1884     return smu7_write_smc_sram_dword(hwmgr,
1885             smu_data->smu7_data.arb_table_start,  tmp, SMC_RAM_END);
1886 }
1887
1888 static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
1889 {
1890     pp_atomctrl_voltage_table param_led_dpm;
1891     int result = 0;
1892     u32 mask = 0;
1893
1894     result = atomctrl_get_voltage_table_v3(hwmgr,
1895                            VOLTAGE_TYPE_LEDDPM, VOLTAGE_OBJ_GPIO_LUT,
1896                            &param_led_dpm);
1897     if (result == 0) {
1898         int i, j;
1899         u32 tmp = param_led_dpm.mask_low;
1900
1901         for (i = 0, j = 0; i < 32; i++) {
1902             if (tmp & 1) {
1903                 mask |= (i << (8 * j));
1904                 if (++j >= 3)
1905                     break;
1906             }
1907             tmp >>= 1;
1908         }
1909     }
1910     if (mask)
1911         smum_send_msg_to_smc_with_parameter(hwmgr,
1912                             PPSMC_MSG_LedConfig,
1913                             mask,
1914                             NULL);
1915     return 0;
1916 }
1917
1918 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
1919 {
1920     int result;
1921     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1922     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
1923     struct phm_ppt_v1_information *table_info =
1924             (struct phm_ppt_v1_information *)(hwmgr->pptable);
1925     struct SMU73_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1926     uint8_t i;
1927     struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1928
1929     fiji_initialize_power_tune_defaults(hwmgr);
1930
1931     if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control)
1932         fiji_populate_smc_voltage_tables(hwmgr, table);
1933
1934     table->SystemFlags = 0;
1935
1936     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1937             PHM_PlatformCaps_AutomaticDCTransition))
1938         table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1939
1940     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1941             PHM_PlatformCaps_StepVddc))
1942         table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1943
1944     if (data->is_memory_gddr5)
1945         table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1946
1947     if (data->ulv_supported && table_info->us_ulv_voltage_offset) {
1948         result = fiji_populate_ulv_state(hwmgr, table);
1949         PP_ASSERT_WITH_CODE(0 == result,
1950                 "Failed to initialize ULV state!", return result);
1951         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1952                 ixCG_ULV_PARAMETER, 0x40035);
1953     }
1954
1955     result = fiji_populate_smc_link_level(hwmgr, table);
1956     PP_ASSERT_WITH_CODE(0 == result,
1957             "Failed to initialize Link Level!", return result);
1958
1959     result = fiji_populate_all_graphic_levels(hwmgr);
1960     PP_ASSERT_WITH_CODE(0 == result,
1961             "Failed to initialize Graphics Level!", return result);
1962
1963     result = fiji_populate_all_memory_levels(hwmgr);
1964     PP_ASSERT_WITH_CODE(0 == result,
1965             "Failed to initialize Memory Level!", return result);
1966
1967     result = fiji_populate_smc_acpi_level(hwmgr, table);
1968     PP_ASSERT_WITH_CODE(0 == result,
1969             "Failed to initialize ACPI Level!", return result);
1970
1971     result = fiji_populate_smc_vce_level(hwmgr, table);
1972     PP_ASSERT_WITH_CODE(0 == result,
1973             "Failed to initialize VCE Level!", return result);
1974
1975     result = fiji_populate_smc_acp_level(hwmgr, table);
1976     PP_ASSERT_WITH_CODE(0 == result,
1977             "Failed to initialize ACP Level!", return result);
1978
1979     /* Since only the initial state is completely set up at this point
1980      * (the other states are just copies of the boot state) we only
1981      * need to populate the  ARB settings for the initial state.
1982      */
1983     result = fiji_program_memory_timing_parameters(hwmgr);
1984     PP_ASSERT_WITH_CODE(0 == result,
1985             "Failed to Write ARB settings for the initial state.", return result);
1986
1987     result = fiji_populate_smc_uvd_level(hwmgr, table);
1988     PP_ASSERT_WITH_CODE(0 == result,
1989             "Failed to initialize UVD Level!", return result);
1990
1991     result = fiji_populate_smc_boot_level(hwmgr, table);
1992     PP_ASSERT_WITH_CODE(0 == result,
1993             "Failed to initialize Boot Level!", return result);
1994
1995     result = fiji_populate_smc_initailial_state(hwmgr);
1996     PP_ASSERT_WITH_CODE(0 == result,
1997             "Failed to initialize Boot State!", return result);
1998
1999     result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2000     PP_ASSERT_WITH_CODE(0 == result,
2001             "Failed to populate BAPM Parameters!", return result);
2002
2003     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2004             PHM_PlatformCaps_ClockStretcher)) {
2005         result = fiji_populate_clock_stretcher_data_table(hwmgr);
2006         PP_ASSERT_WITH_CODE(0 == result,
2007                 "Failed to populate Clock Stretcher Data Table!",
2008                 return result);
2009     }
2010
2011     table->GraphicsVoltageChangeEnable  = 1;
2012     table->GraphicsThermThrottleEnable  = 1;
2013     table->GraphicsInterval = 1;
2014     table->VoltageInterval  = 1;
2015     table->ThermalInterval  = 1;
2016     table->TemperatureLimitHigh =
2017             table_info->cac_dtp_table->usTargetOperatingTemp *
2018             SMU7_Q88_FORMAT_CONVERSION_UNIT;
2019     table->TemperatureLimitLow  =
2020             (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2021             SMU7_Q88_FORMAT_CONVERSION_UNIT;
2022     table->MemoryVoltageChangeEnable = 1;
2023     table->MemoryInterval = 1;
2024     table->VoltageResponseTime = 0;
2025     table->PhaseResponseTime = 0;
2026     table->MemoryThermThrottleEnable = 1;
2027     table->PCIeBootLinkLevel = 0;      /* 0:Gen1 1:Gen2 2:Gen3*/
2028     table->PCIeGenInterval = 1;
2029     table->VRConfig = 0;
2030
2031     result = fiji_populate_vr_config(hwmgr, table);
2032     PP_ASSERT_WITH_CODE(0 == result,
2033             "Failed to populate VRConfig setting!", return result);
2034     data->vr_config = table->VRConfig;
2035     table->ThermGpio = 17;
2036     table->SclkStepSize = 0x4000;
2037
2038     if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2039         table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2040         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2041                 PHM_PlatformCaps_RegulatorHot);
2042     } else {
2043         table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2044         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2045                 PHM_PlatformCaps_RegulatorHot);
2046     }
2047
2048     if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2049             &gpio_pin)) {
2050         table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2051         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2052                 PHM_PlatformCaps_AutomaticDCTransition);
2053     } else {
2054         table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2055         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2056                 PHM_PlatformCaps_AutomaticDCTransition);
2057     }
2058
2059     /* Thermal Output GPIO */
2060     if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2061             &gpio_pin)) {
2062         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2063                 PHM_PlatformCaps_ThermalOutGPIO);
2064
2065         table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2066
2067         /* For porlarity read GPIOPAD_A with assigned Gpio pin
2068          * since VBIOS will program this register to set 'inactive state',
2069          * driver can then determine 'active state' from this and
2070          * program SMU with correct polarity
2071          */
2072         table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2073                 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2074         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2075
2076         /* if required, combine VRHot/PCC with thermal out GPIO */
2077         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2078                 PHM_PlatformCaps_RegulatorHot) &&
2079             phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2080                     PHM_PlatformCaps_CombinePCCWithThermalSignal))
2081             table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2082     } else {
2083         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2084                 PHM_PlatformCaps_ThermalOutGPIO);
2085         table->ThermOutGpio = 17;
2086         table->ThermOutPolarity = 1;
2087         table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2088     }
2089
2090     for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
2091         table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2092
2093     CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2094     CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2095     CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2096     CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2097     CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2098     CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2099     CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2100     CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2101     CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2102
2103     /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2104     result = smu7_copy_bytes_to_smc(hwmgr,
2105             smu_data->smu7_data.dpm_table_start +
2106             offsetof(SMU73_Discrete_DpmTable, SystemFlags),
2107             (uint8_t *)&(table->SystemFlags),
2108             sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
2109             SMC_RAM_END);
2110     PP_ASSERT_WITH_CODE(0 == result,
2111             "Failed to upload dpm data to SMC memory!", return result);
2112
2113     result = fiji_init_arb_table_index(hwmgr);
2114     PP_ASSERT_WITH_CODE(0 == result,
2115             "Failed to upload arb data to SMC memory!", return result);
2116
2117     result = fiji_populate_pm_fuses(hwmgr);
2118     PP_ASSERT_WITH_CODE(0 == result,
2119             "Failed to  populate PM fuses to SMC memory!", return result);
2120
2121     result = fiji_setup_dpm_led_config(hwmgr);
2122     PP_ASSERT_WITH_CODE(0 == result,
2123                 "Failed to setup dpm led config", return result);
2124
2125     return 0;
2126 }
2127
2128 static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2129 {
2130     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2131
2132     SMU73_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2133     uint32_t duty100;
2134     uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2135     uint16_t fdo_min, slope1, slope2;
2136     uint32_t reference_clock;
2137     int res;
2138     uint64_t tmp64;
2139
2140     if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2141         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2142             PHM_PlatformCaps_MicrocodeFanControl);
2143         return 0;
2144     }
2145
2146     if (smu_data->smu7_data.fan_table_start == 0) {
2147         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2148                 PHM_PlatformCaps_MicrocodeFanControl);
2149         return 0;
2150     }
2151
2152     duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2153             CG_FDO_CTRL1, FMAX_DUTY100);
2154
2155     if (duty100 == 0) {
2156         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2157                 PHM_PlatformCaps_MicrocodeFanControl);
2158         return 0;
2159     }
2160
2161     tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2162             usPWMMin * duty100;
2163     do_div(tmp64, 10000);
2164     fdo_min = (uint16_t)tmp64;
2165
2166     t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2167             hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2168     t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2169             hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2170
2171     pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2172             hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2173     pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2174             hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2175
2176     slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2177     slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2178
2179     fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2180             thermal_controller.advanceFanControlParameters.usTMin) / 100);
2181     fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2182             thermal_controller.advanceFanControlParameters.usTMed) / 100);
2183     fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2184             thermal_controller.advanceFanControlParameters.usTMax) / 100);
2185
2186     fan_table.Slope1 = cpu_to_be16(slope1);
2187     fan_table.Slope2 = cpu_to_be16(slope2);
2188
2189     fan_table.FdoMin = cpu_to_be16(fdo_min);
2190
2191     fan_table.HystDown = cpu_to_be16(hwmgr->
2192             thermal_controller.advanceFanControlParameters.ucTHyst);
2193
2194     fan_table.HystUp = cpu_to_be16(1);
2195
2196     fan_table.HystSlope = cpu_to_be16(1);
2197
2198     fan_table.TempRespLim = cpu_to_be16(5);
2199
2200     reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2201
2202     fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2203             thermal_controller.advanceFanControlParameters.ulCycleDelay *
2204             reference_clock) / 1600);
2205
2206     fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2207
2208     fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2209             hwmgr->device, CGS_IND_REG__SMC,
2210             CG_MULT_THERMAL_CTRL, TEMP_SEL);
2211
2212     res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2213             (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2214             SMC_RAM_END);
2215
2216     if (!res && hwmgr->thermal_controller.
2217             advanceFanControlParameters.ucMinimumPWMLimit)
2218         res = smum_send_msg_to_smc_with_parameter(hwmgr,
2219                 PPSMC_MSG_SetFanMinPwm,
2220                 hwmgr->thermal_controller.
2221                 advanceFanControlParameters.ucMinimumPWMLimit,
2222                 NULL);
2223
2224     if (!res && hwmgr->thermal_controller.
2225             advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2226         res = smum_send_msg_to_smc_with_parameter(hwmgr,
2227                 PPSMC_MSG_SetFanSclkTarget,
2228                 hwmgr->thermal_controller.
2229                 advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2230                 NULL);
2231
2232     if (res)
2233         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2234                 PHM_PlatformCaps_MicrocodeFanControl);
2235
2236     return 0;
2237 }
2238
2239
2240 static int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2241 {
2242     if (!hwmgr->avfs_supported)
2243         return 0;
2244
2245     smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2246
2247     return 0;
2248 }
2249
2250 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2251 {
2252     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2253
2254     if (data->need_update_smu7_dpm_table &
2255         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2256         return fiji_program_memory_timing_parameters(hwmgr);
2257
2258     return 0;
2259 }
2260
2261 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2262 {
2263     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2264     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2265
2266     int result = 0;
2267     uint32_t low_sclk_interrupt_threshold = 0;
2268
2269     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2270             PHM_PlatformCaps_SclkThrottleLowNotification)
2271         && (data->low_sclk_interrupt_threshold != 0)) {
2272         low_sclk_interrupt_threshold =
2273                 data->low_sclk_interrupt_threshold;
2274
2275         CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2276
2277         result = smu7_copy_bytes_to_smc(
2278                 hwmgr,
2279                 smu_data->smu7_data.dpm_table_start +
2280                 offsetof(SMU73_Discrete_DpmTable,
2281                     LowSclkInterruptThreshold),
2282                 (uint8_t *)&low_sclk_interrupt_threshold,
2283                 sizeof(uint32_t),
2284                 SMC_RAM_END);
2285     }
2286     result = fiji_program_mem_timing_parameters(hwmgr);
2287     PP_ASSERT_WITH_CODE((result == 0),
2288             "Failed to program memory timing parameters!",
2289             );
2290     return result;
2291 }
2292
2293 static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member)
2294 {
2295     switch (type) {
2296     case SMU_SoftRegisters:
2297         switch (member) {
2298         case HandshakeDisables:
2299             return offsetof(SMU73_SoftRegisters, HandshakeDisables);
2300         case VoltageChangeTimeout:
2301             return offsetof(SMU73_SoftRegisters, VoltageChangeTimeout);
2302         case AverageGraphicsActivity:
2303             return offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
2304         case AverageMemoryActivity:
2305             return offsetof(SMU73_SoftRegisters, AverageMemoryActivity);
2306         case PreVBlankGap:
2307             return offsetof(SMU73_SoftRegisters, PreVBlankGap);
2308         case VBlankTimeout:
2309             return offsetof(SMU73_SoftRegisters, VBlankTimeout);
2310         case UcodeLoadStatus:
2311             return offsetof(SMU73_SoftRegisters, UcodeLoadStatus);
2312         case DRAM_LOG_ADDR_H:
2313             return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_H);
2314         case DRAM_LOG_ADDR_L:
2315             return offsetof(SMU73_SoftRegisters, DRAM_LOG_ADDR_L);
2316         case DRAM_LOG_PHY_ADDR_H:
2317             return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2318         case DRAM_LOG_PHY_ADDR_L:
2319             return offsetof(SMU73_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2320         case DRAM_LOG_BUFF_SIZE:
2321             return offsetof(SMU73_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2322         }
2323         break;
2324     case SMU_Discrete_DpmTable:
2325         switch (member) {
2326         case UvdBootLevel:
2327             return offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
2328         case VceBootLevel:
2329             return offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
2330         case LowSclkInterruptThreshold:
2331             return offsetof(SMU73_Discrete_DpmTable, LowSclkInterruptThreshold);
2332         }
2333         break;
2334     }
2335     pr_warn("can't get the offset of type %x member %x\n", type, member);
2336     return 0;
2337 }
2338
2339 static uint32_t fiji_get_mac_definition(uint32_t value)
2340 {
2341     switch (value) {
2342     case SMU_MAX_LEVELS_GRAPHICS:
2343         return SMU73_MAX_LEVELS_GRAPHICS;
2344     case SMU_MAX_LEVELS_MEMORY:
2345         return SMU73_MAX_LEVELS_MEMORY;
2346     case SMU_MAX_LEVELS_LINK:
2347         return SMU73_MAX_LEVELS_LINK;
2348     case SMU_MAX_ENTRIES_SMIO:
2349         return SMU73_MAX_ENTRIES_SMIO;
2350     case SMU_MAX_LEVELS_VDDC:
2351         return SMU73_MAX_LEVELS_VDDC;
2352     case SMU_MAX_LEVELS_VDDGFX:
2353         return SMU73_MAX_LEVELS_VDDGFX;
2354     case SMU_MAX_LEVELS_VDDCI:
2355         return SMU73_MAX_LEVELS_VDDCI;
2356     case SMU_MAX_LEVELS_MVDD:
2357         return SMU73_MAX_LEVELS_MVDD;
2358     }
2359
2360     pr_warn("can't get the mac of %x\n", value);
2361     return 0;
2362 }
2363
2364
2365 static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2366 {
2367     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2368     uint32_t mm_boot_level_offset, mm_boot_level_value;
2369     struct phm_ppt_v1_information *table_info =
2370             (struct phm_ppt_v1_information *)(hwmgr->pptable);
2371
2372     smu_data->smc_state_table.UvdBootLevel = 0;
2373     if (table_info->mm_dep_table->count > 0)
2374         smu_data->smc_state_table.UvdBootLevel =
2375                 (uint8_t) (table_info->mm_dep_table->count - 1);
2376     mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable,
2377                         UvdBootLevel);
2378     mm_boot_level_offset /= 4;
2379     mm_boot_level_offset *= 4;
2380     mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2381             CGS_IND_REG__SMC, mm_boot_level_offset);
2382     mm_boot_level_value &= 0x00FFFFFF;
2383     mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2384     cgs_write_ind_register(hwmgr->device,
2385             CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2386
2387     if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2388             PHM_PlatformCaps_UVDDPM) ||
2389         phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2390             PHM_PlatformCaps_StablePState))
2391         smum_send_msg_to_smc_with_parameter(hwmgr,
2392                 PPSMC_MSG_UVDDPM_SetEnabledMask,
2393                 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2394                 NULL);
2395     return 0;
2396 }
2397
2398 static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2399 {
2400     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2401     uint32_t mm_boot_level_offset, mm_boot_level_value;
2402     struct phm_ppt_v1_information *table_info =
2403             (struct phm_ppt_v1_information *)(hwmgr->pptable);
2404
2405     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2406                     PHM_PlatformCaps_StablePState))
2407         smu_data->smc_state_table.VceBootLevel =
2408             (uint8_t) (table_info->mm_dep_table->count - 1);
2409     else
2410         smu_data->smc_state_table.VceBootLevel = 0;
2411
2412     mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2413                     offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
2414     mm_boot_level_offset /= 4;
2415     mm_boot_level_offset *= 4;
2416     mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2417             CGS_IND_REG__SMC, mm_boot_level_offset);
2418     mm_boot_level_value &= 0xFF00FFFF;
2419     mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2420     cgs_write_ind_register(hwmgr->device,
2421             CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2422
2423     if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2424         smum_send_msg_to_smc_with_parameter(hwmgr,
2425                 PPSMC_MSG_VCEDPM_SetEnabledMask,
2426                 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2427                 NULL);
2428     return 0;
2429 }
2430
2431 static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2432 {
2433     switch (type) {
2434     case SMU_UVD_TABLE:
2435         fiji_update_uvd_smc_table(hwmgr);
2436         break;
2437     case SMU_VCE_TABLE:
2438         fiji_update_vce_smc_table(hwmgr);
2439         break;
2440     default:
2441         break;
2442     }
2443     return 0;
2444 }
2445
2446 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
2447 {
2448     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2449     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
2450     uint32_t tmp;
2451     int result;
2452     bool error = false;
2453
2454     result = smu7_read_smc_sram_dword(hwmgr,
2455             SMU7_FIRMWARE_HEADER_LOCATION +
2456             offsetof(SMU73_Firmware_Header, DpmTable),
2457             &tmp, SMC_RAM_END);
2458
2459     if (0 == result)
2460         smu_data->smu7_data.dpm_table_start = tmp;
2461
2462     error |= (0 != result);
2463
2464     result = smu7_read_smc_sram_dword(hwmgr,
2465             SMU7_FIRMWARE_HEADER_LOCATION +
2466             offsetof(SMU73_Firmware_Header, SoftRegisters),
2467             &tmp, SMC_RAM_END);
2468
2469     if (!result) {
2470         data->soft_regs_start = tmp;
2471         smu_data->smu7_data.soft_regs_start = tmp;
2472     }
2473
2474     error |= (0 != result);
2475
2476     result = smu7_read_smc_sram_dword(hwmgr,
2477             SMU7_FIRMWARE_HEADER_LOCATION +
2478             offsetof(SMU73_Firmware_Header, mcRegisterTable),
2479             &tmp, SMC_RAM_END);
2480
2481     if (!result)
2482         smu_data->smu7_data.mc_reg_table_start = tmp;
2483
2484     result = smu7_read_smc_sram_dword(hwmgr,
2485             SMU7_FIRMWARE_HEADER_LOCATION +
2486             offsetof(SMU73_Firmware_Header, FanTable),
2487             &tmp, SMC_RAM_END);
2488
2489     if (!result)
2490         smu_data->smu7_data.fan_table_start = tmp;
2491
2492     error |= (0 != result);
2493
2494     result = smu7_read_smc_sram_dword(hwmgr,
2495             SMU7_FIRMWARE_HEADER_LOCATION +
2496             offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
2497             &tmp, SMC_RAM_END);
2498
2499     if (!result)
2500         smu_data->smu7_data.arb_table_start = tmp;
2501
2502     error |= (0 != result);
2503
2504     result = smu7_read_smc_sram_dword(hwmgr,
2505             SMU7_FIRMWARE_HEADER_LOCATION +
2506             offsetof(SMU73_Firmware_Header, Version),
2507             &tmp, SMC_RAM_END);
2508
2509     if (!result)
2510         hwmgr->microcode_version_info.SMC = tmp;
2511
2512     error |= (0 != result);
2513
2514     return error ? -1 : 0;
2515 }
2516
2517 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2518 {
2519
2520     /* Program additional LP registers
2521      * that are no longer programmed by VBIOS
2522      */
2523     cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
2524             cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
2525     cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
2526             cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
2527     cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
2528             cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
2529     cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
2530             cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
2531     cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
2532             cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
2533     cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
2534             cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
2535     cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
2536             cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
2537
2538     return 0;
2539 }
2540
2541 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
2542 {
2543     return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2544             CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2545             ? true : false;
2546 }
2547
2548 static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr,
2549                 void *profile_setting)
2550 {
2551     struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2552     struct fiji_smumgr *smu_data = (struct fiji_smumgr *)
2553             (hwmgr->smu_backend);
2554     struct profile_mode_setting *setting;
2555     struct SMU73_Discrete_GraphicsLevel *levels =
2556             smu_data->smc_state_table.GraphicsLevel;
2557     uint32_t array = smu_data->smu7_data.dpm_table_start +
2558             offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
2559
2560     uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2561             offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2562     struct SMU73_Discrete_MemoryLevel *mclk_levels =
2563             smu_data->smc_state_table.MemoryLevel;
2564     uint32_t i;
2565     uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2566
2567     if (profile_setting == NULL)
2568         return -EINVAL;
2569
2570     setting = (struct profile_mode_setting *)profile_setting;
2571
2572     if (setting->bupdate_sclk) {
2573         if (!data->sclk_dpm_key_disabled)
2574             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2575         for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2576             if (levels[i].ActivityLevel !=
2577                 cpu_to_be16(setting->sclk_activity)) {
2578                 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2579
2580                 clk_activity_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2581                         + offsetof(SMU73_Discrete_GraphicsLevel, ActivityLevel);
2582                 offset = clk_activity_offset & ~0x3;
2583                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2584                 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2585                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2586
2587             }
2588             if (levels[i].UpHyst != setting->sclk_up_hyst ||
2589                 levels[i].DownHyst != setting->sclk_down_hyst) {
2590                 levels[i].UpHyst = setting->sclk_up_hyst;
2591                 levels[i].DownHyst = setting->sclk_down_hyst;
2592                 up_hyst_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2593                         + offsetof(SMU73_Discrete_GraphicsLevel, UpHyst);
2594                 down_hyst_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i)
2595                         + offsetof(SMU73_Discrete_GraphicsLevel, DownHyst);
2596                 offset = up_hyst_offset & ~0x3;
2597                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2598                 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2599                 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2600                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2601             }
2602         }
2603         if (!data->sclk_dpm_key_disabled)
2604             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2605     }
2606
2607     if (setting->bupdate_mclk) {
2608         if (!data->mclk_dpm_key_disabled)
2609             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2610         for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2611             if (mclk_levels[i].ActivityLevel !=
2612                 cpu_to_be16(setting->mclk_activity)) {
2613                 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2614
2615                 clk_activity_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2616                         + offsetof(SMU73_Discrete_MemoryLevel, ActivityLevel);
2617                 offset = clk_activity_offset & ~0x3;
2618                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2619                 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2620                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2621
2622             }
2623             if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2624                 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2625                 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2626                 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2627                 up_hyst_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2628                         + offsetof(SMU73_Discrete_MemoryLevel, UpHyst);
2629                 down_hyst_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i)
2630                         + offsetof(SMU73_Discrete_MemoryLevel, DownHyst);
2631                 offset = up_hyst_offset & ~0x3;
2632                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2633                 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2634                 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2635                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2636             }
2637         }
2638         if (!data->mclk_dpm_key_disabled)
2639             smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
2640     }
2641     return 0;
2642 }
2643
2644 const struct pp_smumgr_func fiji_smu_funcs = {
2645     .name = "fiji_smu",
2646     .smu_init = &fiji_smu_init,
2647     .smu_fini = &smu7_smu_fini,
2648     .start_smu = &fiji_start_smu,
2649     .check_fw_load_finish = &smu7_check_fw_load_finish,
2650     .request_smu_load_fw = &smu7_reload_firmware,
2651     .request_smu_load_specific_fw = NULL,
2652     .send_msg_to_smc = &smu7_send_msg_to_smc,
2653     .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter,
2654     .get_argument = smu7_get_argument,
2655     .download_pptable_settings = NULL,
2656     .upload_pptable_settings = NULL,
2657     .update_smc_table = fiji_update_smc_table,
2658     .get_offsetof = fiji_get_offsetof,
2659     .process_firmware_header = fiji_process_firmware_header,
2660     .init_smc_table = fiji_init_smc_table,
2661     .update_sclk_threshold = fiji_update_sclk_threshold,
2662     .thermal_setup_fan_table = fiji_thermal_setup_fan_table,
2663     .thermal_avfs_enable = fiji_thermal_avfs_enable,
2664     .populate_all_graphic_levels = fiji_populate_all_graphic_levels,
2665     .populate_all_memory_levels = fiji_populate_all_memory_levels,
2666     .get_mac_definition = fiji_get_mac_definition,
2667     .initialize_mc_reg_table = fiji_initialize_mc_reg_table,
2668     .is_dpm_running = fiji_is_dpm_running,
2669     .is_hw_avfs_present = fiji_is_hw_avfs_present,
2670     .update_dpm_settings = fiji_update_dpm_settings,
2671 };