powerplay/smumgr/ci_smumgr.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _CI_SMUMANAGER_H_
0024 #define _CI_SMUMANAGER_H_
0025
0026 #define SMU__NUM_SCLK_DPM_STATE  8
0027 #define SMU__NUM_MCLK_DPM_LEVELS 6
0028 #define SMU__NUM_LCLK_DPM_LEVELS 8
0029 #define SMU__NUM_PCIE_DPM_LEVELS 8
0030
0031 #include "smu7_discrete.h"
0032 #include <pp_endian.h>
0033 #include "ppatomctrl.h"
0034
0035 struct ci_pt_defaults {
0036     u8 svi_load_line_en;
0037     u8 svi_load_line_vddc;
0038     u8 tdc_vddc_throttle_release_limit_perc;
0039     u8 tdc_mawt;
0040     u8 tdc_waterfall_ctl;
0041     u8 dte_ambient_temp_base;
0042     u32 display_cac;
0043     u32 bapm_temp_gradient;
0044     u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
0045     u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];
0046 };
0047
0048 struct ci_mc_reg_entry {
0049     uint32_t mclk_max;
0050     uint32_t mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0051 };
0052
0053 struct ci_mc_reg_table {
0054     uint8_t   last;
0055     uint8_t   num_entries;
0056     uint16_t  validflag;
0057     struct ci_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
0058     SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0059 };
0060
0061 struct ci_smumgr {
0062     uint32_t                             soft_regs_start;
0063     uint32_t                             dpm_table_start;
0064     uint32_t                             mc_reg_table_start;
0065     uint32_t                             fan_table_start;
0066     uint32_t                             arb_table_start;
0067     uint32_t                             ulv_setting_starts;
0068     struct SMU7_Discrete_DpmTable       smc_state_table;
0069     struct SMU7_Discrete_PmFuses  power_tune_table;
0070     const struct ci_pt_defaults  *power_tune_defaults;
0071     SMU7_Discrete_MCRegisters      mc_regs;
0072     struct ci_mc_reg_table mc_reg_table;
0073 };
0074
0075 #endif
0076