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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef VEGA12_SMU9_DRIVER_IF_H
0025 #define VEGA12_SMU9_DRIVER_IF_H
0026 
0027 /**** IMPORTANT ***
0028  * SMU TEAM: Always increment the interface version if
0029  * any structure is changed in this file
0030  */
0031 #define SMU9_DRIVER_IF_VERSION 0x10
0032 
0033 #define PPTABLE_V12_SMU_VERSION 1
0034 
0035 #define NUM_GFXCLK_DPM_LEVELS  16
0036 #define NUM_VCLK_DPM_LEVELS    8
0037 #define NUM_DCLK_DPM_LEVELS    8
0038 #define NUM_ECLK_DPM_LEVELS    8
0039 #define NUM_MP0CLK_DPM_LEVELS  2
0040 #define NUM_UCLK_DPM_LEVELS    4
0041 #define NUM_SOCCLK_DPM_LEVELS  8
0042 #define NUM_DCEFCLK_DPM_LEVELS 8
0043 #define NUM_DISPCLK_DPM_LEVELS 8
0044 #define NUM_PIXCLK_DPM_LEVELS  8
0045 #define NUM_PHYCLK_DPM_LEVELS  8
0046 #define NUM_LINK_LEVELS        2
0047 
0048 #define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
0049 #define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
0050 #define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
0051 #define MAX_ECLK_DPM_LEVEL    (NUM_ECLK_DPM_LEVELS    - 1)
0052 #define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
0053 #define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
0054 #define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
0055 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
0056 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
0057 #define MAX_PIXCLK_DPM_LEVEL  (NUM_PIXCLK_DPM_LEVELS  - 1)
0058 #define MAX_PHYCLK_DPM_LEVEL  (NUM_PHYCLK_DPM_LEVELS  - 1)
0059 #define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
0060 
0061 
0062 #define PPSMC_GeminiModeNone   0
0063 #define PPSMC_GeminiModeMaster 1
0064 #define PPSMC_GeminiModeSlave  2
0065 
0066 
0067 #define FEATURE_DPM_PREFETCHER_BIT      0
0068 #define FEATURE_DPM_GFXCLK_BIT          1
0069 #define FEATURE_DPM_UCLK_BIT            2
0070 #define FEATURE_DPM_SOCCLK_BIT          3
0071 #define FEATURE_DPM_UVD_BIT             4
0072 #define FEATURE_DPM_VCE_BIT             5
0073 #define FEATURE_ULV_BIT                 6
0074 #define FEATURE_DPM_MP0CLK_BIT          7
0075 #define FEATURE_DPM_LINK_BIT            8
0076 #define FEATURE_DPM_DCEFCLK_BIT         9
0077 #define FEATURE_DS_GFXCLK_BIT           10
0078 #define FEATURE_DS_SOCCLK_BIT           11
0079 #define FEATURE_DS_LCLK_BIT             12
0080 #define FEATURE_PPT_BIT                 13
0081 #define FEATURE_TDC_BIT                 14
0082 #define FEATURE_THERMAL_BIT             15
0083 #define FEATURE_GFX_PER_CU_CG_BIT       16
0084 #define FEATURE_RM_BIT                  17
0085 #define FEATURE_DS_DCEFCLK_BIT          18
0086 #define FEATURE_ACDC_BIT                19
0087 #define FEATURE_VR0HOT_BIT              20
0088 #define FEATURE_VR1HOT_BIT              21
0089 #define FEATURE_FW_CTF_BIT              22
0090 #define FEATURE_LED_DISPLAY_BIT         23
0091 #define FEATURE_FAN_CONTROL_BIT         24
0092 #define FEATURE_GFX_EDC_BIT             25
0093 #define FEATURE_GFXOFF_BIT              26
0094 #define FEATURE_CG_BIT                  27
0095 #define FEATURE_ACG_BIT                 28
0096 #define FEATURE_SPARE_29_BIT            29
0097 #define FEATURE_SPARE_30_BIT            30
0098 #define FEATURE_SPARE_31_BIT            31
0099 
0100 #define NUM_FEATURES                    32
0101 
0102 #define FEATURE_DPM_PREFETCHER_MASK     (1 << FEATURE_DPM_PREFETCHER_BIT     )
0103 #define FEATURE_DPM_GFXCLK_MASK         (1 << FEATURE_DPM_GFXCLK_BIT         )
0104 #define FEATURE_DPM_UCLK_MASK           (1 << FEATURE_DPM_UCLK_BIT           )
0105 #define FEATURE_DPM_SOCCLK_MASK         (1 << FEATURE_DPM_SOCCLK_BIT         )
0106 #define FEATURE_DPM_UVD_MASK            (1 << FEATURE_DPM_UVD_BIT            )
0107 #define FEATURE_DPM_VCE_MASK            (1 << FEATURE_DPM_VCE_BIT            )
0108 #define FEATURE_ULV_MASK                (1 << FEATURE_ULV_BIT                )
0109 #define FEATURE_DPM_MP0CLK_MASK         (1 << FEATURE_DPM_MP0CLK_BIT         )
0110 #define FEATURE_DPM_LINK_MASK           (1 << FEATURE_DPM_LINK_BIT           )
0111 #define FEATURE_DPM_DCEFCLK_MASK        (1 << FEATURE_DPM_DCEFCLK_BIT        )
0112 #define FEATURE_DS_GFXCLK_MASK          (1 << FEATURE_DS_GFXCLK_BIT          )
0113 #define FEATURE_DS_SOCCLK_MASK          (1 << FEATURE_DS_SOCCLK_BIT          )
0114 #define FEATURE_DS_LCLK_MASK            (1 << FEATURE_DS_LCLK_BIT            )
0115 #define FEATURE_PPT_MASK                (1 << FEATURE_PPT_BIT                )
0116 #define FEATURE_TDC_MASK                (1 << FEATURE_TDC_BIT                )
0117 #define FEATURE_THERMAL_MASK            (1 << FEATURE_THERMAL_BIT            )
0118 #define FEATURE_GFX_PER_CU_CG_MASK      (1 << FEATURE_GFX_PER_CU_CG_BIT      )
0119 #define FEATURE_RM_MASK                 (1 << FEATURE_RM_BIT                 )
0120 #define FEATURE_DS_DCEFCLK_MASK         (1 << FEATURE_DS_DCEFCLK_BIT         )
0121 #define FEATURE_ACDC_MASK               (1 << FEATURE_ACDC_BIT               )
0122 #define FEATURE_VR0HOT_MASK             (1 << FEATURE_VR0HOT_BIT             )
0123 #define FEATURE_VR1HOT_MASK             (1 << FEATURE_VR1HOT_BIT             )
0124 #define FEATURE_FW_CTF_MASK             (1 << FEATURE_FW_CTF_BIT             )
0125 #define FEATURE_LED_DISPLAY_MASK        (1 << FEATURE_LED_DISPLAY_BIT        )
0126 #define FEATURE_FAN_CONTROL_MASK        (1 << FEATURE_FAN_CONTROL_BIT        )
0127 #define FEATURE_GFX_EDC_MASK            (1 << FEATURE_GFX_EDC_BIT            )
0128 #define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
0129 #define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
0130 #define FEATURE_ACG_MASK          (1 << FEATURE_ACG_BIT)
0131 #define FEATURE_SPARE_29_MASK           (1 << FEATURE_SPARE_29_BIT           )
0132 #define FEATURE_SPARE_30_MASK           (1 << FEATURE_SPARE_30_BIT           )
0133 #define FEATURE_SPARE_31_MASK           (1 << FEATURE_SPARE_31_BIT           )
0134 
0135 
0136 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID             0x00000001
0137 #define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000002
0138 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK    0x00000004
0139 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK      0x00000008
0140 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK   0x00000010
0141 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK     0x00000020
0142 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK   0x00000040
0143 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK     0x00000080
0144 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK    0x00000100
0145 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK      0x00000200
0146 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK   0x00000400
0147 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK     0x00000800
0148 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
0149 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK   0x00002000
0150 #define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH    0x00004000
0151 #define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH    0x00008000
0152 #define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH      0x00010000
0153 
0154 
0155 #define VR_MAPPING_VR_SELECT_MASK  0x01
0156 #define VR_MAPPING_VR_SELECT_SHIFT 0x00
0157 
0158 #define VR_MAPPING_PLANE_SELECT_MASK  0x02
0159 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
0160 
0161 
0162 #define PSI_SEL_VR0_PLANE0_PSI0  0x01
0163 #define PSI_SEL_VR0_PLANE0_PSI1  0x02
0164 #define PSI_SEL_VR0_PLANE1_PSI0  0x04
0165 #define PSI_SEL_VR0_PLANE1_PSI1  0x08
0166 #define PSI_SEL_VR1_PLANE0_PSI0  0x10
0167 #define PSI_SEL_VR1_PLANE0_PSI1  0x20
0168 #define PSI_SEL_VR1_PLANE1_PSI0  0x40
0169 #define PSI_SEL_VR1_PLANE1_PSI1  0x80
0170 
0171 
0172 #define THROTTLER_STATUS_PADDING_BIT      0
0173 #define THROTTLER_STATUS_TEMP_EDGE_BIT    1
0174 #define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
0175 #define THROTTLER_STATUS_TEMP_HBM_BIT     3
0176 #define THROTTLER_STATUS_TEMP_VR_GFX_BIT  4
0177 #define THROTTLER_STATUS_TEMP_VR_MEM_BIT  5
0178 #define THROTTLER_STATUS_TEMP_LIQUID_BIT  6
0179 #define THROTTLER_STATUS_TEMP_PLX_BIT     7
0180 #define THROTTLER_STATUS_TEMP_SKIN_BIT    8
0181 #define THROTTLER_STATUS_TDC_GFX_BIT      9
0182 #define THROTTLER_STATUS_TDC_SOC_BIT      10
0183 #define THROTTLER_STATUS_PPT_BIT          11
0184 #define THROTTLER_STATUS_FIT_BIT          12
0185 #define THROTTLER_STATUS_PPM_BIT          13
0186 
0187 
0188 #define TABLE_TRANSFER_OK         0x0
0189 #define TABLE_TRANSFER_FAILED     0xFF
0190 
0191 
0192 #define WORKLOAD_DEFAULT_BIT              0
0193 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
0194 #define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
0195 #define WORKLOAD_PPLIB_VIDEO_BIT          3
0196 #define WORKLOAD_PPLIB_VR_BIT             4
0197 #define WORKLOAD_PPLIB_COMPUTE_BIT        5
0198 #define WORKLOAD_PPLIB_CUSTOM_BIT         6
0199 #define WORKLOAD_PPLIB_COUNT              7
0200 
0201 typedef struct {
0202   uint32_t a;
0203   uint32_t b;
0204   uint32_t c;
0205 } QuadraticInt_t;
0206 
0207 typedef struct {
0208   uint32_t m;
0209   uint32_t b;
0210 } LinearInt_t;
0211 
0212 typedef struct {
0213   uint32_t a;
0214   uint32_t b;
0215   uint32_t c;
0216 } DroopInt_t;
0217 
0218 typedef enum {
0219   PPCLK_GFXCLK,
0220   PPCLK_VCLK,
0221   PPCLK_DCLK,
0222   PPCLK_ECLK,
0223   PPCLK_SOCCLK,
0224   PPCLK_UCLK,
0225   PPCLK_DCEFCLK,
0226   PPCLK_DISPCLK,
0227   PPCLK_PIXCLK,
0228   PPCLK_PHYCLK,
0229   PPCLK_COUNT,
0230 } PPCLK_e;
0231 
0232 enum {
0233   VOLTAGE_MODE_AVFS,
0234   VOLTAGE_MODE_AVFS_SS,
0235   VOLTAGE_MODE_SS,
0236   VOLTAGE_MODE_COUNT,
0237 };
0238 
0239 typedef struct {
0240   uint8_t        VoltageMode;
0241   uint8_t        SnapToDiscrete;
0242   uint8_t        NumDiscreteLevels;
0243   uint8_t        padding;
0244   LinearInt_t    ConversionToAvfsClk;
0245   QuadraticInt_t SsCurve;
0246 } DpmDescriptor_t;
0247 
0248 typedef struct {
0249   uint32_t Version;
0250 
0251 
0252   uint32_t FeaturesToRun[2];
0253 
0254 
0255   uint16_t SocketPowerLimitAc0;
0256   uint16_t SocketPowerLimitAc0Tau;
0257   uint16_t SocketPowerLimitAc1;
0258   uint16_t SocketPowerLimitAc1Tau;
0259   uint16_t SocketPowerLimitAc2;
0260   uint16_t SocketPowerLimitAc2Tau;
0261   uint16_t SocketPowerLimitAc3;
0262   uint16_t SocketPowerLimitAc3Tau;
0263   uint16_t SocketPowerLimitDc;
0264   uint16_t SocketPowerLimitDcTau;
0265   uint16_t TdcLimitSoc;
0266   uint16_t TdcLimitSocTau;
0267   uint16_t TdcLimitGfx;
0268   uint16_t TdcLimitGfxTau;
0269 
0270   uint16_t TedgeLimit;
0271   uint16_t ThotspotLimit;
0272   uint16_t ThbmLimit;
0273   uint16_t Tvr_gfxLimit;
0274   uint16_t Tvr_memLimit;
0275   uint16_t Tliquid1Limit;
0276   uint16_t Tliquid2Limit;
0277   uint16_t TplxLimit;
0278   uint32_t FitLimit;
0279 
0280   uint16_t PpmPowerLimit;
0281   uint16_t PpmTemperatureThreshold;
0282 
0283   uint8_t  MemoryOnPackage;
0284   uint8_t  padding8_limits[3];
0285 
0286 
0287   uint16_t  UlvVoltageOffsetSoc;
0288   uint16_t  UlvVoltageOffsetGfx;
0289 
0290   uint8_t  UlvSmnclkDid;
0291   uint8_t  UlvMp1clkDid;
0292   uint8_t  UlvGfxclkBypass;
0293   uint8_t  Padding234;
0294 
0295 
0296   uint16_t     MinVoltageGfx;
0297   uint16_t     MinVoltageSoc;
0298   uint16_t     MaxVoltageGfx;
0299   uint16_t     MaxVoltageSoc;
0300 
0301   uint16_t     LoadLineResistance;
0302   uint16_t     LoadLine_padding;
0303 
0304 
0305   DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
0306 
0307   uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];
0308   uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];
0309   uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];
0310   uint16_t       FreqTableEclk     [NUM_ECLK_DPM_LEVELS    ];
0311   uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];
0312   uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];
0313   uint16_t       FreqTableDcefclk  [NUM_DCEFCLK_DPM_LEVELS ];
0314   uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];
0315   uint16_t       FreqTablePixclk   [NUM_PIXCLK_DPM_LEVELS  ];
0316   uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];
0317 
0318   uint16_t       DcModeMaxFreq     [PPCLK_COUNT            ];
0319 
0320 
0321   uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];
0322   uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];
0323 
0324 
0325   uint16_t        GfxclkFidle;
0326   uint16_t        GfxclkSlewRate;
0327   uint16_t        CksEnableFreq;
0328   uint16_t        Padding789;
0329   QuadraticInt_t  CksVoltageOffset;
0330   uint16_t        AcgThresholdFreqHigh;
0331   uint16_t        AcgThresholdFreqLow;
0332   uint16_t        GfxclkDsMaxFreq;
0333   uint8_t         Padding456[2];
0334 
0335 
0336   uint8_t      LowestUclkReservedForUlv;
0337   uint8_t      Padding8_Uclk[3];
0338 
0339 
0340   uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
0341   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
0342   uint16_t     LclkFreq[NUM_LINK_LEVELS];
0343 
0344 
0345   uint16_t     EnableTdpm;
0346   uint16_t     TdpmHighHystTemperature;
0347   uint16_t     TdpmLowHystTemperature;
0348   uint16_t     GfxclkFreqHighTempLimit;
0349 
0350 
0351   uint16_t     FanStopTemp;
0352   uint16_t     FanStartTemp;
0353 
0354   uint16_t     FanGainEdge;
0355   uint16_t     FanGainHotspot;
0356   uint16_t     FanGainLiquid;
0357   uint16_t     FanGainVrVddc;
0358   uint16_t     FanGainVrMvdd;
0359   uint16_t     FanGainPlx;
0360   uint16_t     FanGainHbm;
0361   uint16_t     FanPwmMin;
0362   uint16_t     FanAcousticLimitRpm;
0363   uint16_t     FanThrottlingRpm;
0364   uint16_t     FanMaximumRpm;
0365   uint16_t     FanTargetTemperature;
0366   uint16_t     FanTargetGfxclk;
0367   uint8_t      FanZeroRpmEnable; 
0368   uint8_t      FanTachEdgePerRev;
0369 
0370 
0371 
0372   int16_t      FuzzyFan_ErrorSetDelta;
0373   int16_t      FuzzyFan_ErrorRateSetDelta;
0374   int16_t      FuzzyFan_PwmSetDelta;
0375   uint16_t     FuzzyFan_Reserved;
0376 
0377 
0378 
0379 
0380   uint8_t           OverrideAvfsGb;
0381   uint8_t           Padding8_Avfs[3];
0382 
0383   QuadraticInt_t    qAvfsGb;
0384   DroopInt_t        dBtcGbGfxCksOn;
0385   DroopInt_t        dBtcGbGfxCksOff;
0386   DroopInt_t        dBtcGbGfxAcg;
0387   DroopInt_t        dBtcGbSoc;
0388   LinearInt_t       qAgingGbGfx;
0389   LinearInt_t       qAgingGbSoc;
0390 
0391   QuadraticInt_t    qStaticVoltageOffsetGfx;
0392   QuadraticInt_t    qStaticVoltageOffsetSoc;
0393 
0394   uint16_t          DcTolGfx;
0395   uint16_t          DcTolSoc;
0396 
0397   uint8_t           DcBtcGfxEnabled;
0398   uint8_t           DcBtcSocEnabled;
0399   uint8_t           Padding8_GfxBtc[2];
0400 
0401   uint16_t          DcBtcGfxMin;
0402   uint16_t          DcBtcGfxMax;
0403 
0404   uint16_t          DcBtcSocMin;
0405   uint16_t          DcBtcSocMax;
0406 
0407 
0408 
0409   uint32_t          DebugOverrides;
0410   QuadraticInt_t    ReservedEquation0;
0411   QuadraticInt_t    ReservedEquation1;
0412   QuadraticInt_t    ReservedEquation2;
0413   QuadraticInt_t    ReservedEquation3;
0414 
0415   uint16_t     MinVoltageUlvGfx;
0416   uint16_t     MinVoltageUlvSoc;
0417 
0418   uint32_t     Reserved[14];
0419 
0420 
0421 
0422   uint8_t      Liquid1_I2C_address;
0423   uint8_t      Liquid2_I2C_address;
0424   uint8_t      Vr_I2C_address;
0425   uint8_t      Plx_I2C_address;
0426 
0427   uint8_t      Liquid_I2C_LineSCL;
0428   uint8_t      Liquid_I2C_LineSDA;
0429   uint8_t      Vr_I2C_LineSCL;
0430   uint8_t      Vr_I2C_LineSDA;
0431 
0432   uint8_t      Plx_I2C_LineSCL;
0433   uint8_t      Plx_I2C_LineSDA;
0434   uint8_t      VrSensorPresent;
0435   uint8_t      LiquidSensorPresent;
0436 
0437   uint16_t     MaxVoltageStepGfx;
0438   uint16_t     MaxVoltageStepSoc;
0439 
0440   uint8_t      VddGfxVrMapping;
0441   uint8_t      VddSocVrMapping;
0442   uint8_t      VddMem0VrMapping;
0443   uint8_t      VddMem1VrMapping;
0444 
0445   uint8_t      GfxUlvPhaseSheddingMask;
0446   uint8_t      SocUlvPhaseSheddingMask;
0447   uint8_t      ExternalSensorPresent;
0448   uint8_t      Padding8_V;
0449 
0450 
0451   uint16_t     GfxMaxCurrent;
0452   int8_t       GfxOffset;
0453   uint8_t      Padding_TelemetryGfx;
0454 
0455   uint16_t     SocMaxCurrent;
0456   int8_t       SocOffset;
0457   uint8_t      Padding_TelemetrySoc;
0458 
0459   uint16_t     Mem0MaxCurrent;
0460   int8_t       Mem0Offset;
0461   uint8_t      Padding_TelemetryMem0;
0462 
0463   uint16_t     Mem1MaxCurrent;
0464   int8_t       Mem1Offset;
0465   uint8_t      Padding_TelemetryMem1;
0466 
0467 
0468   uint8_t      AcDcGpio;
0469   uint8_t      AcDcPolarity;
0470   uint8_t      VR0HotGpio;
0471   uint8_t      VR0HotPolarity;
0472 
0473   uint8_t      VR1HotGpio;
0474   uint8_t      VR1HotPolarity;
0475   uint8_t      Padding1;
0476   uint8_t      Padding2;
0477 
0478 
0479 
0480   uint8_t      LedPin0;
0481   uint8_t      LedPin1;
0482   uint8_t      LedPin2;
0483   uint8_t      padding8_4;
0484 
0485 
0486   uint8_t      PllGfxclkSpreadEnabled;
0487   uint8_t      PllGfxclkSpreadPercent;
0488   uint16_t     PllGfxclkSpreadFreq;
0489 
0490   uint8_t      UclkSpreadEnabled;
0491   uint8_t      UclkSpreadPercent;
0492   uint16_t     UclkSpreadFreq;
0493 
0494   uint8_t      SocclkSpreadEnabled;
0495   uint8_t      SocclkSpreadPercent;
0496   uint16_t     SocclkSpreadFreq;
0497 
0498   uint8_t      AcgGfxclkSpreadEnabled;
0499   uint8_t      AcgGfxclkSpreadPercent;
0500   uint16_t     AcgGfxclkSpreadFreq;
0501 
0502   uint8_t      Vr2_I2C_address;
0503   uint8_t      padding_vr2[3];
0504 
0505   uint32_t     BoardReserved[9];
0506 
0507 
0508   uint32_t     MmHubPadding[7];
0509 
0510 } PPTable_t;
0511 
0512 typedef struct {
0513 
0514   uint16_t     GfxclkAverageLpfTau;
0515   uint16_t     SocclkAverageLpfTau;
0516   uint16_t     UclkAverageLpfTau;
0517   uint16_t     GfxActivityLpfTau;
0518   uint16_t     UclkActivityLpfTau;
0519 
0520 
0521   uint32_t     MmHubPadding[7];
0522 } DriverSmuConfig_t;
0523 
0524 typedef struct {
0525 
0526   uint16_t      GfxclkFmin;
0527   uint16_t      GfxclkFmax;
0528   uint16_t      GfxclkFreq1;
0529   uint16_t      GfxclkOffsetVolt1;
0530   uint16_t      GfxclkFreq2;
0531   uint16_t      GfxclkOffsetVolt2;
0532   uint16_t      GfxclkFreq3;
0533   uint16_t      GfxclkOffsetVolt3;
0534   uint16_t      UclkFmax;
0535   int16_t       OverDrivePct;
0536   uint16_t      FanMaximumRpm;
0537   uint16_t      FanMinimumPwm;
0538   uint16_t      FanTargetTemperature;
0539   uint16_t      MaxOpTemp;
0540 
0541 } OverDriveTable_t;
0542 
0543 typedef struct {
0544   uint16_t CurrClock[PPCLK_COUNT];
0545   uint16_t AverageGfxclkFrequency;
0546   uint16_t AverageSocclkFrequency;
0547   uint16_t AverageUclkFrequency  ;
0548   uint16_t AverageGfxActivity    ;
0549   uint16_t AverageUclkActivity   ;
0550   uint8_t  CurrSocVoltageOffset  ;
0551   uint8_t  CurrGfxVoltageOffset  ;
0552   uint8_t  CurrMemVidOffset      ;
0553   uint8_t  Padding8              ;
0554   uint16_t CurrSocketPower       ;
0555   uint16_t TemperatureEdge       ;
0556   uint16_t TemperatureHotspot    ;
0557   uint16_t TemperatureHBM        ;
0558   uint16_t TemperatureVrGfx      ;
0559   uint16_t TemperatureVrMem      ;
0560   uint16_t TemperatureLiquid     ;
0561   uint16_t TemperaturePlx        ;
0562   uint32_t ThrottlerStatus       ;
0563 
0564   uint8_t  LinkDpmLevel;
0565   uint8_t  Padding[3];
0566 
0567 
0568   uint32_t     MmHubPadding[7];
0569 } SmuMetrics_t;
0570 
0571 typedef struct {
0572   uint16_t MinClock;
0573   uint16_t MaxClock;
0574   uint16_t MinUclk;
0575   uint16_t MaxUclk;
0576 
0577   uint8_t  WmSetting;
0578   uint8_t  Padding[3];
0579 } WatermarkRowGeneric_t;
0580 
0581 #define NUM_WM_RANGES 4
0582 
0583 typedef enum {
0584   WM_SOCCLK = 0,
0585   WM_DCEFCLK,
0586   WM_COUNT_PP,
0587 } WM_CLOCK_e;
0588 
0589 typedef struct {
0590 
0591   WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
0592 
0593   uint32_t     MmHubPadding[7];
0594 } Watermarks_t;
0595 
0596 typedef struct {
0597   uint16_t avgPsmCount[30];
0598   uint16_t minPsmCount[30];
0599   float    avgPsmVoltage[30];
0600   float    minPsmVoltage[30];
0601 
0602   uint32_t MmHubPadding[7];
0603 } AvfsDebugTable_t;
0604 
0605 typedef struct {
0606   uint8_t  AvfsEn;
0607   uint8_t  AvfsVersion;
0608   uint8_t  OverrideVFT;
0609   uint8_t  OverrideAvfsGb;
0610 
0611   uint8_t  OverrideTemperatures;
0612   uint8_t  OverrideVInversion;
0613   uint8_t  OverrideP2V;
0614   uint8_t  OverrideP2VCharzFreq;
0615 
0616   int32_t VFT0_m1;
0617   int32_t VFT0_m2;
0618   int32_t VFT0_b;
0619 
0620   int32_t VFT1_m1;
0621   int32_t VFT1_m2;
0622   int32_t VFT1_b;
0623 
0624   int32_t VFT2_m1;
0625   int32_t VFT2_m2;
0626   int32_t VFT2_b;
0627 
0628   int32_t AvfsGb0_m1;
0629   int32_t AvfsGb0_m2;
0630   int32_t AvfsGb0_b;
0631 
0632   int32_t AcBtcGb_m1;
0633   int32_t AcBtcGb_m2;
0634   int32_t AcBtcGb_b;
0635 
0636   uint32_t AvfsTempCold;
0637   uint32_t AvfsTempMid;
0638   uint32_t AvfsTempHot;
0639 
0640   uint32_t GfxVInversion;
0641   uint32_t SocVInversion;
0642 
0643   int32_t P2V_m1;
0644   int32_t P2V_m2;
0645   int32_t P2V_b;
0646 
0647   uint32_t P2VCharzFreq;
0648 
0649   uint32_t EnabledAvfsModules;
0650 
0651   uint32_t MmHubPadding[7];
0652 } AvfsFuseOverride_t;
0653 
0654 typedef struct {
0655 
0656   uint8_t   Gfx_ActiveHystLimit;
0657   uint8_t   Gfx_IdleHystLimit;
0658   uint8_t   Gfx_FPS;
0659   uint8_t   Gfx_MinActiveFreqType;
0660   uint8_t   Gfx_BoosterFreqType; 
0661   uint8_t   Gfx_UseRlcBusy; 
0662   uint16_t  Gfx_MinActiveFreq;
0663   uint16_t  Gfx_BoosterFreq;
0664   uint16_t  Gfx_PD_Data_time_constant;
0665   uint32_t  Gfx_PD_Data_limit_a;
0666   uint32_t  Gfx_PD_Data_limit_b;
0667   uint32_t  Gfx_PD_Data_limit_c;
0668   uint32_t  Gfx_PD_Data_error_coeff;
0669   uint32_t  Gfx_PD_Data_error_rate_coeff;
0670 
0671   uint8_t   Soc_ActiveHystLimit;
0672   uint8_t   Soc_IdleHystLimit;
0673   uint8_t   Soc_FPS;
0674   uint8_t   Soc_MinActiveFreqType;
0675   uint8_t   Soc_BoosterFreqType; 
0676   uint8_t   Soc_UseRlcBusy;
0677   uint16_t  Soc_MinActiveFreq;
0678   uint16_t  Soc_BoosterFreq;
0679   uint16_t  Soc_PD_Data_time_constant;
0680   uint32_t  Soc_PD_Data_limit_a;
0681   uint32_t  Soc_PD_Data_limit_b;
0682   uint32_t  Soc_PD_Data_limit_c;
0683   uint32_t  Soc_PD_Data_error_coeff;
0684   uint32_t  Soc_PD_Data_error_rate_coeff;
0685 
0686   uint8_t   Mem_ActiveHystLimit;
0687   uint8_t   Mem_IdleHystLimit;
0688   uint8_t   Mem_FPS;
0689   uint8_t   Mem_MinActiveFreqType;
0690   uint8_t   Mem_BoosterFreqType;
0691   uint8_t   Mem_UseRlcBusy; 
0692   uint16_t  Mem_MinActiveFreq;
0693   uint16_t  Mem_BoosterFreq;
0694   uint16_t  Mem_PD_Data_time_constant;
0695   uint32_t  Mem_PD_Data_limit_a;
0696   uint32_t  Mem_PD_Data_limit_b;
0697   uint32_t  Mem_PD_Data_limit_c;
0698   uint32_t  Mem_PD_Data_error_coeff;
0699   uint32_t  Mem_PD_Data_error_rate_coeff;
0700 
0701 } DpmActivityMonitorCoeffInt_t;
0702 
0703 
0704 
0705 
0706 #define TABLE_PPTABLE                 0
0707 #define TABLE_WATERMARKS              1
0708 #define TABLE_AVFS                    2
0709 #define TABLE_AVFS_PSM_DEBUG          3
0710 #define TABLE_AVFS_FUSE_OVERRIDE      4
0711 #define TABLE_PMSTATUSLOG             5
0712 #define TABLE_SMU_METRICS             6
0713 #define TABLE_DRIVER_SMU_CONFIG       7
0714 #define TABLE_ACTIVITY_MONITOR_COEFF  8
0715 #define TABLE_OVERDRIVE               9
0716 #define TABLE_COUNT                  10
0717 
0718 
0719 #define UCLK_SWITCH_SLOW 0
0720 #define UCLK_SWITCH_FAST 1
0721 
0722 
0723 #define SQ_Enable_MASK 0x1
0724 #define SQ_IR_MASK 0x2
0725 #define SQ_PCC_MASK 0x4
0726 #define SQ_EDC_MASK 0x8
0727 
0728 #define TCP_Enable_MASK 0x100
0729 #define TCP_IR_MASK 0x200
0730 #define TCP_PCC_MASK 0x400
0731 #define TCP_EDC_MASK 0x800
0732 
0733 #define TD_Enable_MASK 0x10000
0734 #define TD_IR_MASK 0x20000
0735 #define TD_PCC_MASK 0x40000
0736 #define TD_EDC_MASK 0x80000
0737 
0738 #define DB_Enable_MASK 0x1000000
0739 #define DB_IR_MASK 0x2000000
0740 #define DB_PCC_MASK 0x4000000
0741 #define DB_EDC_MASK 0x8000000
0742 
0743 #define SQ_Enable_SHIFT 0
0744 #define SQ_IR_SHIFT 1
0745 #define SQ_PCC_SHIFT 2
0746 #define SQ_EDC_SHIFT 3
0747 
0748 #define TCP_Enable_SHIFT 8
0749 #define TCP_IR_SHIFT 9
0750 #define TCP_PCC_SHIFT 10
0751 #define TCP_EDC_SHIFT 11
0752 
0753 #define TD_Enable_SHIFT 16
0754 #define TD_IR_SHIFT 17
0755 #define TD_PCC_SHIFT 18
0756 #define TD_EDC_SHIFT 19
0757 
0758 #define DB_Enable_SHIFT 24
0759 #define DB_IR_SHIFT 25
0760 #define DB_PCC_SHIFT 26
0761 #define DB_EDC_SHIFT 27
0762 
0763 #define REMOVE_FMAX_MARGIN_BIT     0x0
0764 #define REMOVE_DCTOL_MARGIN_BIT    0x1
0765 #define REMOVE_PLATFORM_MARGIN_BIT 0x2
0766 
0767 #endif
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