powerplay/inc/smumgr.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _SMUMGR_H_
0024 #define _SMUMGR_H_
0025 #include <linux/types.h>
0026 #include "amd_powerplay.h"
0027 #include "hwmgr.h"
0028
0029 enum SMU_TABLE {
0030     SMU_UVD_TABLE = 0,
0031     SMU_VCE_TABLE,
0032     SMU_BIF_TABLE,
0033 };
0034
0035 enum SMU_TYPE {
0036     SMU_SoftRegisters = 0,
0037     SMU_Discrete_DpmTable,
0038 };
0039
0040 enum SMU_MEMBER {
0041     HandshakeDisables = 0,
0042     VoltageChangeTimeout,
0043     AverageGraphicsActivity,
0044     AverageMemoryActivity,
0045     PreVBlankGap,
0046     VBlankTimeout,
0047     UcodeLoadStatus,
0048     UvdBootLevel,
0049     VceBootLevel,
0050     LowSclkInterruptThreshold,
0051     DRAM_LOG_ADDR_H,
0052     DRAM_LOG_ADDR_L,
0053     DRAM_LOG_PHY_ADDR_H,
0054     DRAM_LOG_PHY_ADDR_L,
0055     DRAM_LOG_BUFF_SIZE,
0056 };
0057
0058
0059 enum SMU_MAC_DEFINITION {
0060     SMU_MAX_LEVELS_GRAPHICS = 0,
0061     SMU_MAX_LEVELS_MEMORY,
0062     SMU_MAX_LEVELS_LINK,
0063     SMU_MAX_ENTRIES_SMIO,
0064     SMU_MAX_LEVELS_VDDC,
0065     SMU_MAX_LEVELS_VDDGFX,
0066     SMU_MAX_LEVELS_VDDCI,
0067     SMU_MAX_LEVELS_MVDD,
0068     SMU_UVD_MCLK_HANDSHAKE_DISABLE,
0069 };
0070
0071 enum SMU9_TABLE_ID {
0072     PPTABLE = 0,
0073     WMTABLE,
0074     AVFSTABLE,
0075     TOOLSTABLE,
0076     AVFSFUSETABLE
0077 };
0078
0079 enum SMU10_TABLE_ID {
0080     SMU10_WMTABLE = 0,
0081     SMU10_CLOCKTABLE,
0082 };
0083
0084 extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
0085
0086 extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
0087
0088 extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp);
0089
0090 extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
0091                     uint16_t msg, uint32_t parameter,
0092                     uint32_t *resp);
0093
0094 extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
0095
0096 extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
0097 extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
0098 extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
0099 extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
0100 extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
0101 extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
0102 extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
0103 extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
0104 extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
0105                 uint32_t type, uint32_t member);
0106 extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
0107
0108 extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
0109
0110 extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
0111
0112 extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting);
0113
0114 extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
0115
0116 extern int smum_stop_smc(struct pp_hwmgr *hwmgr);
0117
0118 #endif