powerplay/inc/smu9_driver_if.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU9_DRIVER_IF_H
0025 #define SMU9_DRIVER_IF_H
0026
0027 #include "smu9.h"
0028
0029 /**** IMPORTANT ***
0030  * SMU TEAM: Always increment the interface version if
0031  * any structure is changed in this file
0032  */
0033 #define SMU9_DRIVER_IF_VERSION 0xE
0034
0035 #define PPTABLE_V10_SMU_VERSION 1
0036
0037 #define NUM_GFXCLK_DPM_LEVELS  8
0038 #define NUM_UVD_DPM_LEVELS     8
0039 #define NUM_VCE_DPM_LEVELS     8
0040 #define NUM_MP0CLK_DPM_LEVELS  8
0041 #define NUM_UCLK_DPM_LEVELS    4
0042 #define NUM_SOCCLK_DPM_LEVELS  8
0043 #define NUM_DCEFCLK_DPM_LEVELS 8
0044 #define NUM_LINK_LEVELS        2
0045
0046 #define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
0047 #define MAX_UVD_DPM_LEVEL     (NUM_UVD_DPM_LEVELS     - 1)
0048 #define MAX_VCE_DPM_LEVEL     (NUM_VCE_DPM_LEVELS     - 1)
0049 #define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
0050 #define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
0051 #define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
0052 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
0053 #define MAX_LINK_DPM_LEVEL    (NUM_LINK_LEVELS        - 1)
0054
0055 #define MIN_GFXCLK_DPM_LEVEL  0
0056 #define MIN_UVD_DPM_LEVEL     0
0057 #define MIN_VCE_DPM_LEVEL     0
0058 #define MIN_MP0CLK_DPM_LEVEL  0
0059 #define MIN_UCLK_DPM_LEVEL    0
0060 #define MIN_SOCCLK_DPM_LEVEL  0
0061 #define MIN_DCEFCLK_DPM_LEVEL 0
0062 #define MIN_LINK_DPM_LEVEL    0
0063
0064 #define NUM_EVV_VOLTAGE_LEVELS 8
0065 #define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
0066 #define MIN_EVV_VOLTAGE_LEVEL 0
0067
0068 #define NUM_PSP_LEVEL_MAP 4
0069
0070 /* Gemini Modes */
0071 #define PPSMC_GeminiModeNone   0  /* Single GPU board */
0072 #define PPSMC_GeminiModeMaster 1  /* Master GPU on a Gemini board */
0073 #define PPSMC_GeminiModeSlave  2  /* Slave GPU on a Gemini board */
0074
0075 /* Voltage Modes for DPMs */
0076 #define VOLTAGE_MODE_AVFS_INTERPOLATE 0
0077 #define VOLTAGE_MODE_AVFS_WORST_CASE  1
0078 #define VOLTAGE_MODE_STATIC           2
0079
0080 typedef struct {
0081   uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
0082   uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
0083   uint16_t SsSlewFrac;
0084   uint8_t  SsOn;
0085   uint8_t  Did;      /* DID */
0086 } PllSetting_t;
0087
0088 typedef struct {
0089   int32_t a0;
0090   int32_t a1;
0091   int32_t a2;
0092
0093   uint8_t a0_shift;
0094   uint8_t a1_shift;
0095   uint8_t a2_shift;
0096   uint8_t padding;
0097 } GbVdroopTable_t;
0098
0099 typedef struct {
0100   int32_t m1;
0101   int32_t m2;
0102   int32_t b;
0103
0104   uint8_t m1_shift;
0105   uint8_t m2_shift;
0106   uint8_t b_shift;
0107   uint8_t padding;
0108 } QuadraticInt_t;
0109
0110 #define NUM_DSPCLK_LEVELS 8
0111
0112 typedef enum {
0113   DSPCLK_DCEFCLK = 0,
0114   DSPCLK_DISPCLK,
0115   DSPCLK_PIXCLK,
0116   DSPCLK_PHYCLK,
0117   DSPCLK_COUNT,
0118 } DSPCLK_e;
0119
0120 typedef struct {
0121   uint16_t Freq; /* in MHz */
0122   uint16_t Vid;  /* min voltage in SVI2 VID */
0123 } DisplayClockTable_t;
0124
0125 typedef struct {
0126   /* PowerTune */
0127   uint16_t SocketPowerLimit; /* Watts */
0128   uint16_t TdcLimit;         /* Amps */
0129   uint16_t EdcLimit;         /* Amps */
0130   uint16_t TedgeLimit;       /* Celcius */
0131   uint16_t ThotspotLimit;    /* Celcius */
0132   uint16_t ThbmLimit;        /* Celcius */
0133   uint16_t Tvr_socLimit;     /* Celcius */
0134   uint16_t Tvr_memLimit;     /* Celcius */
0135   uint16_t Tliquid1Limit;    /* Celcius */
0136   uint16_t Tliquid2Limit;    /* Celcius */
0137   uint16_t TplxLimit;        /* Celcius */
0138   uint16_t LoadLineResistance; /* in mOhms */
0139   uint32_t FitLimit;         /* Failures in time (failures per million parts over the defined lifetime) */
0140
0141   /* External Component Communication Settings */
0142   uint8_t  Liquid1_I2C_address;
0143   uint8_t  Liquid2_I2C_address;
0144   uint8_t  Vr_I2C_address;
0145   uint8_t  Plx_I2C_address;
0146
0147   uint8_t  GeminiMode;
0148   uint8_t  spare17[3];
0149   uint32_t GeminiApertureHigh;
0150   uint32_t GeminiApertureLow;
0151
0152   uint8_t  Liquid_I2C_LineSCL;
0153   uint8_t  Liquid_I2C_LineSDA;
0154   uint8_t  Vr_I2C_LineSCL;
0155   uint8_t  Vr_I2C_LineSDA;
0156   uint8_t  Plx_I2C_LineSCL;
0157   uint8_t  Plx_I2C_LineSDA;
0158   uint8_t  paddingx[2];
0159
0160   /* ULV Settings */
0161   uint8_t  UlvOffsetVid;     /* SVI2 VID */
0162   uint8_t  UlvSmnclkDid;     /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
0163   uint8_t  UlvMp1clkDid;     /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
0164   uint8_t  UlvGfxclkBypass;  /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
0165
0166   /* VDDCR_SOC Voltages */
0167   uint8_t      SocVid[NUM_EVV_VOLTAGE_LEVELS];
0168
0169   /* This is the minimum voltage needed to run the SOC. */
0170   uint8_t      MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
0171   uint8_t      MaxVoltageVid; /* Maximum Voltage allowable */
0172   uint8_t      MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
0173   uint8_t      padding8;
0174
0175   uint8_t      UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
0176   uint8_t      UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
0177   uint8_t      padding8_2[2];
0178
0179   /* SOC Frequencies */
0180   PllSetting_t GfxclkLevel        [NUM_GFXCLK_DPM_LEVELS];
0181
0182   uint8_t      SocclkDid          [NUM_SOCCLK_DPM_LEVELS];          /* DID */
0183   uint8_t      SocDpmVoltageIndex [NUM_SOCCLK_DPM_LEVELS];
0184
0185   uint8_t      VclkDid            [NUM_UVD_DPM_LEVELS];            /* DID */
0186   uint8_t      DclkDid            [NUM_UVD_DPM_LEVELS];            /* DID */
0187   uint8_t      UvdDpmVoltageIndex [NUM_UVD_DPM_LEVELS];
0188
0189   uint8_t      EclkDid            [NUM_VCE_DPM_LEVELS];            /* DID */
0190   uint8_t      VceDpmVoltageIndex [NUM_VCE_DPM_LEVELS];
0191
0192   uint8_t      Mp0clkDid          [NUM_MP0CLK_DPM_LEVELS];          /* DID */
0193   uint8_t      Mp0DpmVoltageIndex [NUM_MP0CLK_DPM_LEVELS];
0194
0195   DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
0196   QuadraticInt_t      DisplayClock2Gfxclk[DSPCLK_COUNT];
0197
0198   uint8_t      GfxDpmVoltageMode;
0199   uint8_t      SocDpmVoltageMode;
0200   uint8_t      UclkDpmVoltageMode;
0201   uint8_t      UvdDpmVoltageMode;
0202
0203   uint8_t      VceDpmVoltageMode;
0204   uint8_t      Mp0DpmVoltageMode;
0205   uint8_t      DisplayDpmVoltageMode;
0206   uint8_t      padding8_3;
0207
0208   uint16_t     GfxclkSlewRate;
0209   uint16_t     padding;
0210
0211   uint32_t     LowGfxclkInterruptThreshold;  /* in units of 10KHz */
0212
0213   /* Alpha parameters for clock averages. ("255"=1) */
0214   uint8_t      GfxclkAverageAlpha;
0215   uint8_t      SocclkAverageAlpha;
0216   uint8_t      UclkAverageAlpha;
0217   uint8_t      GfxActivityAverageAlpha;
0218
0219   /* UCLK States */
0220   uint8_t      MemVid[NUM_UCLK_DPM_LEVELS];    /* VID */
0221   PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS];   /* Full PLL settings */
0222   uint8_t      MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
0223   uint8_t      LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
0224   uint8_t      paddingUclk[3];
0225   uint16_t     NumMemoryChannels;  /* Used for memory bandwidth calculations */
0226   uint16_t     MemoryChannelWidth; /* Used for memory bandwidth calculations */
0227
0228   /* CKS Settings */
0229   uint8_t      CksEnable[NUM_GFXCLK_DPM_LEVELS];
0230   uint8_t      CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
0231
0232   /* MP0 Mapping Table */
0233   uint8_t      PspLevelMap[NUM_PSP_LEVEL_MAP];
0234
0235   /* Link DPM Settings */
0236   uint8_t     PcieGenSpeed[NUM_LINK_LEVELS];           /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
0237   uint8_t     PcieLaneCount[NUM_LINK_LEVELS];          /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
0238   uint8_t     LclkDid[NUM_LINK_LEVELS];                /* Leave at 0 to use hardcoded values in FW */
0239   uint8_t     paddingLinkDpm[2];
0240
0241   /* Fan Control */
0242   uint16_t     FanStopTemp;          /* Celcius */
0243   uint16_t     FanStartTemp;         /* Celcius */
0244
0245   uint16_t     FanGainEdge;
0246   uint16_t     FanGainHotspot;
0247   uint16_t     FanGainLiquid;
0248   uint16_t     FanGainVrVddc;
0249   uint16_t     FanGainVrMvdd;
0250   uint16_t     FanGainPlx;
0251   uint16_t     FanGainHbm;
0252   uint16_t     FanPwmMin;
0253   uint16_t     FanAcousticLimitRpm;
0254   uint16_t     FanThrottlingRpm;
0255   uint16_t     FanMaximumRpm;
0256   uint16_t     FanTargetTemperature;
0257   uint16_t     FanTargetGfxclk;
0258   uint8_t      FanZeroRpmEnable;
0259   uint8_t      FanSpare;
0260
0261   /* The following are AFC override parameters. Leave at 0 to use FW defaults. */
0262   int16_t      FuzzyFan_ErrorSetDelta;
0263   int16_t      FuzzyFan_ErrorRateSetDelta;
0264   int16_t      FuzzyFan_PwmSetDelta;
0265   uint16_t     FuzzyFan_Reserved;
0266
0267   /* GPIO Settings */
0268   uint8_t      AcDcGpio;        /* GPIO pin configured for AC/DC switching */
0269   uint8_t      AcDcPolarity;    /* GPIO polarity for AC/DC switching */
0270   uint8_t      VR0HotGpio;      /* GPIO pin configured for VR0 HOT event */
0271   uint8_t      VR0HotPolarity;  /* GPIO polarity for VR0 HOT event */
0272   uint8_t      VR1HotGpio;      /* GPIO pin configured for VR1 HOT event */
0273   uint8_t      VR1HotPolarity;  /* GPIO polarity for VR1 HOT event */
0274   uint8_t      Padding1;       /* replace GPIO pin configured for CTF */
0275   uint8_t      Padding2;       /* replace GPIO polarity for CTF */
0276
0277   /* LED Display Settings */
0278   uint8_t      LedPin0;         /* GPIO number for LedPin[0] */
0279   uint8_t      LedPin1;         /* GPIO number for LedPin[1] */
0280   uint8_t      LedPin2;         /* GPIO number for LedPin[2] */
0281   uint8_t      padding8_4;
0282
0283   /* AVFS */
0284   uint8_t      OverrideBtcGbCksOn;
0285   uint8_t      OverrideAvfsGbCksOn;
0286   uint8_t      PaddingAvfs8[2];
0287
0288   GbVdroopTable_t BtcGbVdroopTableCksOn;
0289   GbVdroopTable_t BtcGbVdroopTableCksOff;
0290
0291   QuadraticInt_t  AvfsGbCksOn;  /* Replacement equation */
0292   QuadraticInt_t  AvfsGbCksOff; /* Replacement equation */
0293
0294   uint8_t      StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
0295
0296   /* Ageing Guardband Parameters */
0297   uint32_t     AConstant[3];
0298   uint16_t     DC_tol_sigma;
0299   uint16_t     Platform_mean;
0300   uint16_t     Platform_sigma;
0301   uint16_t     PSM_Age_CompFactor;
0302
0303   uint32_t     DpmLevelPowerDelta;
0304
0305   uint8_t      EnableBoostState;
0306   uint8_t      AConstant_Shift;
0307   uint8_t      DC_tol_sigma_Shift;
0308   uint8_t      PSM_Age_CompFactor_Shift;
0309
0310   uint16_t     BoostStartTemperature;
0311   uint16_t     BoostStopTemperature;
0312
0313   PllSetting_t GfxBoostState;
0314
0315   uint8_t      AcgEnable[NUM_GFXCLK_DPM_LEVELS];
0316   GbVdroopTable_t AcgBtcGbVdroopTable;
0317   QuadraticInt_t  AcgAvfsGb;
0318
0319   /* ACG Frequency Table, in Mhz */
0320   uint32_t     AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];
0321
0322   /* Padding - ignore */
0323   uint32_t     MmHubPadding[3]; /* SMU internal use */
0324
0325 } PPTable_t;
0326
0327 typedef struct {
0328   uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
0329   uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
0330   uint16_t MinUclk;
0331   uint16_t MaxUclk;
0332
0333   uint8_t  WmSetting;
0334   uint8_t  Padding[3];
0335 } WatermarkRowGeneric_t;
0336
0337 #define NUM_WM_RANGES 4
0338
0339 typedef enum {
0340   WM_SOCCLK = 0,
0341   WM_DCEFCLK,
0342   WM_COUNT,
0343 } WM_CLOCK_e;
0344
0345 typedef struct {
0346   /* Watermarks */
0347   WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0348
0349   uint32_t     MmHubPadding[7]; /* SMU internal use */
0350 } Watermarks_t;
0351
0352 #ifdef PPTABLE_V10_SMU_VERSION
0353 typedef struct {
0354   float        AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
0355   float        AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
0356   float        AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
0357   float        AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
0358   float        DcBtcGb;
0359
0360   uint32_t     MmHubPadding[7]; /* SMU internal use */
0361 } AvfsTable_t;
0362 #else
0363 typedef struct {
0364   uint32_t     AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
0365   uint32_t     AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
0366   uint32_t     AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
0367   uint32_t     AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
0368   uint32_t     DcBtcGb;
0369
0370   uint32_t     MmHubPadding[7]; /* SMU internal use */
0371 } AvfsTable_t;
0372 #endif
0373
0374 typedef struct {
0375   uint16_t avgPsmCount[30];
0376   uint16_t minPsmCount[30];
0377   float    avgPsmVoltage[30];
0378   float    minPsmVoltage[30];
0379
0380   uint32_t MmHubPadding[7]; /* SMU internal use */
0381 } AvfsDebugTable_t;
0382
0383 typedef struct {
0384   uint8_t  AvfsEn;
0385   uint8_t  AvfsVersion;
0386   uint8_t  Padding[2];
0387
0388   int32_t VFT0_m1; /* Q8.24 */
0389   int32_t VFT0_m2; /* Q12.12 */
0390   int32_t VFT0_b;  /* Q32 */
0391
0392   int32_t VFT1_m1; /* Q8.16 */
0393   int32_t VFT1_m2; /* Q12.12 */
0394   int32_t VFT1_b;  /* Q32 */
0395
0396   int32_t VFT2_m1; /* Q8.16 */
0397   int32_t VFT2_m2; /* Q12.12 */
0398   int32_t VFT2_b;  /* Q32 */
0399
0400   int32_t AvfsGb0_m1; /* Q8.16 */
0401   int32_t AvfsGb0_m2; /* Q12.12 */
0402   int32_t AvfsGb0_b;  /* Q32 */
0403
0404   int32_t AcBtcGb_m1; /* Q8.24 */
0405   int32_t AcBtcGb_m2; /* Q12.12 */
0406   int32_t AcBtcGb_b;  /* Q32 */
0407
0408   uint32_t AvfsTempCold;
0409   uint32_t AvfsTempMid;
0410   uint32_t AvfsTempHot;
0411
0412   uint32_t InversionVoltage; /*  in mV with 2 fractional bits */
0413
0414   int32_t P2V_m1; /* Q8.24 */
0415   int32_t P2V_m2; /* Q12.12 */
0416   int32_t P2V_b;  /* Q32 */
0417
0418   uint32_t P2VCharzFreq; /* in 10KHz units */
0419
0420   uint32_t EnabledAvfsModules;
0421
0422   uint32_t MmHubPadding[7]; /* SMU internal use */
0423 } AvfsFuseOverride_t;
0424
0425 /* These defines are used with the following messages:
0426  * SMC_MSG_TransferTableDram2Smu
0427  * SMC_MSG_TransferTableSmu2Dram
0428  */
0429 #define TABLE_PPTABLE            0
0430 #define TABLE_WATERMARKS         1
0431 #define TABLE_AVFS               2
0432 #define TABLE_AVFS_PSM_DEBUG     3
0433 #define TABLE_AVFS_FUSE_OVERRIDE 4
0434 #define TABLE_PMSTATUSLOG        5
0435 #define TABLE_COUNT              6
0436
0437 /* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
0438 #define UCLK_SWITCH_SLOW 0
0439 #define UCLK_SWITCH_FAST 1
0440
0441 /* GFX DIDT Configuration */
0442 #define SQ_Enable_MASK 0x1
0443 #define SQ_IR_MASK 0x2
0444 #define SQ_PCC_MASK 0x4
0445 #define SQ_EDC_MASK 0x8
0446
0447 #define TCP_Enable_MASK 0x100
0448 #define TCP_IR_MASK 0x200
0449 #define TCP_PCC_MASK 0x400
0450 #define TCP_EDC_MASK 0x800
0451
0452 #define TD_Enable_MASK 0x10000
0453 #define TD_IR_MASK 0x20000
0454 #define TD_PCC_MASK 0x40000
0455 #define TD_EDC_MASK 0x80000
0456
0457 #define DB_Enable_MASK 0x1000000
0458 #define DB_IR_MASK 0x2000000
0459 #define DB_PCC_MASK 0x4000000
0460 #define DB_EDC_MASK 0x8000000
0461
0462 #define SQ_Enable_SHIFT 0
0463 #define SQ_IR_SHIFT 1
0464 #define SQ_PCC_SHIFT 2
0465 #define SQ_EDC_SHIFT 3
0466
0467 #define TCP_Enable_SHIFT 8
0468 #define TCP_IR_SHIFT 9
0469 #define TCP_PCC_SHIFT 10
0470 #define TCP_EDC_SHIFT 11
0471
0472 #define TD_Enable_SHIFT 16
0473 #define TD_IR_SHIFT 17
0474 #define TD_PCC_SHIFT 18
0475 #define TD_EDC_SHIFT 19
0476
0477 #define DB_Enable_SHIFT 24
0478 #define DB_IR_SHIFT 25
0479 #define DB_PCC_SHIFT 26
0480 #define DB_EDC_SHIFT 27
0481
0482 #define REMOVE_FMAX_MARGIN_BIT     0x0
0483 #define REMOVE_DCTOL_MARGIN_BIT    0x1
0484 #define REMOVE_PLATFORM_MARGIN_BIT 0x2
0485
0486 #endif