powerplay/inc/smu9.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU9_H
0025 #define SMU9_H
0026
0027 #pragma pack(push, 1)
0028
0029 #define ENABLE_DEBUG_FEATURES
0030
0031 /* Feature Control Defines */
0032 #define FEATURE_DPM_PREFETCHER_BIT      0
0033 #define FEATURE_DPM_GFXCLK_BIT          1
0034 #define FEATURE_DPM_UCLK_BIT            2
0035 #define FEATURE_DPM_SOCCLK_BIT          3
0036 #define FEATURE_DPM_UVD_BIT             4
0037 #define FEATURE_DPM_VCE_BIT             5
0038 #define FEATURE_ULV_BIT                 6
0039 #define FEATURE_DPM_MP0CLK_BIT          7
0040 #define FEATURE_DPM_LINK_BIT            8
0041 #define FEATURE_DPM_DCEFCLK_BIT         9
0042 #define FEATURE_AVFS_BIT                10
0043 #define FEATURE_DS_GFXCLK_BIT           11
0044 #define FEATURE_DS_SOCCLK_BIT           12
0045 #define FEATURE_DS_LCLK_BIT             13
0046 #define FEATURE_PPT_BIT                 14
0047 #define FEATURE_TDC_BIT                 15
0048 #define FEATURE_THERMAL_BIT             16
0049 #define FEATURE_GFX_PER_CU_CG_BIT       17
0050 #define FEATURE_RM_BIT                  18
0051 #define FEATURE_DS_DCEFCLK_BIT          19
0052 #define FEATURE_ACDC_BIT                20
0053 #define FEATURE_VR0HOT_BIT              21
0054 #define FEATURE_VR1HOT_BIT              22
0055 #define FEATURE_FW_CTF_BIT              23
0056 #define FEATURE_LED_DISPLAY_BIT         24
0057 #define FEATURE_FAN_CONTROL_BIT         25
0058 #define FEATURE_FAST_PPT_BIT            26
0059 #define FEATURE_GFX_EDC_BIT             27
0060 #define FEATURE_ACG_BIT                 28
0061 #define FEATURE_PCC_LIMIT_CONTROL_BIT   29
0062 #define FEATURE_SPARE_30_BIT            30
0063 #define FEATURE_SPARE_31_BIT            31
0064
0065 #define NUM_FEATURES                    32
0066
0067 #define FFEATURE_DPM_PREFETCHER_MASK     (1 << FEATURE_DPM_PREFETCHER_BIT     )
0068 #define FFEATURE_DPM_GFXCLK_MASK         (1 << FEATURE_DPM_GFXCLK_BIT         )
0069 #define FFEATURE_DPM_UCLK_MASK           (1 << FEATURE_DPM_UCLK_BIT           )
0070 #define FFEATURE_DPM_SOCCLK_MASK         (1 << FEATURE_DPM_SOCCLK_BIT         )
0071 #define FFEATURE_DPM_UVD_MASK            (1 << FEATURE_DPM_UVD_BIT            )
0072 #define FFEATURE_DPM_VCE_MASK            (1 << FEATURE_DPM_VCE_BIT            )
0073 #define FFEATURE_ULV_MASK                (1 << FEATURE_ULV_BIT                )
0074 #define FFEATURE_DPM_MP0CLK_MASK         (1 << FEATURE_DPM_MP0CLK_BIT         )
0075 #define FFEATURE_DPM_LINK_MASK           (1 << FEATURE_DPM_LINK_BIT           )
0076 #define FFEATURE_DPM_DCEFCLK_MASK        (1 << FEATURE_DPM_DCEFCLK_BIT        )
0077 #define FFEATURE_AVFS_MASK               (1 << FEATURE_AVFS_BIT               )
0078 #define FFEATURE_DS_GFXCLK_MASK          (1 << FEATURE_DS_GFXCLK_BIT          )
0079 #define FFEATURE_DS_SOCCLK_MASK          (1 << FEATURE_DS_SOCCLK_BIT          )
0080 #define FFEATURE_DS_LCLK_MASK            (1 << FEATURE_DS_LCLK_BIT            )
0081 #define FFEATURE_PPT_MASK                (1 << FEATURE_PPT_BIT                )
0082 #define FFEATURE_TDC_MASK                (1 << FEATURE_TDC_BIT                )
0083 #define FFEATURE_THERMAL_MASK            (1 << FEATURE_THERMAL_BIT            )
0084 #define FFEATURE_GFX_PER_CU_CG_MASK      (1 << FEATURE_GFX_PER_CU_CG_BIT      )
0085 #define FFEATURE_RM_MASK                 (1 << FEATURE_RM_BIT                 )
0086 #define FFEATURE_DS_DCEFCLK_MASK         (1 << FEATURE_DS_DCEFCLK_BIT         )
0087 #define FFEATURE_ACDC_MASK               (1 << FEATURE_ACDC_BIT               )
0088 #define FFEATURE_VR0HOT_MASK             (1 << FEATURE_VR0HOT_BIT             )
0089 #define FFEATURE_VR1HOT_MASK             (1 << FEATURE_VR1HOT_BIT             )
0090 #define FFEATURE_FW_CTF_MASK             (1 << FEATURE_FW_CTF_BIT             )
0091 #define FFEATURE_LED_DISPLAY_MASK        (1 << FEATURE_LED_DISPLAY_BIT        )
0092 #define FFEATURE_FAN_CONTROL_MASK        (1 << FEATURE_FAN_CONTROL_BIT        )
0093
0094 #define FEATURE_FAST_PPT_MASK            (1 << FAST_PPT_BIT                   )
0095 #define FEATURE_GFX_EDC_MASK             (1 << FEATURE_GFX_EDC_BIT            )
0096 #define FEATURE_ACG_MASK                 (1 << FEATURE_ACG_BIT                )
0097 #define FEATURE_PCC_LIMIT_CONTROL_MASK   (1 << FEATURE_PCC_LIMIT_CONTROL_BIT  )
0098 #define FFEATURE_SPARE_30_MASK           (1 << FEATURE_SPARE_30_BIT           )
0099 #define FFEATURE_SPARE_31_MASK           (1 << FEATURE_SPARE_31_BIT           )
0100 /* Workload types */
0101 #define WORKLOAD_VR_BIT                 0
0102 #define WORKLOAD_FRTC_BIT               1
0103 #define WORKLOAD_VIDEO_BIT              2
0104 #define WORKLOAD_COMPUTE_BIT            3
0105 #define NUM_WORKLOADS                   4
0106
0107 /* ULV Client Masks */
0108 #define ULV_CLIENT_RLC_MASK         0x00000001
0109 #define ULV_CLIENT_UVD_MASK         0x00000002
0110 #define ULV_CLIENT_VCE_MASK         0x00000004
0111 #define ULV_CLIENT_SDMA0_MASK       0x00000008
0112 #define ULV_CLIENT_SDMA1_MASK       0x00000010
0113 #define ULV_CLIENT_JPEG_MASK        0x00000020
0114 #define ULV_CLIENT_GFXCLK_DPM_MASK  0x00000040
0115 #define ULV_CLIENT_UVD_DPM_MASK     0x00000080
0116 #define ULV_CLIENT_VCE_DPM_MASK     0x00000100
0117 #define ULV_CLIENT_MP0CLK_DPM_MASK  0x00000200
0118 #define ULV_CLIENT_UCLK_DPM_MASK    0x00000400
0119 #define ULV_CLIENT_SOCCLK_DPM_MASK  0x00000800
0120 #define ULV_CLIENT_DCEFCLK_DPM_MASK 0x00001000
0121
0122 typedef struct {
0123     /* MP1_EXT_SCRATCH0 */
0124     uint32_t CurrLevel_GFXCLK  : 4;
0125     uint32_t CurrLevel_UVD     : 4;
0126     uint32_t CurrLevel_VCE     : 4;
0127     uint32_t CurrLevel_LCLK    : 4;
0128     uint32_t CurrLevel_MP0CLK  : 4;
0129     uint32_t CurrLevel_UCLK    : 4;
0130     uint32_t CurrLevel_SOCCLK  : 4;
0131     uint32_t CurrLevel_DCEFCLK : 4;
0132     /* MP1_EXT_SCRATCH1 */
0133     uint32_t TargLevel_GFXCLK  : 4;
0134     uint32_t TargLevel_UVD     : 4;
0135     uint32_t TargLevel_VCE     : 4;
0136     uint32_t TargLevel_LCLK    : 4;
0137     uint32_t TargLevel_MP0CLK  : 4;
0138     uint32_t TargLevel_UCLK    : 4;
0139     uint32_t TargLevel_SOCCLK  : 4;
0140     uint32_t TargLevel_DCEFCLK : 4;
0141     /* MP1_EXT_SCRATCH2-7 */
0142     uint32_t Reserved[6];
0143 } FwStatus_t;
0144
0145 #pragma pack(pop)
0146
0147 #endif
0148