powerplay/inc/smu7_fusion.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU7_FUSION_H
0025 #define SMU7_FUSION_H
0026
0027 #include "smu7.h"
0028
0029 #pragma pack(push, 1)
0030
0031 #define SMU7_DTE_ITERATIONS 5
0032 #define SMU7_DTE_SOURCES 5
0033 #define SMU7_DTE_SINKS 3
0034 #define SMU7_NUM_CPU_TES 2
0035 #define SMU7_NUM_GPU_TES 1
0036 #define SMU7_NUM_NON_TES 2
0037
0038 // All 'soft registers' should be uint32_t.
0039 struct SMU7_SoftRegisters
0040 {
0041     uint32_t        RefClockFrequency;
0042     uint32_t        PmTimerP;
0043     uint32_t        FeatureEnables;
0044     uint32_t        HandshakeDisables;
0045
0046     uint8_t         DisplayPhy1Config;
0047     uint8_t         DisplayPhy2Config;
0048     uint8_t         DisplayPhy3Config;
0049     uint8_t         DisplayPhy4Config;
0050
0051     uint8_t         DisplayPhy5Config;
0052     uint8_t         DisplayPhy6Config;
0053     uint8_t         DisplayPhy7Config;
0054     uint8_t         DisplayPhy8Config;
0055
0056     uint32_t        AverageGraphicsA;
0057     uint32_t        AverageMemoryA;
0058     uint32_t        AverageGioA;
0059
0060     uint8_t         SClkDpmEnabledLevels;
0061     uint8_t         MClkDpmEnabledLevels;
0062     uint8_t         LClkDpmEnabledLevels;
0063     uint8_t         PCIeDpmEnabledLevels;
0064
0065     uint8_t         UVDDpmEnabledLevels;
0066     uint8_t         SAMUDpmEnabledLevels;
0067     uint8_t         ACPDpmEnabledLevels;
0068     uint8_t         VCEDpmEnabledLevels;
0069
0070     uint32_t        DRAM_LOG_ADDR_H;
0071     uint32_t        DRAM_LOG_ADDR_L;
0072     uint32_t        DRAM_LOG_PHY_ADDR_H;
0073     uint32_t        DRAM_LOG_PHY_ADDR_L;
0074     uint32_t        DRAM_LOG_BUFF_SIZE;
0075     uint32_t        UlvEnterC;
0076     uint32_t        UlvTime;
0077     uint32_t        Reserved[3];
0078
0079 };
0080
0081 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
0082
0083 struct SMU7_Fusion_GraphicsLevel
0084 {
0085     uint32_t    MinVddNb;
0086
0087     uint32_t    SclkFrequency;
0088
0089     uint8_t     Vid;
0090     uint8_t     VidOffset;
0091     uint16_t    AT;
0092
0093     uint8_t     PowerThrottle;
0094     uint8_t     GnbSlow;
0095     uint8_t     ForceNbPs1;
0096     uint8_t     SclkDid;
0097
0098     uint8_t     DisplayWatermark;
0099     uint8_t     EnabledForActivity;
0100     uint8_t     EnabledForThrottle;
0101     uint8_t     UpH;
0102
0103     uint8_t     DownH;
0104     uint8_t     VoltageDownH;
0105     uint8_t     DeepSleepDivId;
0106
0107     uint8_t     ClkBypassCntl;
0108
0109     uint32_t    reserved;
0110 };
0111
0112 typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
0113
0114 struct SMU7_Fusion_GIOLevel
0115 {
0116     uint8_t     EnabledForActivity;
0117     uint8_t     LclkDid;
0118     uint8_t     Vid;
0119     uint8_t     VoltageDownH;
0120
0121     uint32_t    MinVddNb;
0122
0123     uint16_t    ResidencyCounter;
0124     uint8_t     UpH;
0125     uint8_t     DownH;
0126
0127     uint32_t    LclkFrequency;
0128
0129     uint8_t     ActivityLevel;
0130     uint8_t     EnabledForThrottle;
0131
0132     uint8_t     ClkBypassCntl;
0133
0134     uint8_t     padding;
0135 };
0136
0137 typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
0138
0139 // UVD VCLK/DCLK state (level) definition.
0140 struct SMU7_Fusion_UvdLevel
0141 {
0142     uint32_t VclkFrequency;
0143     uint32_t DclkFrequency;
0144     uint16_t MinVddNb;
0145     uint8_t  VclkDivider;
0146     uint8_t  DclkDivider;
0147
0148     uint8_t     VClkBypassCntl;
0149     uint8_t     DClkBypassCntl;
0150
0151     uint8_t     padding[2];
0152
0153 };
0154
0155 typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
0156
0157 // Clocks for other external blocks (VCE, ACP, SAMU).
0158 struct SMU7_Fusion_ExtClkLevel
0159 {
0160     uint32_t Frequency;
0161     uint16_t MinVoltage;
0162     uint8_t  Divider;
0163     uint8_t  ClkBypassCntl;
0164
0165     uint32_t Reserved;
0166 };
0167 typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
0168
0169 struct SMU7_Fusion_ACPILevel
0170 {
0171     uint32_t    Flags;
0172     uint32_t    MinVddNb;
0173     uint32_t    SclkFrequency;
0174     uint8_t     SclkDid;
0175     uint8_t     GnbSlow;
0176     uint8_t     ForceNbPs1;
0177     uint8_t     DisplayWatermark;
0178     uint8_t     DeepSleepDivId;
0179     uint8_t     padding[3];
0180 };
0181
0182 typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
0183
0184 struct SMU7_Fusion_NbDpm
0185 {
0186     uint8_t DpmXNbPsHi;
0187     uint8_t DpmXNbPsLo;
0188     uint8_t Dpm0PgNbPsHi;
0189     uint8_t Dpm0PgNbPsLo;
0190     uint8_t EnablePsi1;
0191     uint8_t SkipDPM0;
0192     uint8_t SkipPG;
0193     uint8_t Hysteresis;
0194     uint8_t EnableDpmPstatePoll;
0195     uint8_t padding[3];
0196 };
0197
0198 typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
0199
0200 struct SMU7_Fusion_StateInfo
0201 {
0202     uint32_t SclkFrequency;
0203     uint32_t LclkFrequency;
0204     uint32_t VclkFrequency;
0205     uint32_t DclkFrequency;
0206     uint32_t SamclkFrequency;
0207     uint32_t AclkFrequency;
0208     uint32_t EclkFrequency;
0209     uint8_t  DisplayWatermark;
0210     uint8_t  McArbIndex;
0211     int8_t   SclkIndex;
0212     int8_t   MclkIndex;
0213 };
0214
0215 typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
0216
0217 struct SMU7_Fusion_DpmTable
0218 {
0219     uint32_t                            SystemFlags;
0220
0221     SMU7_PIDController                  GraphicsPIDController;
0222     SMU7_PIDController                  GioPIDController;
0223
0224     uint8_t                            GraphicsDpmLevelCount;
0225     uint8_t                            GIOLevelCount;
0226     uint8_t                            UvdLevelCount;
0227     uint8_t                            VceLevelCount;
0228
0229     uint8_t                            AcpLevelCount;
0230     uint8_t                            SamuLevelCount;
0231     uint16_t                           FpsHighT;
0232
0233     SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
0234     SMU7_Fusion_ACPILevel             ACPILevel;
0235     SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
0236     SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
0237     SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
0238     SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
0239
0240     uint8_t                           UvdBootLevel;
0241     uint8_t                           VceBootLevel;
0242     uint8_t                           AcpBootLevel;
0243     uint8_t                           SamuBootLevel;
0244     uint8_t                           UVDInterval;
0245     uint8_t                           VCEInterval;
0246     uint8_t                           ACPInterval;
0247     uint8_t                           SAMUInterval;
0248
0249     uint8_t                           GraphicsBootLevel;
0250     uint8_t                           GraphicsInterval;
0251     uint8_t                           GraphicsThermThrottleEnable;
0252     uint8_t                           GraphicsVoltageChangeEnable;
0253
0254     uint8_t                           GraphicsClkSlowEnable;
0255     uint8_t                           GraphicsClkSlowDivider;
0256     uint16_t                          FpsLowT;
0257
0258     uint32_t                          DisplayCac;
0259     uint32_t                          LowSclkInterruptT;
0260
0261     uint32_t                          DRAM_LOG_ADDR_H;
0262     uint32_t                          DRAM_LOG_ADDR_L;
0263     uint32_t                          DRAM_LOG_PHY_ADDR_H;
0264     uint32_t                          DRAM_LOG_PHY_ADDR_L;
0265     uint32_t                          DRAM_LOG_BUFF_SIZE;
0266
0267 };
0268
0269 struct SMU7_Fusion_GIODpmTable
0270 {
0271
0272     SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];
0273
0274     SMU7_PIDController                GioPIDController;
0275
0276     uint32_t                          GIOLevelCount;
0277
0278     uint8_t                           Enable;
0279     uint8_t                           GIOVoltageChangeEnable;
0280     uint8_t                           GIOBootLevel;
0281     uint8_t                           padding;
0282     uint8_t                           padding1[2];
0283     uint8_t                           TargetState;
0284     uint8_t                           CurrenttState;
0285     uint8_t                           ThrottleOnHtc;
0286     uint8_t                           ThermThrottleStatus;
0287     uint8_t                           ThermThrottleTempSelect;
0288     uint8_t                           ThermThrottleEnable;
0289     uint16_t                          TemperatureLimitHigh;
0290     uint16_t                          TemperatureLimitLow;
0291
0292 };
0293
0294 typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
0295 typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
0296
0297 #pragma pack(pop)
0298
0299 #endif
0300