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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef SMU75_DISCRETE_H
0025 #define SMU75_DISCRETE_H
0026 
0027 #include "smu75.h"
0028 
0029 #pragma pack(push, 1)
0030 
0031 #define NUM_SCLK_RANGE 8
0032 
0033 #define VCO_3_6 1
0034 #define VCO_2_4 3
0035 
0036 #define POSTDIV_DIV_BY_1  0
0037 #define POSTDIV_DIV_BY_2  1
0038 #define POSTDIV_DIV_BY_4  2
0039 #define POSTDIV_DIV_BY_8  3
0040 #define POSTDIV_DIV_BY_16 4
0041 
0042 struct sclkFcwRange_t {
0043     uint8_t  vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
0044     uint8_t  postdiv;     /* divide by 2^n */
0045     uint16_t fcw_pcc;
0046     uint16_t fcw_trans_upper;
0047     uint16_t fcw_trans_lower;
0048 };
0049 typedef struct sclkFcwRange_t sclkFcwRange_t;
0050 
0051 struct SMIO_Pattern {
0052     uint16_t Voltage;
0053     uint8_t  Smio;
0054     uint8_t  padding;
0055 };
0056 
0057 typedef struct SMIO_Pattern SMIO_Pattern;
0058 
0059 struct SMIO_Table {
0060     SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
0061 };
0062 
0063 typedef struct SMIO_Table SMIO_Table;
0064 
0065 struct SMU_SclkSetting {
0066     uint32_t    SclkFrequency;
0067     uint16_t    Fcw_int;
0068     uint16_t    Fcw_frac;
0069     uint16_t    Pcc_fcw_int;
0070     uint8_t     PllRange;
0071     uint8_t     SSc_En;
0072     uint16_t    Sclk_slew_rate;
0073     uint16_t    Pcc_up_slew_rate;
0074     uint16_t    Pcc_down_slew_rate;
0075     uint16_t    Fcw1_int;
0076     uint16_t    Fcw1_frac;
0077     uint16_t    Sclk_ss_slew_rate;
0078 };
0079 typedef struct SMU_SclkSetting SMU_SclkSetting;
0080 
0081 struct SMU75_Discrete_GraphicsLevel {
0082     SMU_VoltageLevel MinVoltage;
0083 
0084     uint8_t     pcieDpmLevel;
0085     uint8_t     DeepSleepDivId;
0086     uint16_t    ActivityLevel;
0087 
0088     uint32_t    CgSpllFuncCntl3;
0089     uint32_t    CgSpllFuncCntl4;
0090     uint32_t    CcPwrDynRm;
0091     uint32_t    CcPwrDynRm1;
0092 
0093     uint8_t     SclkDid;
0094     uint8_t     padding;
0095     uint8_t     EnabledForActivity;
0096     uint8_t     EnabledForThrottle;
0097     uint8_t     UpHyst;
0098     uint8_t     DownHyst;
0099     uint8_t     VoltageDownHyst;
0100     uint8_t     PowerThrottle;
0101 
0102     SMU_SclkSetting SclkSetting;
0103 
0104     uint8_t  ScksStretchThreshVid[NUM_SCKS_STATE_TYPES];
0105     uint16_t Padding;
0106 };
0107 
0108 typedef struct SMU75_Discrete_GraphicsLevel SMU75_Discrete_GraphicsLevel;
0109 
0110 struct SMU75_Discrete_ACPILevel {
0111     uint32_t    Flags;
0112     SMU_VoltageLevel MinVoltage;
0113     uint32_t    SclkFrequency;
0114     uint8_t     SclkDid;
0115     uint8_t     DisplayWatermark;
0116     uint8_t     DeepSleepDivId;
0117     uint8_t     padding;
0118     uint32_t    CcPwrDynRm;
0119     uint32_t    CcPwrDynRm1;
0120 
0121     SMU_SclkSetting SclkSetting;
0122 };
0123 
0124 typedef struct SMU75_Discrete_ACPILevel SMU75_Discrete_ACPILevel;
0125 
0126 struct SMU75_Discrete_Ulv {
0127     uint32_t    CcPwrDynRm;
0128     uint32_t    CcPwrDynRm1;
0129     uint16_t    VddcOffset;
0130     uint8_t     VddcOffsetVid;
0131     uint8_t     VddcPhase;
0132     uint16_t    BifSclkDfs;
0133     uint16_t    Reserved;
0134 };
0135 
0136 typedef struct SMU75_Discrete_Ulv SMU75_Discrete_Ulv;
0137 
0138 struct SMU75_Discrete_MemoryLevel {
0139     SMU_VoltageLevel MinVoltage;
0140     uint32_t    MinMvdd;
0141 
0142     uint32_t    MclkFrequency;
0143 
0144     uint8_t     StutterEnable;
0145     uint8_t     EnabledForThrottle;
0146     uint8_t     EnabledForActivity;
0147     uint8_t     padding_0;
0148 
0149     uint8_t     UpHyst;
0150     uint8_t     DownHyst;
0151     uint8_t     VoltageDownHyst;
0152     uint8_t     padding_1;
0153 
0154     uint16_t    ActivityLevel;
0155     uint8_t     DisplayWatermark;
0156     uint8_t     padding_2;
0157 
0158     uint16_t    Fcw_int;
0159     uint16_t    Fcw_frac;
0160     uint8_t     Postdiv;
0161     uint8_t     padding_3[3];
0162 };
0163 
0164 typedef struct SMU75_Discrete_MemoryLevel SMU75_Discrete_MemoryLevel;
0165 
0166 struct SMU75_Discrete_LinkLevel {
0167     uint8_t     PcieGenSpeed;
0168     uint8_t     PcieLaneCount;
0169     uint8_t     EnabledForActivity;
0170     uint8_t     SPC;
0171     uint32_t    DownThreshold;
0172     uint32_t    UpThreshold;
0173     uint16_t    BifSclkDfs;
0174     uint16_t    Reserved;
0175 };
0176 
0177 typedef struct SMU75_Discrete_LinkLevel SMU75_Discrete_LinkLevel;
0178 
0179 
0180 /* MC ARB DRAM Timing registers. */
0181 struct SMU75_Discrete_MCArbDramTimingTableEntry {
0182     uint32_t McArbDramTiming;
0183     uint32_t McArbDramTiming2;
0184     uint32_t McArbBurstTime;
0185     uint32_t McArbRfshRate;
0186     uint32_t McArbMisc3;
0187 };
0188 
0189 typedef struct SMU75_Discrete_MCArbDramTimingTableEntry SMU75_Discrete_MCArbDramTimingTableEntry;
0190 
0191 struct SMU75_Discrete_MCArbDramTimingTable {
0192     SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
0193 };
0194 
0195 typedef struct SMU75_Discrete_MCArbDramTimingTable SMU75_Discrete_MCArbDramTimingTable;
0196 
0197 /* UVD VCLK/DCLK state (level) definition. */
0198 struct SMU75_Discrete_UvdLevel {
0199     uint32_t VclkFrequency;
0200     uint32_t DclkFrequency;
0201     SMU_VoltageLevel MinVoltage;
0202     uint8_t  VclkDivider;
0203     uint8_t  DclkDivider;
0204     uint8_t  padding[2];
0205 };
0206 
0207 typedef struct SMU75_Discrete_UvdLevel SMU75_Discrete_UvdLevel;
0208 
0209 /* Clocks for other external blocks (VCE, ACP, SAMU). */
0210 struct SMU75_Discrete_ExtClkLevel {
0211     uint32_t Frequency;
0212     SMU_VoltageLevel MinVoltage;
0213     uint8_t  Divider;
0214     uint8_t  padding[3];
0215 };
0216 
0217 typedef struct SMU75_Discrete_ExtClkLevel SMU75_Discrete_ExtClkLevel;
0218 
0219 struct SMU75_Discrete_StateInfo {
0220     uint32_t SclkFrequency;
0221     uint32_t MclkFrequency;
0222     uint32_t VclkFrequency;
0223     uint32_t DclkFrequency;
0224     uint32_t SamclkFrequency;
0225     uint32_t AclkFrequency;
0226     uint32_t EclkFrequency;
0227     uint16_t MvddVoltage;
0228     uint16_t padding16;
0229     uint8_t  DisplayWatermark;
0230     uint8_t  McArbIndex;
0231     uint8_t  McRegIndex;
0232     uint8_t  SeqIndex;
0233     uint8_t  SclkDid;
0234     int8_t   SclkIndex;
0235     int8_t   MclkIndex;
0236     uint8_t  PCIeGen;
0237 };
0238 
0239 typedef struct SMU75_Discrete_StateInfo SMU75_Discrete_StateInfo;
0240 
0241 struct SMU75_Discrete_DpmTable {
0242     SMU75_PIDController                  GraphicsPIDController;
0243     SMU75_PIDController                  MemoryPIDController;
0244     SMU75_PIDController                  LinkPIDController;
0245 
0246     uint32_t                            SystemFlags;
0247 
0248     uint32_t                            VRConfig;
0249     uint32_t                            SmioMask1;
0250     uint32_t                            SmioMask2;
0251     SMIO_Table                          SmioTable1;
0252     SMIO_Table                          SmioTable2;
0253 
0254     uint32_t                            MvddLevelCount;
0255 
0256     uint8_t                             BapmVddcVidHiSidd        [SMU75_MAX_LEVELS_VDDC];
0257     uint8_t                             BapmVddcVidLoSidd        [SMU75_MAX_LEVELS_VDDC];
0258     uint8_t                             BapmVddcVidHiSidd2       [SMU75_MAX_LEVELS_VDDC];
0259 
0260     uint8_t                             GraphicsDpmLevelCount;
0261     uint8_t                             MemoryDpmLevelCount;
0262     uint8_t                             LinkLevelCount;
0263     uint8_t                             MasterDeepSleepControl;
0264 
0265     uint8_t                             UvdLevelCount;
0266     uint8_t                             VceLevelCount;
0267     uint8_t                             AcpLevelCount;
0268     uint8_t                             SamuLevelCount;
0269 
0270     uint8_t                             ThermOutGpio;
0271     uint8_t                             ThermOutPolarity;
0272     uint8_t                             ThermOutMode;
0273     uint8_t                             BootPhases;
0274 
0275     uint8_t                             VRHotLevel;
0276     uint8_t                             LdoRefSel;
0277 
0278     uint8_t                             Reserved1[2];
0279 
0280     uint16_t                            FanStartTemperature;
0281     uint16_t                            FanStopTemperature;
0282 
0283     uint16_t                            MaxVoltage;
0284     uint16_t                            Reserved2;
0285     uint32_t                            Reserved;
0286 
0287     SMU75_Discrete_GraphicsLevel        GraphicsLevel           [SMU75_MAX_LEVELS_GRAPHICS];
0288     SMU75_Discrete_MemoryLevel          MemoryACPILevel;
0289     SMU75_Discrete_MemoryLevel          MemoryLevel             [SMU75_MAX_LEVELS_MEMORY];
0290     SMU75_Discrete_LinkLevel            LinkLevel               [SMU75_MAX_LEVELS_LINK];
0291     SMU75_Discrete_ACPILevel            ACPILevel;
0292     SMU75_Discrete_UvdLevel             UvdLevel                [SMU75_MAX_LEVELS_UVD];
0293     SMU75_Discrete_ExtClkLevel          VceLevel                [SMU75_MAX_LEVELS_VCE];
0294     SMU75_Discrete_ExtClkLevel          AcpLevel                [SMU75_MAX_LEVELS_ACP];
0295     SMU75_Discrete_ExtClkLevel          SamuLevel               [SMU75_MAX_LEVELS_SAMU];
0296     SMU75_Discrete_Ulv                  Ulv;
0297 
0298     uint8_t                             DisplayWatermark        [SMU75_MAX_LEVELS_MEMORY][SMU75_MAX_LEVELS_GRAPHICS];
0299 
0300     uint32_t                            SclkStepSize;
0301     uint32_t                            Smio                    [SMU75_MAX_ENTRIES_SMIO];
0302 
0303     uint8_t                             UvdBootLevel;
0304     uint8_t                             VceBootLevel;
0305     uint8_t                             AcpBootLevel;
0306     uint8_t                             SamuBootLevel;
0307 
0308     uint8_t                             GraphicsBootLevel;
0309     uint8_t                             GraphicsVoltageChangeEnable;
0310     uint8_t                             GraphicsThermThrottleEnable;
0311     uint8_t                             GraphicsInterval;
0312 
0313     uint8_t                             VoltageInterval;
0314     uint8_t                             ThermalInterval;
0315     uint16_t                            TemperatureLimitHigh;
0316 
0317     uint16_t                            TemperatureLimitLow;
0318     uint8_t                             MemoryBootLevel;
0319     uint8_t                             MemoryVoltageChangeEnable;
0320 
0321     uint16_t                            BootMVdd;
0322     uint8_t                             MemoryInterval;
0323     uint8_t                             MemoryThermThrottleEnable;
0324 
0325     uint16_t                            VoltageResponseTime;
0326     uint16_t                            PhaseResponseTime;
0327 
0328     uint8_t                             PCIeBootLinkLevel;
0329     uint8_t                             PCIeGenInterval;
0330     uint8_t                             DTEInterval;
0331     uint8_t                             DTEMode;
0332 
0333     uint8_t                             SVI2Enable;
0334     uint8_t                             VRHotGpio;
0335     uint8_t                             AcDcGpio;
0336     uint8_t                             ThermGpio;
0337 
0338     uint16_t                            PPM_PkgPwrLimit;
0339     uint16_t                            PPM_TemperatureLimit;
0340 
0341     uint16_t                            DefaultTdp;
0342     uint16_t                            TargetTdp;
0343 
0344     uint16_t                            FpsHighThreshold;
0345     uint16_t                            FpsLowThreshold;
0346 
0347     uint16_t                            BAPMTI_R  [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
0348     uint16_t                            BAPMTI_RC [SMU75_DTE_ITERATIONS][SMU75_DTE_SOURCES][SMU75_DTE_SINKS];
0349 
0350     uint16_t                            TemperatureLimitEdge;
0351     uint16_t                            TemperatureLimitHotspot;
0352 
0353     uint16_t                            BootVddc;
0354     uint16_t                            BootVddci;
0355 
0356     uint16_t                            FanGainEdge;
0357     uint16_t                            FanGainHotspot;
0358 
0359     uint32_t                            LowSclkInterruptThreshold;
0360     uint32_t                            VddGfxReChkWait;
0361 
0362     uint8_t                             ClockStretcherAmount;
0363     uint8_t                             Sclk_CKS_masterEn0_7;
0364     uint8_t                             Sclk_CKS_masterEn8_15;
0365     uint8_t                             DPMFreezeAndForced;
0366 
0367     uint8_t                             Sclk_voltageOffset[8];
0368 
0369     SMU_ClockStretcherDataTable         ClockStretcherDataTable;
0370     SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
0371 
0372     uint32_t                            CurrSclkPllRange;
0373     sclkFcwRange_t                      SclkFcwRangeTable[NUM_SCLK_RANGE];
0374 
0375     GB_VDROOP_TABLE_t                   BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
0376     SMU_QuadraticCoeffs                 AVFSGB_FUSE_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
0377 };
0378 
0379 typedef struct SMU75_Discrete_DpmTable SMU75_Discrete_DpmTable;
0380 
0381 struct SMU75_Discrete_FanTable {
0382     uint16_t FdoMode;
0383     int16_t  TempMin;
0384     int16_t  TempMed;
0385     int16_t  TempMax;
0386     int16_t  Slope1;
0387     int16_t  Slope2;
0388     int16_t  FdoMin;
0389     int16_t  HystUp;
0390     int16_t  HystDown;
0391     int16_t  HystSlope;
0392     int16_t  TempRespLim;
0393     int16_t  TempCurr;
0394     int16_t  SlopeCurr;
0395     int16_t  PwmCurr;
0396     uint32_t RefreshPeriod;
0397     int16_t  FdoMax;
0398     uint8_t  TempSrc;
0399     int8_t   Padding;
0400 };
0401 
0402 typedef struct SMU75_Discrete_FanTable SMU75_Discrete_FanTable;
0403 
0404 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
0405 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
0406 
0407 
0408 
0409 struct SMU7_MclkDpmScoreboard {
0410     uint32_t PercentageBusy;
0411 
0412     int32_t  PIDError;
0413     int32_t  PIDIntegral;
0414     int32_t  PIDOutput;
0415 
0416     uint32_t SigmaDeltaAccum;
0417     uint32_t SigmaDeltaOutput;
0418     uint32_t SigmaDeltaLevel;
0419 
0420     uint32_t UtilizationSetpoint;
0421 
0422     uint8_t  TdpClampMode;
0423     uint8_t  TdcClampMode;
0424     uint8_t  ThermClampMode;
0425     uint8_t  VoltageBusy;
0426 
0427     int8_t   CurrLevel;
0428     int8_t   TargLevel;
0429     uint8_t  LevelChangeInProgress;
0430     uint8_t  UpHyst;
0431 
0432     uint8_t  DownHyst;
0433     uint8_t  VoltageDownHyst;
0434     uint8_t  DpmEnable;
0435     uint8_t  DpmRunning;
0436 
0437     uint8_t  DpmForce;
0438     uint8_t  DpmForceLevel;
0439     uint8_t  padding2;
0440     uint8_t  McArbIndex;
0441 
0442     uint32_t MinimumPerfMclk;
0443 
0444     uint8_t  AcpiReq;
0445     uint8_t  AcpiAck;
0446     uint8_t  MclkSwitchInProgress;
0447     uint8_t  MclkSwitchCritical;
0448 
0449     uint8_t  IgnoreVBlank;
0450     uint8_t  TargetMclkIndex;
0451     uint8_t  TargetMvddIndex;
0452     uint8_t  MclkSwitchResult;
0453 
0454     uint16_t VbiFailureCount;
0455     uint8_t  VbiWaitCounter;
0456     uint8_t  EnabledLevelsChange;
0457 
0458     uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_MEMORY];
0459     uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_MEMORY];
0460 
0461     void     (*TargetStateCalculator)(uint8_t);
0462     void     (*SavedTargetStateCalculator)(uint8_t);
0463 
0464     uint16_t AutoDpmInterval;
0465     uint16_t AutoDpmRange;
0466 
0467     uint16_t VbiTimeoutCount;
0468     uint16_t MclkSwitchingTime;
0469 
0470     uint8_t  fastSwitch;
0471     uint8_t  Save_PIC_VDDGFX_EXIT;
0472     uint8_t  Save_PIC_VDDGFX_ENTER;
0473     uint8_t  VbiTimeout;
0474 
0475     uint32_t HbmTempRegBackup;
0476 };
0477 
0478 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
0479 
0480 struct SMU7_UlvScoreboard {
0481     uint8_t     EnterUlv;
0482     uint8_t     ExitUlv;
0483     uint8_t     UlvActive;
0484     uint8_t     WaitingForUlv;
0485     uint8_t     UlvEnable;
0486     uint8_t     UlvRunning;
0487     uint8_t     UlvMasterEnable;
0488     uint8_t     padding;
0489     uint32_t    UlvAbortedCount;
0490     uint32_t    UlvTimeStamp;
0491 };
0492 
0493 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
0494 
0495 struct VddgfxSavedRegisters {
0496     uint32_t GPU_DBG[3];
0497     uint32_t MEC_BaseAddress_Hi;
0498     uint32_t MEC_BaseAddress_Lo;
0499     uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
0500     uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
0501     uint32_t CP_INT_CNTL;
0502 };
0503 
0504 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
0505 
0506 struct SMU7_VddGfxScoreboard {
0507     uint8_t     VddGfxEnable;
0508     uint8_t     VddGfxActive;
0509     uint8_t     VPUResetOccured;
0510     uint8_t     padding;
0511 
0512     uint32_t    VddGfxEnteredCount;
0513     uint32_t    VddGfxAbortedCount;
0514 
0515     uint32_t    VddGfxVid;
0516 
0517     VddgfxSavedRegisters SavedRegisters;
0518 };
0519 
0520 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
0521 
0522 struct SMU7_TdcLimitScoreboard {
0523     uint8_t  Enable;
0524     uint8_t  Running;
0525     uint16_t Alpha;
0526     uint32_t FilteredIddc;
0527     uint32_t IddcLimit;
0528     uint32_t IddcHyst;
0529     SMU7_HystController_Data HystControllerData;
0530 };
0531 
0532 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
0533 
0534 struct SMU7_PkgPwrLimitScoreboard {
0535     uint8_t  Enable;
0536     uint8_t  Running;
0537     uint16_t Alpha;
0538     uint32_t FilteredPkgPwr;
0539     uint32_t Limit;
0540     uint32_t Hyst;
0541     uint32_t LimitFromDriver;
0542     uint8_t PowerSharingEnabled;
0543     uint8_t PowerSharingCounter;
0544     uint8_t PowerSharingINTEnabled;
0545     uint8_t GFXActivityCounterEnabled;
0546     uint32_t EnergyCount;
0547     uint32_t PSACTCount;
0548     uint8_t RollOverRequired;
0549     uint8_t RollOverCount;
0550     uint8_t padding[2];
0551     SMU7_HystController_Data HystControllerData;
0552 };
0553 
0554 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
0555 
0556 struct SMU7_BapmScoreboard {
0557     uint32_t source_powers[SMU75_DTE_SOURCES];
0558     uint32_t source_powers_last[SMU75_DTE_SOURCES];
0559     int32_t entity_temperatures[SMU75_NUM_GPU_TES];
0560     int32_t initial_entity_temperatures[SMU75_NUM_GPU_TES];
0561     int32_t Limit;
0562     int32_t Hyst;
0563     int32_t therm_influence_coeff_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS * 2];
0564     int32_t therm_node_table[SMU75_DTE_ITERATIONS * SMU75_DTE_SOURCES * SMU75_DTE_SINKS];
0565     uint16_t ConfigTDPPowerScalar;
0566     uint16_t FanSpeedPowerScalar;
0567     uint16_t OverDrivePowerScalar;
0568     uint16_t OverDriveLimitScalar;
0569     uint16_t FinalPowerScalar;
0570     uint8_t VariantID;
0571     uint8_t spare997;
0572 
0573     SMU7_HystController_Data HystControllerData;
0574 
0575     int32_t temperature_gradient_slope;
0576     int32_t temperature_gradient;
0577     uint32_t measured_temperature;
0578 };
0579 
0580 
0581 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
0582 
0583 struct SMU7_AcpiScoreboard {
0584     uint32_t SavedInterruptMask[2];
0585     uint8_t LastACPIRequest;
0586     uint8_t CgBifResp;
0587     uint8_t RequestType;
0588     uint8_t Padding;
0589     SMU75_Discrete_ACPILevel D0Level;
0590 };
0591 
0592 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
0593 
0594 struct SMU75_Discrete_PmFuses {
0595     uint8_t BapmVddCVidHiSidd[8];
0596 
0597     uint8_t BapmVddCVidLoSidd[8];
0598 
0599     uint8_t VddCVid[8];
0600 
0601     uint8_t SviLoadLineEn;
0602     uint8_t SviLoadLineVddC;
0603     uint8_t SviLoadLineTrimVddC;
0604     uint8_t SviLoadLineOffsetVddC;
0605 
0606     uint16_t TDC_VDDC_PkgLimit;
0607     uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
0608     uint8_t TDC_MAWt;
0609 
0610     uint8_t TdcWaterfallCtl;
0611     uint8_t LPMLTemperatureMin;
0612     uint8_t LPMLTemperatureMax;
0613     uint8_t Reserved;
0614 
0615     uint8_t LPMLTemperatureScaler[16];
0616 
0617     int16_t FuzzyFan_ErrorSetDelta;
0618     int16_t FuzzyFan_ErrorRateSetDelta;
0619     int16_t FuzzyFan_PwmSetDelta;
0620     uint16_t Reserved6;
0621 
0622     uint8_t GnbLPML[16];
0623 
0624     uint8_t GnbLPMLMaxVid;
0625     uint8_t GnbLPMLMinVid;
0626     uint8_t Reserved1[2];
0627 
0628     uint16_t BapmVddCBaseLeakageHiSidd;
0629     uint16_t BapmVddCBaseLeakageLoSidd;
0630 
0631     uint16_t  VFT_Temp[3];
0632     uint8_t   Version;
0633     uint8_t   padding;
0634 
0635     SMU_QuadraticCoeffs VFT_ATE[3];
0636 
0637     SMU_QuadraticCoeffs AVFS_GB;
0638     SMU_QuadraticCoeffs ATE_ACBTC_GB;
0639 
0640     SMU_QuadraticCoeffs P2V;
0641 
0642     uint32_t PsmCharzFreq;
0643 
0644     uint16_t InversionVoltage;
0645     uint16_t PsmCharzTemp;
0646 
0647     uint32_t EnabledAvfsModules;
0648 
0649     SMU_QuadraticCoeffs BtcGbv_CksOff;
0650 };
0651 
0652 typedef struct SMU75_Discrete_PmFuses SMU75_Discrete_PmFuses;
0653 
0654 struct SMU7_Discrete_Log_Header_Table {
0655     uint32_t    version;
0656     uint32_t    asic_id;
0657     uint16_t    flags;
0658     uint16_t    entry_size;
0659     uint32_t    total_size;
0660     uint32_t    num_of_entries;
0661     uint8_t     type;
0662     uint8_t     mode;
0663     uint8_t     filler_0[2];
0664     uint32_t    filler_1[2];
0665 };
0666 
0667 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
0668 
0669 struct SMU7_Discrete_Log_Cntl {
0670     uint8_t             Enabled;
0671     uint8_t             Type;
0672     uint8_t             padding[2];
0673     uint32_t            BufferSize;
0674     uint32_t            SamplesLogged;
0675     uint32_t            SampleSize;
0676     uint32_t            AddrL;
0677     uint32_t            AddrH;
0678 };
0679 
0680 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
0681 
0682 #if defined SMU__DGPU_ONLY
0683 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
0684 #endif
0685 
0686 
0687 struct SMU7_Discrete_Cac_Collection_Table {
0688     uint32_t temperature;
0689     uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
0690 };
0691 
0692 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
0693 
0694 struct SMU7_Discrete_Cac_Verification_Table {
0695     uint32_t VddcTotalPower;
0696     uint32_t VddcLeakagePower;
0697     uint32_t VddcConstantPower;
0698     uint32_t VddcGfxDynamicPower;
0699     uint32_t VddcUvdDynamicPower;
0700     uint32_t VddcVceDynamicPower;
0701     uint32_t VddcAcpDynamicPower;
0702     uint32_t VddcPcieDynamicPower;
0703     uint32_t VddcDceDynamicPower;
0704     uint32_t VddcCurrent;
0705     uint32_t VddcVoltage;
0706     uint32_t VddciTotalPower;
0707     uint32_t VddciLeakagePower;
0708     uint32_t VddciConstantPower;
0709     uint32_t VddciDynamicPower;
0710     uint32_t Vddr1TotalPower;
0711     uint32_t Vddr1LeakagePower;
0712     uint32_t Vddr1ConstantPower;
0713     uint32_t Vddr1DynamicPower;
0714     uint32_t spare[4];
0715     uint32_t temperature;
0716 };
0717 
0718 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
0719 
0720 struct SMU7_Discrete_Pm_Status_Table {
0721     int32_t T_meas_max[SMU75_THERMAL_INPUT_LOOP_COUNT];
0722     int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
0723 
0724     uint32_t I_calc_max;
0725     uint32_t I_calc_acc;
0726     uint32_t P_meas_acc;
0727     uint32_t V_meas_load_acc;
0728     uint32_t I_meas_acc;
0729     uint32_t P_meas_acc_vddci;
0730     uint32_t V_meas_load_acc_vddci;
0731     uint32_t I_meas_acc_vddci;
0732 
0733     uint16_t Sclk_dpm_residency[8];
0734     uint16_t Uvd_dpm_residency[8];
0735     uint16_t Vce_dpm_residency[8];
0736     uint16_t Mclk_dpm_residency[4];
0737 
0738     uint32_t P_roc_acc;
0739     uint32_t PkgPwr_max;
0740     uint32_t PkgPwr_acc;
0741     uint32_t MclkSwitchingTime_max;
0742     uint32_t MclkSwitchingTime_acc;
0743     uint32_t FanPwm_acc;
0744     uint32_t FanRpm_acc;
0745     uint32_t Gfx_busy_acc;
0746     uint32_t Mc_busy_acc;
0747     uint32_t Fps_acc;
0748 
0749     uint32_t AccCnt;
0750 };
0751 
0752 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
0753 
0754 struct SMU7_Discrete_AutoWattMan_Status_Table {
0755     int32_t T_meas_acc[SMU75_THERMAL_INPUT_LOOP_COUNT];
0756     uint16_t Sclk_dpm_residency[8];
0757     uint16_t Mclk_dpm_residency[4];
0758     uint32_t TgpPwr_acc;
0759     uint32_t Gfx_busy_acc;
0760     uint32_t Mc_busy_acc;
0761     uint32_t AccCnt;
0762 };
0763 
0764 typedef struct SMU7_Discrete_AutoWattMan_Status_Table SMU7_Discrete_AutoWattMan_Status_Table;
0765 
0766 #define SMU7_MAX_GFX_CU_COUNT 24
0767 #define SMU7_MIN_GFX_CU_COUNT  8
0768 #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT 0
0769 #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK  (0xFFFF << SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT)
0770 #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT 16
0771 #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK  (0xFFFF << SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT)
0772 
0773 struct SMU7_GfxCuPgScoreboard {
0774     uint8_t Enabled;
0775     uint8_t WaterfallUp;
0776     uint8_t WaterfallDown;
0777     uint8_t WaterfallLimit;
0778     uint8_t CurrMaxCu;
0779     uint8_t TargMaxCu;
0780     uint8_t ClampMode;
0781     uint8_t Active;
0782     uint8_t MaxSupportedCu;
0783     uint8_t MinSupportedCu;
0784     uint8_t PendingGfxCuHostInterrupt;
0785     uint8_t LastFilteredMaxCuInteger;
0786     uint16_t FilteredMaxCu;
0787     uint16_t FilteredMaxCuAlpha;
0788     uint16_t FilterResetCount;
0789     uint16_t FilterResetCountLimit;
0790     uint8_t ForceCu;
0791     uint8_t ForceCuCount;
0792     uint8_t AcModeMaxCu;
0793     uint8_t DcModeMaxCu;
0794 };
0795 
0796 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
0797 
0798 #define SMU7_SCLK_CAC 0x561
0799 #define SMU7_MCLK_CAC 0xF9
0800 #define SMU7_VCLK_CAC 0x2DE
0801 #define SMU7_DCLK_CAC 0x2DE
0802 #define SMU7_ECLK_CAC 0x25E
0803 #define SMU7_ACLK_CAC 0x25E
0804 #define SMU7_SAMCLK_CAC 0x25E
0805 #define SMU7_DISPCLK_CAC 0x100
0806 #define SMU7_CAC_CONSTANT 0x2EE3430
0807 #define SMU7_CAC_CONSTANT_SHIFT 18
0808 
0809 #define SMU7_VDDCI_MCLK_CONST        1765
0810 #define SMU7_VDDCI_MCLK_CONST_SHIFT  16
0811 #define SMU7_VDDCI_VDDCI_CONST       50958
0812 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
0813 #define SMU7_VDDCI_CONST             11781
0814 #define SMU7_VDDCI_STROBE_PWR        1331
0815 
0816 #define SMU7_VDDR1_CONST            693
0817 #define SMU7_VDDR1_CAC_WEIGHT       20
0818 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
0819 #define SMU7_VDDR1_STROBE_PWR       512
0820 
0821 #define SMU7_AREA_COEFF_UVD 0xA78
0822 #define SMU7_AREA_COEFF_VCE 0x190A
0823 #define SMU7_AREA_COEFF_ACP 0x22D1
0824 #define SMU7_AREA_COEFF_SAMU 0x534
0825 
0826 #define SMU7_THERM_OUT_MODE_DISABLE       0x0
0827 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
0828 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
0829 
0830 #define SQ_Enable_MASK 0x1
0831 #define SQ_IR_MASK 0x2
0832 #define SQ_PCC_MASK 0x4
0833 #define SQ_EDC_MASK 0x8
0834 
0835 #define TCP_Enable_MASK 0x100
0836 #define TCP_IR_MASK 0x200
0837 #define TCP_PCC_MASK 0x400
0838 #define TCP_EDC_MASK 0x800
0839 
0840 #define TD_Enable_MASK 0x10000
0841 #define TD_IR_MASK 0x20000
0842 #define TD_PCC_MASK 0x40000
0843 #define TD_EDC_MASK 0x80000
0844 
0845 #define DB_Enable_MASK 0x1000000
0846 #define DB_IR_MASK 0x2000000
0847 #define DB_PCC_MASK 0x4000000
0848 #define DB_EDC_MASK 0x8000000
0849 
0850 #define SQ_Enable_SHIFT 0
0851 #define SQ_IR_SHIFT 1
0852 #define SQ_PCC_SHIFT 2
0853 #define SQ_EDC_SHIFT 3
0854 
0855 #define TCP_Enable_SHIFT 8
0856 #define TCP_IR_SHIFT 9
0857 #define TCP_PCC_SHIFT 10
0858 #define TCP_EDC_SHIFT 11
0859 
0860 #define TD_Enable_SHIFT 16
0861 #define TD_IR_SHIFT 17
0862 #define TD_PCC_SHIFT 18
0863 #define TD_EDC_SHIFT 19
0864 
0865 #define DB_Enable_SHIFT 24
0866 #define DB_IR_SHIFT 25
0867 #define DB_PCC_SHIFT 26
0868 #define DB_EDC_SHIFT 27
0869 
0870 #define PMFUSES_AVFSSIZE 104
0871 
0872 #define BTCGB0_Vdroop_Enable_MASK  0x1
0873 #define BTCGB1_Vdroop_Enable_MASK  0x2
0874 #define AVFSGB0_Vdroop_Enable_MASK 0x4
0875 #define AVFSGB1_Vdroop_Enable_MASK 0x8
0876 
0877 #define BTCGB0_Vdroop_Enable_SHIFT  0
0878 #define BTCGB1_Vdroop_Enable_SHIFT  1
0879 #define AVFSGB0_Vdroop_Enable_SHIFT 2
0880 #define AVFSGB1_Vdroop_Enable_SHIFT 3
0881 
0882 #pragma pack(pop)
0883 
0884 
0885 #endif
0886
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