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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef SMU75_H
0024 #define SMU75_H
0025 
0026 #pragma pack(push, 1)
0027 
0028 typedef struct {
0029     uint32_t high;
0030     uint32_t low;
0031 } data_64_t;
0032 
0033 typedef struct {
0034     data_64_t high;
0035     data_64_t low;
0036 } data_128_t;
0037 
0038 #define SMU__DGPU_ONLY
0039 
0040 #define SMU__NUM_SCLK_DPM_STATE  8
0041 #define SMU__NUM_MCLK_DPM_LEVELS 4
0042 #define SMU__NUM_LCLK_DPM_LEVELS 8
0043 #define SMU__NUM_PCIE_DPM_LEVELS 8
0044 
0045 #define SMU7_CONTEXT_ID_SMC        1
0046 #define SMU7_CONTEXT_ID_VBIOS      2
0047 
0048 #define SMU75_MAX_LEVELS_VDDC            16
0049 #define SMU75_MAX_LEVELS_VDDGFX          16
0050 #define SMU75_MAX_LEVELS_VDDCI           8
0051 #define SMU75_MAX_LEVELS_MVDD            4
0052 
0053 #define SMU_MAX_SMIO_LEVELS              4
0054 
0055 #define SMU75_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE
0056 #define SMU75_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS
0057 #define SMU75_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS
0058 #define SMU75_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS
0059 #define SMU75_MAX_LEVELS_UVD             8
0060 #define SMU75_MAX_LEVELS_VCE             8
0061 #define SMU75_MAX_LEVELS_ACP             8
0062 #define SMU75_MAX_LEVELS_SAMU            8
0063 #define SMU75_MAX_ENTRIES_SMIO           32
0064 
0065 #define DPM_NO_LIMIT 0
0066 #define DPM_NO_UP 1
0067 #define DPM_GO_DOWN 2
0068 #define DPM_GO_UP 3
0069 
0070 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
0071 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
0072 
0073 #define GPIO_CLAMP_MODE_VRHOT      1
0074 #define GPIO_CLAMP_MODE_THERM      2
0075 #define GPIO_CLAMP_MODE_DC         4
0076 
0077 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
0078 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
0079 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
0080 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
0081 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
0082 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
0083 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
0084 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
0085 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
0086 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
0087 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
0088 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
0089 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
0090 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
0091 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
0092 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
0093 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
0094 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
0095 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
0096 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
0097 
0098 /* Virtualization Defines */
0099 #define CG_XDMA_MASK  0x1
0100 #define CG_XDMA_SHIFT 0
0101 #define CG_UVD_MASK   0x2
0102 #define CG_UVD_SHIFT  1
0103 #define CG_VCE_MASK   0x4
0104 #define CG_VCE_SHIFT  2
0105 #define CG_SAMU_MASK  0x8
0106 #define CG_SAMU_SHIFT 3
0107 #define CG_GFX_MASK   0x10
0108 #define CG_GFX_SHIFT  4
0109 #define CG_SDMA_MASK  0x20
0110 #define CG_SDMA_SHIFT 5
0111 #define CG_HDP_MASK   0x40
0112 #define CG_HDP_SHIFT  6
0113 #define CG_MC_MASK    0x80
0114 #define CG_MC_SHIFT   7
0115 #define CG_DRM_MASK   0x100
0116 #define CG_DRM_SHIFT  8
0117 #define CG_ROM_MASK   0x200
0118 #define CG_ROM_SHIFT  9
0119 #define CG_BIF_MASK   0x400
0120 #define CG_BIF_SHIFT  10
0121 
0122 #if defined SMU__DGPU_ONLY
0123 #define SMU75_DTE_ITERATIONS 5
0124 #define SMU75_DTE_SOURCES 3
0125 #define SMU75_DTE_SINKS 1
0126 #define SMU75_NUM_CPU_TES 0
0127 #define SMU75_NUM_GPU_TES 1
0128 #define SMU75_NUM_NON_TES 2
0129 #define SMU75_DTE_FAN_SCALAR_MIN 0x100
0130 #define SMU75_DTE_FAN_SCALAR_MAX 0x166
0131 #define SMU75_DTE_FAN_TEMP_MAX 93
0132 #define SMU75_DTE_FAN_TEMP_MIN 83
0133 #endif
0134 #define SMU75_THERMAL_INPUT_LOOP_COUNT 2
0135 #define SMU75_THERMAL_CLAMP_MODE_COUNT 2
0136 
0137 #define EXP_M1_1  93
0138 #define EXP_M2_1  195759
0139 #define EXP_B_1   111176531
0140 
0141 #define EXP_M1_2  67
0142 #define EXP_M2_2  153720
0143 #define EXP_B_2   94415767
0144 
0145 #define EXP_M1_3  48
0146 #define EXP_M2_3  119796
0147 #define EXP_B_3   79195279
0148 
0149 #define EXP_M1_4  550
0150 #define EXP_M2_4  1484190
0151 #define EXP_B_4   1051432828
0152 
0153 #define EXP_M1_5  394
0154 #define EXP_M2_5  1143049
0155 #define EXP_B_5   864288432
0156 
0157 struct SMU7_HystController_Data {
0158     uint16_t waterfall_up;
0159     uint16_t waterfall_down;
0160     uint16_t waterfall_limit;
0161     uint16_t release_cnt;
0162     uint16_t release_limit;
0163     uint16_t spare;
0164 };
0165 
0166 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
0167 
0168 struct SMU75_PIDController {
0169     uint32_t Ki;
0170     int32_t LFWindupUpperLim;
0171     int32_t LFWindupLowerLim;
0172     uint32_t StatePrecision;
0173     uint32_t LfPrecision;
0174     uint32_t LfOffset;
0175     uint32_t MaxState;
0176     uint32_t MaxLfFraction;
0177     uint32_t StateShift;
0178 };
0179 
0180 typedef struct SMU75_PIDController SMU75_PIDController;
0181 
0182 struct SMU7_LocalDpmScoreboard {
0183     uint32_t PercentageBusy;
0184 
0185     int32_t  PIDError;
0186     int32_t  PIDIntegral;
0187     int32_t  PIDOutput;
0188 
0189     uint32_t SigmaDeltaAccum;
0190     uint32_t SigmaDeltaOutput;
0191     uint32_t SigmaDeltaLevel;
0192 
0193     uint32_t UtilizationSetpoint;
0194 
0195     uint8_t  TdpClampMode;
0196     uint8_t  TdcClampMode;
0197     uint8_t  ThermClampMode;
0198     uint8_t  VoltageBusy;
0199 
0200     int8_t   CurrLevel;
0201     int8_t   TargLevel;
0202     uint8_t  LevelChangeInProgress;
0203     uint8_t  UpHyst;
0204 
0205     uint8_t  DownHyst;
0206     uint8_t  VoltageDownHyst;
0207     uint8_t  DpmEnable;
0208     uint8_t  DpmRunning;
0209 
0210     uint8_t  DpmForce;
0211     uint8_t  DpmForceLevel;
0212     uint8_t  DisplayWatermark;
0213     uint8_t  McArbIndex;
0214 
0215     uint32_t MinimumPerfSclk;
0216 
0217     uint8_t  AcpiReq;
0218     uint8_t  AcpiAck;
0219     uint8_t  GfxClkSlow;
0220     uint8_t  GpioClampMode;
0221 
0222     uint8_t  EnableModeSwitchRLCNotification;
0223     uint8_t  EnabledLevelsChange;
0224     uint8_t  DteClampMode;
0225     uint8_t  FpsClampMode;
0226 
0227     uint16_t LevelResidencyCounters [SMU75_MAX_LEVELS_GRAPHICS];
0228     uint16_t LevelSwitchCounters [SMU75_MAX_LEVELS_GRAPHICS];
0229 
0230     void     (*TargetStateCalculator)(uint8_t);
0231     void     (*SavedTargetStateCalculator)(uint8_t);
0232 
0233     uint16_t AutoDpmInterval;
0234     uint16_t AutoDpmRange;
0235 
0236     uint8_t  FpsEnabled;
0237     uint8_t  MaxPerfLevel;
0238     uint8_t  AllowLowClkInterruptToHost;
0239     uint8_t  FpsRunning;
0240 
0241     uint32_t MaxAllowedFrequency;
0242 
0243     uint32_t FilteredSclkFrequency;
0244     uint32_t LastSclkFrequency;
0245     uint32_t FilteredSclkFrequencyCnt;
0246 
0247     uint8_t MinPerfLevel;
0248 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1
0249     uint8_t ScksClampMode;
0250     uint8_t padding[2];
0251 #else
0252     uint8_t padding[3];
0253 #endif
0254 
0255     uint16_t FpsAlpha;
0256     uint16_t DeltaTime;
0257     uint32_t CurrentFps;
0258     uint32_t FilteredFps;
0259     uint32_t FrameCount;
0260     uint32_t FrameCountLast;
0261     uint16_t FpsTargetScalar;
0262     uint16_t FpsWaterfallLimitScalar;
0263     uint16_t FpsAlphaScalar;
0264     uint16_t spare8;
0265     SMU7_HystController_Data HystControllerData;
0266 };
0267 
0268 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
0269 
0270 #define SMU7_MAX_VOLTAGE_CLIENTS 12
0271 
0272 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
0273 
0274 #define VDDC_MASK    0x00007FFF
0275 #define VDDC_SHIFT   0
0276 #define VDDCI_MASK   0x3FFF8000
0277 #define VDDCI_SHIFT  15
0278 #define PHASES_MASK  0xC0000000
0279 #define PHASES_SHIFT 30
0280 
0281 typedef uint32_t SMU_VoltageLevel;
0282 
0283 struct SMU7_VoltageScoreboard {
0284     SMU_VoltageLevel TargetVoltage;
0285     uint16_t MaxVid;
0286     uint8_t  HighestVidOffset;
0287     uint8_t  CurrentVidOffset;
0288 
0289     uint16_t CurrentVddc;
0290     uint16_t CurrentVddci;
0291 
0292     uint8_t  ControllerBusy;
0293     uint8_t  CurrentVid;
0294     uint8_t  CurrentVddciVid;
0295     uint8_t  padding;
0296 
0297     SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
0298     SMU_VoltageLevel TargetVoltageState;
0299     uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
0300 
0301     uint8_t  padding2;
0302     uint8_t  padding3;
0303     uint8_t  ControllerEnable;
0304     uint8_t  ControllerRunning;
0305     uint16_t CurrentStdVoltageHiSidd;
0306     uint16_t CurrentStdVoltageLoSidd;
0307     uint8_t  OverrideVoltage;
0308     uint8_t  padding4;
0309     uint8_t  padding5;
0310     uint8_t  CurrentPhases;
0311 
0312     VoltageChangeHandler_t ChangeVddc;
0313     VoltageChangeHandler_t ChangeVddci;
0314     VoltageChangeHandler_t ChangePhase;
0315     VoltageChangeHandler_t ChangeMvdd;
0316 
0317     VoltageChangeHandler_t functionLinks[6];
0318 
0319     uint16_t * VddcFollower1;
0320     int16_t  Driver_OD_RequestedVidOffset1;
0321     int16_t  Driver_OD_RequestedVidOffset2;
0322 };
0323 
0324 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
0325 
0326 #define SMU7_MAX_PCIE_LINK_SPEEDS 3
0327 
0328 struct SMU7_PCIeLinkSpeedScoreboard {
0329     uint8_t     DpmEnable;
0330     uint8_t     DpmRunning;
0331     uint8_t     DpmForce;
0332     uint8_t     DpmForceLevel;
0333 
0334     uint8_t     CurrentLinkSpeed;
0335     uint8_t     EnabledLevelsChange;
0336     uint16_t    AutoDpmInterval;
0337 
0338     uint16_t    AutoDpmRange;
0339     uint16_t    AutoDpmCount;
0340 
0341     uint8_t     DpmMode;
0342     uint8_t     AcpiReq;
0343     uint8_t     AcpiAck;
0344     uint8_t     CurrentLinkLevel;
0345 };
0346 
0347 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
0348 
0349 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
0350 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
0351 
0352 #define SMU7_SCALE_I  7
0353 #define SMU7_SCALE_R 12
0354 
0355 struct SMU7_PowerScoreboard {
0356     uint32_t GpuPower;
0357 
0358     uint32_t VddcPower;
0359     uint32_t VddcVoltage;
0360     uint32_t VddcCurrent;
0361 
0362     uint32_t VddciPower;
0363     uint32_t VddciVoltage;
0364     uint32_t VddciCurrent;
0365 
0366     uint32_t RocPower;
0367 
0368     uint16_t Telemetry_1_slope;
0369     uint16_t Telemetry_2_slope;
0370     int32_t  Telemetry_1_offset;
0371     int32_t  Telemetry_2_offset;
0372 
0373     uint8_t MCLK_patch_flag;
0374     uint8_t reserved[3];
0375 };
0376 
0377 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
0378 
0379 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
0380 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
0381 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
0382 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
0383 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
0384 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
0385 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
0386 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
0387 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
0388 
0389 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
0390 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
0391 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
0392 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
0393 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
0394 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
0395 
0396 struct SMU75_SoftRegisters {
0397     uint32_t        RefClockFrequency;
0398     uint32_t        PmTimerPeriod;
0399     uint32_t        FeatureEnables;
0400 #if defined (SMU__DGPU_ONLY)
0401     uint32_t        PreVBlankGap;
0402     uint32_t        VBlankTimeout;
0403     uint32_t        TrainTimeGap;
0404     uint32_t        MvddSwitchTime;
0405     uint32_t        LongestAcpiTrainTime;
0406     uint32_t        AcpiDelay;
0407     uint32_t        G5TrainTime;
0408     uint32_t        DelayMpllPwron;
0409     uint32_t        VoltageChangeTimeout;
0410 #endif
0411     uint32_t        HandshakeDisables;
0412 
0413     uint8_t         DisplayPhy1Config;
0414     uint8_t         DisplayPhy2Config;
0415     uint8_t         DisplayPhy3Config;
0416     uint8_t         DisplayPhy4Config;
0417 
0418     uint8_t         DisplayPhy5Config;
0419     uint8_t         DisplayPhy6Config;
0420     uint8_t         DisplayPhy7Config;
0421     uint8_t         DisplayPhy8Config;
0422 
0423     uint32_t        AverageGraphicsActivity;
0424     uint32_t        AverageMemoryActivity;
0425     uint32_t        AverageGioActivity;
0426 
0427     uint8_t         SClkDpmEnabledLevels;
0428     uint8_t         MClkDpmEnabledLevels;
0429     uint8_t         LClkDpmEnabledLevels;
0430     uint8_t         PCIeDpmEnabledLevels;
0431 
0432     uint8_t         UVDDpmEnabledLevels;
0433     uint8_t         SAMUDpmEnabledLevels;
0434     uint8_t         ACPDpmEnabledLevels;
0435     uint8_t         VCEDpmEnabledLevels;
0436 
0437     uint32_t        DRAM_LOG_ADDR_H;
0438     uint32_t        DRAM_LOG_ADDR_L;
0439     uint32_t        DRAM_LOG_PHY_ADDR_H;
0440     uint32_t        DRAM_LOG_PHY_ADDR_L;
0441     uint32_t        DRAM_LOG_BUFF_SIZE;
0442     uint32_t        UlvEnterCount;
0443     uint32_t        UlvTime;
0444     uint32_t        UcodeLoadStatus;
0445     uint32_t        AllowMvddSwitch;
0446     uint8_t         Activity_Weight;
0447     uint8_t         Reserved8[3];
0448 };
0449 
0450 typedef struct SMU75_SoftRegisters SMU75_SoftRegisters;
0451 
0452 struct SMU75_Firmware_Header {
0453     uint32_t Digest[5];
0454     uint32_t Version;
0455     uint32_t HeaderSize;
0456     uint32_t Flags;
0457     uint32_t EntryPoint;
0458     uint32_t CodeSize;
0459     uint32_t ImageSize;
0460 
0461     uint32_t Rtos;
0462     uint32_t SoftRegisters;
0463     uint32_t DpmTable;
0464     uint32_t FanTable;
0465     uint32_t CacConfigTable;
0466     uint32_t CacStatusTable;
0467     uint32_t mcRegisterTable;
0468     uint32_t mcArbDramTimingTable;
0469     uint32_t PmFuseTable;
0470     uint32_t Globals;
0471     uint32_t ClockStretcherTable;
0472     uint32_t VftTable;
0473     uint32_t Reserved1;
0474     uint32_t AvfsCksOff_AvfsGbvTable;
0475     uint32_t AvfsCksOff_BtcGbvTable;
0476     uint32_t MM_AvfsTable;
0477     uint32_t PowerSharingTable;
0478     uint32_t AvfsTable;
0479     uint32_t AvfsCksOffGbvTable;
0480     uint32_t AvfsMeanNSigma;
0481     uint32_t AvfsSclkOffsetTable;
0482     uint32_t Reserved[12];
0483     uint32_t Signature;
0484 };
0485 
0486 typedef struct SMU75_Firmware_Header SMU75_Firmware_Header;
0487 
0488 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
0489 
0490 enum  DisplayConfig {
0491     PowerDown = 1,
0492     DP54x4,
0493     DP54x2,
0494     DP54x1,
0495     DP27x4,
0496     DP27x2,
0497     DP27x1,
0498     HDMI297,
0499     HDMI162,
0500     LVDS,
0501     DP324x4,
0502     DP324x2,
0503     DP324x1
0504 };
0505 
0506 #define MC_BLOCK_COUNT 1
0507 #define CPL_BLOCK_COUNT 5
0508 #define SE_BLOCK_COUNT 15
0509 #define GC_BLOCK_COUNT 24
0510 
0511 struct SMU7_Local_Cac {
0512     uint8_t BlockId;
0513     uint8_t SignalId;
0514     uint8_t Threshold;
0515     uint8_t Padding;
0516 };
0517 
0518 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
0519 
0520 struct SMU7_Local_Cac_Table {
0521     SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
0522     SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
0523     SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
0524     SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
0525 };
0526 
0527 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
0528 
0529 #pragma pack(pop)
0530 
0531 #define CG_SYS_BITMASK_FIRST_BIT      0
0532 #define CG_SYS_BITMASK_LAST_BIT       10
0533 #define CG_SYS_BIF_MGLS_SHIFT         0
0534 #define CG_SYS_ROM_SHIFT              1
0535 #define CG_SYS_MC_MGCG_SHIFT          2
0536 #define CG_SYS_MC_MGLS_SHIFT          3
0537 #define CG_SYS_SDMA_MGCG_SHIFT        4
0538 #define CG_SYS_SDMA_MGLS_SHIFT        5
0539 #define CG_SYS_DRM_MGCG_SHIFT         6
0540 #define CG_SYS_HDP_MGCG_SHIFT         7
0541 #define CG_SYS_HDP_MGLS_SHIFT         8
0542 #define CG_SYS_DRM_MGLS_SHIFT         9
0543 #define CG_SYS_BIF_MGCG_SHIFT         10
0544 
0545 #define CG_SYS_BIF_MGLS_MASK          0x1
0546 #define CG_SYS_ROM_MASK               0x2
0547 #define CG_SYS_MC_MGCG_MASK           0x4
0548 #define CG_SYS_MC_MGLS_MASK           0x8
0549 #define CG_SYS_SDMA_MGCG_MASK         0x10
0550 #define CG_SYS_SDMA_MGLS_MASK         0x20
0551 #define CG_SYS_DRM_MGCG_MASK          0x40
0552 #define CG_SYS_HDP_MGCG_MASK          0x80
0553 #define CG_SYS_HDP_MGLS_MASK          0x100
0554 #define CG_SYS_DRM_MGLS_MASK          0x200
0555 #define CG_SYS_BIF_MGCG_MASK          0x400
0556 
0557 #define CG_GFX_BITMASK_FIRST_BIT      16
0558 #define CG_GFX_BITMASK_LAST_BIT       24
0559 
0560 #define CG_GFX_CGCG_SHIFT             16
0561 #define CG_GFX_CGLS_SHIFT             17
0562 #define CG_CPF_MGCG_SHIFT             18
0563 #define CG_RLC_MGCG_SHIFT             19
0564 #define CG_GFX_OTHERS_MGCG_SHIFT      20
0565 #define CG_GFX_3DCG_SHIFT             21
0566 #define CG_GFX_3DLS_SHIFT             22
0567 #define CG_GFX_RLC_LS_SHIFT           23
0568 #define CG_GFX_CP_LS_SHIFT            24
0569 
0570 #define CG_GFX_CGCG_MASK              0x00010000
0571 #define CG_GFX_CGLS_MASK              0x00020000
0572 #define CG_CPF_MGCG_MASK              0x00040000
0573 #define CG_RLC_MGCG_MASK              0x00080000
0574 #define CG_GFX_OTHERS_MGCG_MASK       0x00100000
0575 #define CG_GFX_3DCG_MASK              0x00200000
0576 #define CG_GFX_3DLS_MASK              0x00400000
0577 #define CG_GFX_RLC_LS_MASK            0x00800000
0578 #define CG_GFX_CP_LS_MASK             0x01000000
0579 
0580 
0581 #define VRCONF_VDDC_MASK         0x000000FF
0582 #define VRCONF_VDDC_SHIFT        0
0583 #define VRCONF_VDDGFX_MASK       0x0000FF00
0584 #define VRCONF_VDDGFX_SHIFT      8
0585 #define VRCONF_VDDCI_MASK        0x00FF0000
0586 #define VRCONF_VDDCI_SHIFT       16
0587 #define VRCONF_MVDD_MASK         0xFF000000
0588 #define VRCONF_MVDD_SHIFT        24
0589 
0590 #define VR_MERGED_WITH_VDDC      0
0591 #define VR_SVI2_PLANE_1          1
0592 #define VR_SVI2_PLANE_2          2
0593 #define VR_SMIO_PATTERN_1        3
0594 #define VR_SMIO_PATTERN_2        4
0595 #define VR_STATIC_VOLTAGE        5
0596 
0597 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4
0598 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4
0599 
0600 #define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
0601 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
0602 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
0603 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
0604 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
0605 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
0606 
0607 struct SMU_ClockStretcherDataTableEntry {
0608     uint8_t minVID;
0609     uint8_t maxVID;
0610 
0611     uint16_t setting;
0612 };
0613 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
0614 
0615 struct SMU_ClockStretcherDataTable {
0616     SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
0617 };
0618 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
0619 
0620 struct SMU_CKS_LOOKUPTableEntry {
0621     uint16_t minFreq;
0622     uint16_t maxFreq;
0623 
0624     uint8_t setting;
0625     uint8_t padding[3];
0626 };
0627 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
0628 
0629 struct SMU_CKS_LOOKUPTable {
0630     SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
0631 };
0632 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
0633 
0634 struct AgmAvfsData_t {
0635     uint16_t avgPsmCount[28];
0636     uint16_t minPsmCount[28];
0637 };
0638 typedef struct AgmAvfsData_t AgmAvfsData_t;
0639 
0640 enum VFT_COLUMNS {
0641     SCLK0,
0642     SCLK1,
0643     SCLK2,
0644     SCLK3,
0645     SCLK4,
0646     SCLK5,
0647     SCLK6,
0648     SCLK7,
0649 
0650     NUM_VFT_COLUMNS
0651 };
0652 enum {
0653   SCS_FUSE_T0,
0654   SCS_FUSE_T1,
0655   NUM_SCS_FUSE_TEMPERATURE
0656 };
0657 enum {
0658   SCKS_ON,
0659   SCKS_OFF,
0660   NUM_SCKS_STATE_TYPES
0661 };
0662 
0663 #define VFT_TABLE_DEFINED
0664 
0665 #define TEMP_RANGE_MAXSTEPS 12
0666 struct VFT_CELL_t {
0667     uint16_t Voltage;
0668 };
0669 
0670 typedef struct VFT_CELL_t VFT_CELL_t;
0671 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1
0672 struct SCS_CELL_t {
0673     uint16_t PsmCnt[NUM_SCKS_STATE_TYPES];
0674 };
0675 typedef struct SCS_CELL_t SCS_CELL_t;
0676 #endif
0677 
0678 struct VFT_TABLE_t {
0679     VFT_CELL_t    Cell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
0680     uint16_t      AvfsGbv [NUM_VFT_COLUMNS];
0681     uint16_t      BtcGbv  [NUM_VFT_COLUMNS];
0682     int16_t       Temperature [TEMP_RANGE_MAXSTEPS];
0683 
0684 #ifdef SMU__FIRMWARE_SCKS_PRESENT__1
0685     SCS_CELL_t    ScksCell[TEMP_RANGE_MAXSTEPS][NUM_VFT_COLUMNS];
0686 #endif
0687 
0688     uint8_t       NumTemperatureSteps;
0689     uint8_t       padding[3];
0690 };
0691 typedef struct VFT_TABLE_t VFT_TABLE_t;
0692 
0693 #define BTCGB_VDROOP_TABLE_MAX_ENTRIES 2
0694 #define AVFSGB_VDROOP_TABLE_MAX_ENTRIES 2
0695 
0696 struct GB_VDROOP_TABLE_t {
0697     int32_t a0;
0698     int32_t a1;
0699     int32_t a2;
0700     uint32_t spare;
0701 };
0702 typedef struct GB_VDROOP_TABLE_t GB_VDROOP_TABLE_t;
0703 
0704 struct SMU_QuadraticCoeffs {
0705     int32_t m1;
0706     int32_t b;
0707 
0708     int16_t m2;
0709     uint8_t m1_shift;
0710     uint8_t m2_shift;
0711 };
0712 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
0713 
0714 struct AVFS_Margin_t {
0715     VFT_CELL_t Cell[NUM_VFT_COLUMNS];
0716 };
0717 typedef struct AVFS_Margin_t AVFS_Margin_t;
0718 
0719 struct AVFS_CksOff_Gbv_t {
0720     VFT_CELL_t Cell[NUM_VFT_COLUMNS];
0721 };
0722 typedef struct AVFS_CksOff_Gbv_t AVFS_CksOff_Gbv_t;
0723 
0724 struct AVFS_CksOff_AvfsGbv_t {
0725     VFT_CELL_t Cell[NUM_VFT_COLUMNS];
0726 };
0727 typedef struct AVFS_CksOff_AvfsGbv_t AVFS_CksOff_AvfsGbv_t;
0728 
0729 struct AVFS_CksOff_BtcGbv_t {
0730     VFT_CELL_t Cell[NUM_VFT_COLUMNS];
0731 };
0732 typedef struct AVFS_CksOff_BtcGbv_t AVFS_CksOff_BtcGbv_t;
0733 
0734 struct AVFS_meanNsigma_t {
0735     uint32_t Aconstant[3];
0736     uint16_t DC_tol_sigma;
0737     uint16_t Platform_mean;
0738     uint16_t Platform_sigma;
0739     uint16_t PSM_Age_CompFactor;
0740     uint8_t  Static_Voltage_Offset[NUM_VFT_COLUMNS];
0741 };
0742 typedef struct AVFS_meanNsigma_t AVFS_meanNsigma_t;
0743 
0744 struct AVFS_Sclk_Offset_t {
0745     uint16_t Sclk_Offset[8];
0746 };
0747 typedef struct AVFS_Sclk_Offset_t AVFS_Sclk_Offset_t;
0748 
0749 struct Power_Sharing_t {
0750     uint32_t EnergyCounter;
0751     uint32_t EngeryThreshold;
0752     uint64_t AM_SCLK_CNT;
0753     uint64_t AM_0_BUSY_CNT;
0754 };
0755 typedef struct Power_Sharing_t  Power_Sharing_t;
0756 
0757 
0758 #endif
0759 
0760
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