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0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef SMU74_DISCRETE_H
0025 #define SMU74_DISCRETE_H
0026 
0027 #include "smu74.h"
0028 
0029 #pragma pack(push, 1)
0030 
0031 
0032 #define NUM_SCLK_RANGE 8
0033 
0034 #define VCO_3_6 1
0035 #define VCO_2_4 3
0036 
0037 #define POSTDIV_DIV_BY_1  0
0038 #define POSTDIV_DIV_BY_2  1
0039 #define POSTDIV_DIV_BY_4  2
0040 #define POSTDIV_DIV_BY_8  3
0041 #define POSTDIV_DIV_BY_16 4
0042 
0043 struct sclkFcwRange_t {
0044     uint8_t  vco_setting;
0045     uint8_t  postdiv;
0046     uint16_t fcw_pcc;
0047 
0048     uint16_t fcw_trans_upper;
0049     uint16_t fcw_trans_lower;
0050 };
0051 typedef struct sclkFcwRange_t sclkFcwRange_t;
0052 
0053 struct SMIO_Pattern {
0054     uint16_t Voltage;
0055     uint8_t  Smio;
0056     uint8_t  padding;
0057 };
0058 
0059 typedef struct SMIO_Pattern SMIO_Pattern;
0060 
0061 struct SMIO_Table {
0062     SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
0063 };
0064 
0065 typedef struct SMIO_Table SMIO_Table;
0066 
0067 struct SMU_SclkSetting {
0068     uint32_t    SclkFrequency;
0069     uint16_t    Fcw_int;
0070     uint16_t    Fcw_frac;
0071     uint16_t    Pcc_fcw_int;
0072     uint8_t     PllRange;
0073     uint8_t     SSc_En;
0074     uint16_t    Sclk_slew_rate;
0075     uint16_t    Pcc_up_slew_rate;
0076     uint16_t    Pcc_down_slew_rate;
0077     uint16_t    Fcw1_int;
0078     uint16_t    Fcw1_frac;
0079     uint16_t    Sclk_ss_slew_rate;
0080 };
0081 typedef struct SMU_SclkSetting SMU_SclkSetting;
0082 
0083 struct SMU74_Discrete_GraphicsLevel {
0084     SMU_VoltageLevel MinVoltage;
0085     uint8_t     pcieDpmLevel;
0086     uint8_t     DeepSleepDivId;
0087     uint16_t    ActivityLevel;
0088     uint32_t    CgSpllFuncCntl3;
0089     uint32_t    CgSpllFuncCntl4;
0090     uint32_t    CcPwrDynRm;
0091     uint32_t    CcPwrDynRm1;
0092     uint8_t     SclkDid;
0093     uint8_t     padding;
0094     uint8_t     EnabledForActivity;
0095     uint8_t     EnabledForThrottle;
0096     uint8_t     UpHyst;
0097     uint8_t     DownHyst;
0098     uint8_t     VoltageDownHyst;
0099     uint8_t     PowerThrottle;
0100     SMU_SclkSetting SclkSetting;
0101 };
0102 
0103 typedef struct SMU74_Discrete_GraphicsLevel SMU74_Discrete_GraphicsLevel;
0104 
0105 struct SMU74_Discrete_ACPILevel {
0106     uint32_t    Flags;
0107     SMU_VoltageLevel MinVoltage;
0108     uint32_t    SclkFrequency;
0109     uint8_t     SclkDid;
0110     uint8_t     DisplayWatermark;
0111     uint8_t     DeepSleepDivId;
0112     uint8_t     padding;
0113     uint32_t    CcPwrDynRm;
0114     uint32_t    CcPwrDynRm1;
0115 
0116     SMU_SclkSetting SclkSetting;
0117 };
0118 
0119 typedef struct SMU74_Discrete_ACPILevel SMU74_Discrete_ACPILevel;
0120 
0121 struct SMU74_Discrete_Ulv {
0122     uint32_t    CcPwrDynRm;
0123     uint32_t    CcPwrDynRm1;
0124     uint16_t    VddcOffset;
0125     uint8_t     VddcOffsetVid;
0126     uint8_t     VddcPhase;
0127     uint16_t    BifSclkDfs;
0128     uint16_t    Reserved;
0129 };
0130 
0131 typedef struct SMU74_Discrete_Ulv SMU74_Discrete_Ulv;
0132 
0133 struct SMU74_Discrete_MemoryLevel {
0134     SMU_VoltageLevel MinVoltage;
0135     uint32_t    MinMvdd;
0136 
0137     uint32_t    MclkFrequency;
0138 
0139     uint8_t     StutterEnable;
0140     uint8_t     EnabledForThrottle;
0141     uint8_t     EnabledForActivity;
0142     uint8_t     padding_0;
0143 
0144     uint8_t     UpHyst;
0145     uint8_t     DownHyst;
0146     uint8_t     VoltageDownHyst;
0147     uint8_t     padding_1;
0148 
0149     uint16_t    ActivityLevel;
0150     uint8_t     DisplayWatermark;
0151     uint8_t     Reserved;
0152 };
0153 
0154 typedef struct SMU74_Discrete_MemoryLevel SMU74_Discrete_MemoryLevel;
0155 
0156 struct SMU74_Discrete_LinkLevel {
0157     uint8_t     PcieGenSpeed;
0158     uint8_t     PcieLaneCount;
0159     uint8_t     EnabledForActivity;
0160     uint8_t     SPC;
0161     uint32_t    DownThreshold;
0162     uint32_t    UpThreshold;
0163     uint16_t    BifSclkDfs;
0164     uint16_t    Reserved;
0165 };
0166 
0167 typedef struct SMU74_Discrete_LinkLevel SMU74_Discrete_LinkLevel;
0168 
0169 struct SMU74_Discrete_MCArbDramTimingTableEntry {
0170     uint32_t McArbDramTiming;
0171     uint32_t McArbDramTiming2;
0172     uint8_t  McArbBurstTime;
0173     uint8_t  padding[3];
0174 };
0175 
0176 typedef struct SMU74_Discrete_MCArbDramTimingTableEntry SMU74_Discrete_MCArbDramTimingTableEntry;
0177 
0178 struct SMU74_Discrete_MCArbDramTimingTable {
0179     SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
0180 };
0181 
0182 typedef struct SMU74_Discrete_MCArbDramTimingTable SMU74_Discrete_MCArbDramTimingTable;
0183 
0184 struct SMU74_Discrete_UvdLevel {
0185     uint32_t VclkFrequency;
0186     uint32_t DclkFrequency;
0187     SMU_VoltageLevel MinVoltage;
0188     uint8_t  VclkDivider;
0189     uint8_t  DclkDivider;
0190     uint8_t  padding[2];
0191 };
0192 
0193 typedef struct SMU74_Discrete_UvdLevel SMU74_Discrete_UvdLevel;
0194 
0195 struct SMU74_Discrete_ExtClkLevel {
0196     uint32_t Frequency;
0197     SMU_VoltageLevel MinVoltage;
0198     uint8_t  Divider;
0199     uint8_t  padding[3];
0200 };
0201 
0202 typedef struct SMU74_Discrete_ExtClkLevel SMU74_Discrete_ExtClkLevel;
0203 
0204 struct SMU74_Discrete_StateInfo {
0205     uint32_t SclkFrequency;
0206     uint32_t MclkFrequency;
0207     uint32_t VclkFrequency;
0208     uint32_t DclkFrequency;
0209     uint32_t SamclkFrequency;
0210     uint32_t AclkFrequency;
0211     uint32_t EclkFrequency;
0212     uint16_t MvddVoltage;
0213     uint16_t padding16;
0214     uint8_t  DisplayWatermark;
0215     uint8_t  McArbIndex;
0216     uint8_t  McRegIndex;
0217     uint8_t  SeqIndex;
0218     uint8_t  SclkDid;
0219     int8_t   SclkIndex;
0220     int8_t   MclkIndex;
0221     uint8_t  PCIeGen;
0222 };
0223 
0224 typedef struct SMU74_Discrete_StateInfo SMU74_Discrete_StateInfo;
0225 
0226 struct SMU_QuadraticCoeffs {
0227     int32_t m1;
0228     uint32_t b;
0229 
0230     int16_t m2;
0231     uint8_t m1_shift;
0232     uint8_t m2_shift;
0233 };
0234 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
0235 
0236 struct SMU74_Discrete_DpmTable {
0237 
0238     SMU74_PIDController                  GraphicsPIDController;
0239     SMU74_PIDController                  MemoryPIDController;
0240     SMU74_PIDController                  LinkPIDController;
0241 
0242     uint32_t                            SystemFlags;
0243 
0244     uint32_t                            VRConfig;
0245     uint32_t                            SmioMask1;
0246     uint32_t                            SmioMask2;
0247     SMIO_Table                          SmioTable1;
0248     SMIO_Table                          SmioTable2;
0249 
0250     uint32_t                            MvddLevelCount;
0251 
0252 
0253     uint8_t                             BapmVddcVidHiSidd[SMU74_MAX_LEVELS_VDDC];
0254     uint8_t                             BapmVddcVidLoSidd[SMU74_MAX_LEVELS_VDDC];
0255     uint8_t                             BapmVddcVidHiSidd2[SMU74_MAX_LEVELS_VDDC];
0256 
0257     uint8_t                             GraphicsDpmLevelCount;
0258     uint8_t                             MemoryDpmLevelCount;
0259     uint8_t                             LinkLevelCount;
0260     uint8_t                             MasterDeepSleepControl;
0261 
0262     uint8_t                             UvdLevelCount;
0263     uint8_t                             VceLevelCount;
0264     uint8_t                             AcpLevelCount;
0265     uint8_t                             SamuLevelCount;
0266 
0267     uint8_t                             ThermOutGpio;
0268     uint8_t                             ThermOutPolarity;
0269     uint8_t                             ThermOutMode;
0270     uint8_t                             BootPhases;
0271 
0272     uint8_t                             VRHotLevel;
0273     uint8_t                             LdoRefSel;
0274     uint8_t                             SharedRails;
0275     uint8_t                             Reserved1;
0276     uint16_t                            FanStartTemperature;
0277     uint16_t                            FanStopTemperature;
0278     uint16_t                            MaxVoltage;
0279     uint16_t                            Reserved2;
0280     uint32_t                            Reserved[1];
0281 
0282     SMU74_Discrete_GraphicsLevel        GraphicsLevel[SMU74_MAX_LEVELS_GRAPHICS];
0283     SMU74_Discrete_MemoryLevel          MemoryACPILevel;
0284     SMU74_Discrete_MemoryLevel          MemoryLevel[SMU74_MAX_LEVELS_MEMORY];
0285     SMU74_Discrete_LinkLevel            LinkLevel[SMU74_MAX_LEVELS_LINK];
0286     SMU74_Discrete_ACPILevel            ACPILevel;
0287     SMU74_Discrete_UvdLevel             UvdLevel[SMU74_MAX_LEVELS_UVD];
0288     SMU74_Discrete_ExtClkLevel          VceLevel[SMU74_MAX_LEVELS_VCE];
0289     SMU74_Discrete_ExtClkLevel          AcpLevel[SMU74_MAX_LEVELS_ACP];
0290     SMU74_Discrete_ExtClkLevel          SamuLevel[SMU74_MAX_LEVELS_SAMU];
0291     SMU74_Discrete_Ulv                  Ulv;
0292 
0293     uint8_t                             DisplayWatermark[SMU74_MAX_LEVELS_MEMORY][SMU74_MAX_LEVELS_GRAPHICS];
0294 
0295     uint32_t                            SclkStepSize;
0296     uint32_t                            Smio[SMU74_MAX_ENTRIES_SMIO];
0297 
0298     uint8_t                             UvdBootLevel;
0299     uint8_t                             VceBootLevel;
0300     uint8_t                             AcpBootLevel;
0301     uint8_t                             SamuBootLevel;
0302 
0303     uint8_t                             GraphicsBootLevel;
0304     uint8_t                             GraphicsVoltageChangeEnable;
0305     uint8_t                             GraphicsThermThrottleEnable;
0306     uint8_t                             GraphicsInterval;
0307 
0308     uint8_t                             VoltageInterval;
0309     uint8_t                             ThermalInterval;
0310     uint16_t                            TemperatureLimitHigh;
0311 
0312     uint16_t                            TemperatureLimitLow;
0313     uint8_t                             MemoryBootLevel;
0314     uint8_t                             MemoryVoltageChangeEnable;
0315 
0316     uint16_t                            BootMVdd;
0317     uint8_t                             MemoryInterval;
0318     uint8_t                             MemoryThermThrottleEnable;
0319 
0320     uint16_t                            VoltageResponseTime;
0321     uint16_t                            PhaseResponseTime;
0322 
0323     uint8_t                             PCIeBootLinkLevel;
0324     uint8_t                             PCIeGenInterval;
0325     uint8_t                             DTEInterval;
0326     uint8_t                             DTEMode;
0327 
0328     uint8_t                             SVI2Enable;
0329     uint8_t                             VRHotGpio;
0330     uint8_t                             AcDcGpio;
0331     uint8_t                             ThermGpio;
0332 
0333     uint16_t                            PPM_PkgPwrLimit;
0334     uint16_t                            PPM_TemperatureLimit;
0335 
0336     uint16_t                            DefaultTdp;
0337     uint16_t                            TargetTdp;
0338 
0339     uint16_t                            FpsHighThreshold;
0340     uint16_t                            FpsLowThreshold;
0341 
0342     uint16_t                            BAPMTI_R[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
0343     uint16_t                            BAPMTI_RC[SMU74_DTE_ITERATIONS][SMU74_DTE_SOURCES][SMU74_DTE_SINKS];
0344 
0345     uint16_t                            TemperatureLimitEdge;
0346     uint16_t                            TemperatureLimitHotspot;
0347 
0348     uint16_t                            BootVddc;
0349     uint16_t                            BootVddci;
0350 
0351     uint16_t                            FanGainEdge;
0352     uint16_t                            FanGainHotspot;
0353 
0354     uint32_t                            LowSclkInterruptThreshold;
0355     uint32_t                            VddGfxReChkWait;
0356 
0357     uint8_t                             ClockStretcherAmount;
0358     uint8_t                             Sclk_CKS_masterEn0_7;
0359     uint8_t                             Sclk_CKS_masterEn8_15;
0360     uint8_t                             DPMFreezeAndForced;
0361 
0362     uint8_t                             Sclk_voltageOffset[8];
0363 
0364     SMU_ClockStretcherDataTable         ClockStretcherDataTable;
0365     SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
0366 
0367     uint32_t                            CurrSclkPllRange;
0368     sclkFcwRange_t                      SclkFcwRangeTable[NUM_SCLK_RANGE];
0369     GB_VDROOP_TABLE_t                   BTCGB_VDROOP_TABLE[BTCGB_VDROOP_TABLE_MAX_ENTRIES];
0370     SMU_QuadraticCoeffs                 AVFSGB_VDROOP_TABLE[AVFSGB_VDROOP_TABLE_MAX_ENTRIES];
0371 };
0372 
0373 typedef struct SMU74_Discrete_DpmTable SMU74_Discrete_DpmTable;
0374 
0375 
0376 struct SMU74_Discrete_FanTable {
0377     uint16_t FdoMode;
0378     int16_t  TempMin;
0379     int16_t  TempMed;
0380     int16_t  TempMax;
0381     int16_t  Slope1;
0382     int16_t  Slope2;
0383     int16_t  FdoMin;
0384     int16_t  HystUp;
0385     int16_t  HystDown;
0386     int16_t  HystSlope;
0387     int16_t  TempRespLim;
0388     int16_t  TempCurr;
0389     int16_t  SlopeCurr;
0390     int16_t  PwmCurr;
0391     uint32_t RefreshPeriod;
0392     int16_t  FdoMax;
0393     uint8_t  TempSrc;
0394     int8_t   Padding;
0395 };
0396 
0397 typedef struct SMU74_Discrete_FanTable SMU74_Discrete_FanTable;
0398 
0399 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
0400 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
0401 
0402 
0403 struct SMU7_MclkDpmScoreboard {
0404     uint32_t PercentageBusy;
0405 
0406     int32_t  PIDError;
0407     int32_t  PIDIntegral;
0408     int32_t  PIDOutput;
0409 
0410     uint32_t SigmaDeltaAccum;
0411     uint32_t SigmaDeltaOutput;
0412     uint32_t SigmaDeltaLevel;
0413 
0414     uint32_t UtilizationSetpoint;
0415 
0416     uint8_t  TdpClampMode;
0417     uint8_t  TdcClampMode;
0418     uint8_t  ThermClampMode;
0419     uint8_t  VoltageBusy;
0420 
0421     int8_t   CurrLevel;
0422     int8_t   TargLevel;
0423     uint8_t  LevelChangeInProgress;
0424     uint8_t  UpHyst;
0425 
0426     uint8_t  DownHyst;
0427     uint8_t  VoltageDownHyst;
0428     uint8_t  DpmEnable;
0429     uint8_t  DpmRunning;
0430 
0431     uint8_t  DpmForce;
0432     uint8_t  DpmForceLevel;
0433     uint8_t  padding2;
0434     uint8_t  McArbIndex;
0435 
0436     uint32_t MinimumPerfMclk;
0437 
0438     uint8_t  AcpiReq;
0439     uint8_t  AcpiAck;
0440     uint8_t  MclkSwitchInProgress;
0441     uint8_t  MclkSwitchCritical;
0442 
0443     uint8_t  IgnoreVBlank;
0444     uint8_t  TargetMclkIndex;
0445     uint16_t VbiFailureCount;
0446     uint8_t  VbiWaitCounter;
0447     uint8_t  EnabledLevelsChange;
0448 
0449     uint16_t LevelResidencyCounters[SMU74_MAX_LEVELS_MEMORY];
0450     uint16_t LevelSwitchCounters[SMU74_MAX_LEVELS_MEMORY];
0451 
0452     void     (*TargetStateCalculator)(uint8_t);
0453     void     (*SavedTargetStateCalculator)(uint8_t);
0454 
0455     uint16_t AutoDpmInterval;
0456     uint16_t AutoDpmRange;
0457 
0458     uint16_t VbiTimeoutCount;
0459     uint16_t MclkSwitchingTime;
0460 
0461     uint8_t  fastSwitch;
0462     uint8_t  Save_PIC_VDDGFX_EXIT;
0463     uint8_t  Save_PIC_VDDGFX_ENTER;
0464     uint8_t  padding;
0465 };
0466 
0467 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
0468 
0469 struct SMU7_UlvScoreboard {
0470     uint8_t     EnterUlv;
0471     uint8_t     ExitUlv;
0472     uint8_t     UlvActive;
0473     uint8_t     WaitingForUlv;
0474     uint8_t     UlvEnable;
0475     uint8_t     UlvRunning;
0476     uint8_t     UlvMasterEnable;
0477     uint8_t     padding;
0478     uint32_t    UlvAbortedCount;
0479     uint32_t    UlvTimeStamp;
0480 };
0481 
0482 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
0483 
0484 struct VddgfxSavedRegisters {
0485     uint32_t GPU_DBG[3];
0486     uint32_t MEC_BaseAddress_Hi;
0487     uint32_t MEC_BaseAddress_Lo;
0488     uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
0489     uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
0490     uint32_t CP_INT_CNTL;
0491 };
0492 
0493 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
0494 
0495 struct SMU7_VddGfxScoreboard {
0496     uint8_t     VddGfxEnable;
0497     uint8_t     VddGfxActive;
0498     uint8_t     VPUResetOccured;
0499     uint8_t     padding;
0500 
0501     uint32_t    VddGfxEnteredCount;
0502     uint32_t    VddGfxAbortedCount;
0503 
0504     uint32_t    VddGfxVid;
0505 
0506     VddgfxSavedRegisters SavedRegisters;
0507 };
0508 
0509 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
0510 
0511 struct SMU7_TdcLimitScoreboard {
0512     uint8_t  Enable;
0513     uint8_t  Running;
0514     uint16_t Alpha;
0515     uint32_t FilteredIddc;
0516     uint32_t IddcLimit;
0517     uint32_t IddcHyst;
0518     SMU7_HystController_Data HystControllerData;
0519 };
0520 
0521 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
0522 
0523 struct SMU7_PkgPwrLimitScoreboard {
0524     uint8_t  Enable;
0525     uint8_t  Running;
0526     uint16_t Alpha;
0527     uint32_t FilteredPkgPwr;
0528     uint32_t Limit;
0529     uint32_t Hyst;
0530     uint32_t LimitFromDriver;
0531     SMU7_HystController_Data HystControllerData;
0532 };
0533 
0534 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
0535 
0536 struct SMU7_BapmScoreboard {
0537     uint32_t source_powers[SMU74_DTE_SOURCES];
0538     uint32_t source_powers_last[SMU74_DTE_SOURCES];
0539     int32_t entity_temperatures[SMU74_NUM_GPU_TES];
0540     int32_t initial_entity_temperatures[SMU74_NUM_GPU_TES];
0541     int32_t Limit;
0542     int32_t Hyst;
0543     int32_t therm_influence_coeff_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS * 2];
0544     int32_t therm_node_table[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS];
0545     uint16_t ConfigTDPPowerScalar;
0546     uint16_t FanSpeedPowerScalar;
0547     uint16_t OverDrivePowerScalar;
0548     uint16_t OverDriveLimitScalar;
0549     uint16_t FinalPowerScalar;
0550     uint8_t VariantID;
0551     uint8_t spare997;
0552 
0553     SMU7_HystController_Data HystControllerData;
0554 
0555     int32_t temperature_gradient_slope;
0556     int32_t temperature_gradient;
0557     uint32_t measured_temperature;
0558 };
0559 
0560 
0561 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
0562 
0563 struct SMU7_AcpiScoreboard {
0564     uint32_t SavedInterruptMask[2];
0565     uint8_t LastACPIRequest;
0566     uint8_t CgBifResp;
0567     uint8_t RequestType;
0568     uint8_t Padding;
0569     SMU74_Discrete_ACPILevel D0Level;
0570 };
0571 
0572 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
0573 
0574 struct SMU74_Discrete_PmFuses {
0575     uint8_t BapmVddCVidHiSidd[8];
0576     uint8_t BapmVddCVidLoSidd[8];
0577     uint8_t VddCVid[8];
0578     uint8_t SviLoadLineEn;
0579     uint8_t SviLoadLineVddC;
0580     uint8_t SviLoadLineTrimVddC;
0581     uint8_t SviLoadLineOffsetVddC;
0582     uint16_t TDC_VDDC_PkgLimit;
0583     uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
0584     uint8_t TDC_MAWt;
0585     uint8_t TdcWaterfallCtl;
0586     uint8_t LPMLTemperatureMin;
0587     uint8_t LPMLTemperatureMax;
0588     uint8_t Reserved;
0589 
0590     uint8_t LPMLTemperatureScaler[16];
0591 
0592     int16_t FuzzyFan_ErrorSetDelta;
0593     int16_t FuzzyFan_ErrorRateSetDelta;
0594     int16_t FuzzyFan_PwmSetDelta;
0595     uint16_t Reserved6;
0596 
0597     uint8_t GnbLPML[16];
0598 
0599     uint8_t GnbLPMLMaxVid;
0600     uint8_t GnbLPMLMinVid;
0601     uint8_t Reserved1[2];
0602 
0603     uint16_t BapmVddCBaseLeakageHiSidd;
0604     uint16_t BapmVddCBaseLeakageLoSidd;
0605 
0606     uint16_t  VFT_Temp[3];
0607     uint16_t  padding;
0608 
0609     SMU_QuadraticCoeffs VFT_ATE[3];
0610 
0611     SMU_QuadraticCoeffs AVFS_GB;
0612     SMU_QuadraticCoeffs ATE_ACBTC_GB;
0613 
0614     SMU_QuadraticCoeffs P2V;
0615 
0616     uint32_t PsmCharzFreq;
0617 
0618     uint16_t InversionVoltage;
0619     uint16_t PsmCharzTemp;
0620 
0621     uint32_t EnabledAvfsModules;
0622 };
0623 
0624 typedef struct SMU74_Discrete_PmFuses SMU74_Discrete_PmFuses;
0625 
0626 struct SMU7_Discrete_Log_Header_Table {
0627     uint32_t    version;
0628     uint32_t    asic_id;
0629     uint16_t    flags;
0630     uint16_t    entry_size;
0631     uint32_t    total_size;
0632     uint32_t    num_of_entries;
0633     uint8_t     type;
0634     uint8_t     mode;
0635     uint8_t     filler_0[2];
0636     uint32_t    filler_1[2];
0637 };
0638 
0639 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
0640 
0641 struct SMU7_Discrete_Log_Cntl {
0642     uint8_t             Enabled;
0643     uint8_t             Type;
0644     uint8_t             padding[2];
0645     uint32_t            BufferSize;
0646     uint32_t            SamplesLogged;
0647     uint32_t            SampleSize;
0648     uint32_t            AddrL;
0649     uint32_t            AddrH;
0650 };
0651 
0652 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
0653 
0654 #if defined SMU__DGPU_ONLY
0655 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
0656 #endif
0657 
0658 
0659 struct SMU7_Discrete_Cac_Collection_Table {
0660     uint32_t temperature;
0661     uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
0662 };
0663 
0664 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
0665 
0666 struct SMU7_Discrete_Cac_Verification_Table {
0667     uint32_t VddcTotalPower;
0668     uint32_t VddcLeakagePower;
0669     uint32_t VddcConstantPower;
0670     uint32_t VddcGfxDynamicPower;
0671     uint32_t VddcUvdDynamicPower;
0672     uint32_t VddcVceDynamicPower;
0673     uint32_t VddcAcpDynamicPower;
0674     uint32_t VddcPcieDynamicPower;
0675     uint32_t VddcDceDynamicPower;
0676     uint32_t VddcCurrent;
0677     uint32_t VddcVoltage;
0678     uint32_t VddciTotalPower;
0679     uint32_t VddciLeakagePower;
0680     uint32_t VddciConstantPower;
0681     uint32_t VddciDynamicPower;
0682     uint32_t Vddr1TotalPower;
0683     uint32_t Vddr1LeakagePower;
0684     uint32_t Vddr1ConstantPower;
0685     uint32_t Vddr1DynamicPower;
0686     uint32_t spare[4];
0687     uint32_t temperature;
0688 };
0689 
0690 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
0691 
0692 struct SMU7_Discrete_Pm_Status_Table {
0693     int32_t T_meas_max;
0694     int32_t T_meas_acc;
0695     int32_t T_calc_max;
0696     int32_t T_calc_acc;
0697     uint32_t P_scalar_acc;
0698     uint32_t P_calc_max;
0699     uint32_t P_calc_acc;
0700 
0701     uint32_t I_calc_max;
0702     uint32_t I_calc_acc;
0703     uint32_t I_calc_acc_vddci;
0704     uint32_t V_calc_noload_acc;
0705     uint32_t V_calc_load_acc;
0706     uint32_t V_calc_noload_acc_vddci;
0707     uint32_t P_meas_acc;
0708     uint32_t V_meas_noload_acc;
0709     uint32_t V_meas_load_acc;
0710     uint32_t I_meas_acc;
0711     uint32_t P_meas_acc_vddci;
0712     uint32_t V_meas_noload_acc_vddci;
0713     uint32_t V_meas_load_acc_vddci;
0714     uint32_t I_meas_acc_vddci;
0715 
0716     uint16_t Sclk_dpm_residency[8];
0717     uint16_t Uvd_dpm_residency[8];
0718     uint16_t Vce_dpm_residency[8];
0719     uint16_t Mclk_dpm_residency[4];
0720 
0721     uint32_t P_vddci_acc;
0722     uint32_t P_vddr1_acc;
0723     uint32_t P_nte1_acc;
0724     uint32_t PkgPwr_max;
0725     uint32_t PkgPwr_acc;
0726     uint32_t MclkSwitchingTime_max;
0727     uint32_t MclkSwitchingTime_acc;
0728     uint32_t FanPwm_acc;
0729     uint32_t FanRpm_acc;
0730 
0731     uint32_t AccCnt;
0732 };
0733 
0734 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
0735 
0736 #define SMU7_MAX_GFX_CU_COUNT 16
0737 
0738 struct SMU7_GfxCuPgScoreboard {
0739     uint8_t Enabled;
0740     uint8_t WaterfallUp;
0741     uint8_t WaterfallDown;
0742     uint8_t WaterfallLimit;
0743     uint8_t CurrMaxCu;
0744     uint8_t TargMaxCu;
0745     uint8_t ClampMode;
0746     uint8_t Active;
0747     uint8_t MaxSupportedCu;
0748     uint8_t MinSupportedCu;
0749     uint8_t PendingGfxCuHostInterrupt;
0750     uint8_t LastFilteredMaxCuInteger;
0751     uint16_t FilteredMaxCu;
0752     uint16_t FilteredMaxCuAlpha;
0753     uint16_t FilterResetCount;
0754     uint16_t FilterResetCountLimit;
0755     uint8_t ForceCu;
0756     uint8_t ForceCuCount;
0757     uint8_t spare[2];
0758 };
0759 
0760 typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
0761 
0762 #define SMU7_SCLK_CAC 0x561
0763 #define SMU7_MCLK_CAC 0xF9
0764 #define SMU7_VCLK_CAC 0x2DE
0765 #define SMU7_DCLK_CAC 0x2DE
0766 #define SMU7_ECLK_CAC 0x25E
0767 #define SMU7_ACLK_CAC 0x25E
0768 #define SMU7_SAMCLK_CAC 0x25E
0769 #define SMU7_DISPCLK_CAC 0x100
0770 #define SMU7_CAC_CONSTANT 0x2EE3430
0771 #define SMU7_CAC_CONSTANT_SHIFT 18
0772 
0773 #define SMU7_VDDCI_MCLK_CONST        1765
0774 #define SMU7_VDDCI_MCLK_CONST_SHIFT  16
0775 #define SMU7_VDDCI_VDDCI_CONST       50958
0776 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
0777 #define SMU7_VDDCI_CONST             11781
0778 #define SMU7_VDDCI_STROBE_PWR        1331
0779 
0780 #define SMU7_VDDR1_CONST            693
0781 #define SMU7_VDDR1_CAC_WEIGHT       20
0782 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
0783 #define SMU7_VDDR1_STROBE_PWR       512
0784 
0785 #define SMU7_AREA_COEFF_UVD 0xA78
0786 #define SMU7_AREA_COEFF_VCE 0x190A
0787 #define SMU7_AREA_COEFF_ACP 0x22D1
0788 #define SMU7_AREA_COEFF_SAMU 0x534
0789 
0790 #define SMU7_THERM_OUT_MODE_DISABLE       0x0
0791 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
0792 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
0793 
0794 // DIDT Defines
0795 #define SQ_Enable_MASK 0x1
0796 #define SQ_IR_MASK 0x2
0797 #define SQ_PCC_MASK 0x4
0798 #define SQ_EDC_MASK 0x8
0799 
0800 #define TCP_Enable_MASK 0x100
0801 #define TCP_IR_MASK 0x200
0802 #define TCP_PCC_MASK 0x400
0803 #define TCP_EDC_MASK 0x800
0804 
0805 #define TD_Enable_MASK 0x10000
0806 #define TD_IR_MASK 0x20000
0807 #define TD_PCC_MASK 0x40000
0808 #define TD_EDC_MASK 0x80000
0809 
0810 #define DB_Enable_MASK 0x1000000
0811 #define DB_IR_MASK 0x2000000
0812 #define DB_PCC_MASK 0x4000000 
0813 #define DB_EDC_MASK 0x8000000
0814 
0815 #define SQ_Enable_SHIFT 0
0816 #define SQ_IR_SHIFT 1
0817 #define SQ_PCC_SHIFT 2
0818 #define SQ_EDC_SHIFT 3
0819 
0820 #define TCP_Enable_SHIFT 8
0821 #define TCP_IR_SHIFT 9
0822 #define TCP_PCC_SHIFT 10
0823 #define TCP_EDC_SHIFT 11
0824 
0825 #define TD_Enable_SHIFT 16
0826 #define TD_IR_SHIFT 17
0827 #define TD_PCC_SHIFT 18
0828 #define TD_EDC_SHIFT 19
0829 
0830 #define DB_Enable_SHIFT 24
0831 #define DB_IR_SHIFT 25
0832 #define DB_PCC_SHIFT 26 
0833 #define DB_EDC_SHIFT 27
0834 
0835 #define BTCGB0_Vdroop_Enable_MASK  0x1
0836 #define BTCGB1_Vdroop_Enable_MASK  0x2
0837 #define AVFSGB0_Vdroop_Enable_MASK 0x4
0838 #define AVFSGB1_Vdroop_Enable_MASK 0x8
0839 
0840 #define BTCGB0_Vdroop_Enable_SHIFT  0
0841 #define BTCGB1_Vdroop_Enable_SHIFT  1
0842 #define AVFSGB0_Vdroop_Enable_SHIFT 2
0843 #define AVFSGB1_Vdroop_Enable_SHIFT 3
0844 
0845 
0846 #pragma pack(pop)
0847 
0848 
0849 #endif
0850
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