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0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _SMU73_DISCRETE_H_
0024 #define _SMU73_DISCRETE_H_
0025 
0026 #include "smu73.h"
0027 
0028 #pragma pack(push, 1)
0029 
0030 struct SMIO_Pattern
0031 {
0032   uint16_t Voltage;
0033   uint8_t  Smio;
0034   uint8_t  padding;
0035 };
0036 
0037 typedef struct SMIO_Pattern SMIO_Pattern;
0038 
0039 struct SMIO_Table
0040 {
0041   SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
0042 };
0043 
0044 typedef struct SMIO_Table SMIO_Table;
0045 
0046 struct SMU73_Discrete_GraphicsLevel {
0047     uint32_t    MinVoltage;
0048 
0049     uint32_t    SclkFrequency;
0050 
0051     uint8_t     pcieDpmLevel;
0052     uint8_t     DeepSleepDivId;
0053     uint16_t    ActivityLevel;
0054     uint32_t    CgSpllFuncCntl3;
0055     uint32_t    CgSpllFuncCntl4;
0056     uint32_t    SpllSpreadSpectrum;
0057     uint32_t    SpllSpreadSpectrum2;
0058     uint32_t    CcPwrDynRm;
0059     uint32_t    CcPwrDynRm1;
0060     uint8_t     SclkDid;
0061     uint8_t     DisplayWatermark;
0062     uint8_t     EnabledForActivity;
0063     uint8_t     EnabledForThrottle;
0064     uint8_t     UpHyst;
0065     uint8_t     DownHyst;
0066     uint8_t     VoltageDownHyst;
0067     uint8_t     PowerThrottle;
0068 };
0069 
0070 typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel;
0071 
0072 struct SMU73_Discrete_ACPILevel {
0073     uint32_t    Flags;
0074     uint32_t MinVoltage;
0075     uint32_t    SclkFrequency;
0076     uint8_t     SclkDid;
0077     uint8_t     DisplayWatermark;
0078     uint8_t     DeepSleepDivId;
0079     uint8_t     padding;
0080     uint32_t    CgSpllFuncCntl;
0081     uint32_t    CgSpllFuncCntl2;
0082     uint32_t    CgSpllFuncCntl3;
0083     uint32_t    CgSpllFuncCntl4;
0084     uint32_t    SpllSpreadSpectrum;
0085     uint32_t    SpllSpreadSpectrum2;
0086     uint32_t    CcPwrDynRm;
0087     uint32_t    CcPwrDynRm1;
0088 };
0089 
0090 typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel;
0091 
0092 struct SMU73_Discrete_Ulv {
0093     uint32_t    CcPwrDynRm;
0094     uint32_t    CcPwrDynRm1;
0095     uint16_t    VddcOffset;
0096     uint8_t     VddcOffsetVid;
0097     uint8_t     VddcPhase;
0098     uint32_t    Reserved;
0099 };
0100 
0101 typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv;
0102 
0103 struct SMU73_Discrete_MemoryLevel
0104 {
0105     uint32_t MinVoltage;
0106     uint32_t    MinMvdd;
0107 
0108     uint32_t    MclkFrequency;
0109 
0110     uint8_t     StutterEnable;
0111     uint8_t     FreqRange;
0112     uint8_t     EnabledForThrottle;
0113     uint8_t     EnabledForActivity;
0114 
0115     uint8_t     UpHyst;
0116     uint8_t     DownHyst;
0117     uint8_t     VoltageDownHyst;
0118     uint8_t     padding;
0119 
0120     uint16_t    ActivityLevel;
0121     uint8_t     DisplayWatermark;
0122     uint8_t     MclkDivider;
0123 };
0124 
0125 typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel;
0126 
0127 struct SMU73_Discrete_LinkLevel
0128 {
0129     uint8_t     PcieGenSpeed;           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
0130     uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 
0131     uint8_t     EnabledForActivity;
0132     uint8_t     SPC;
0133     uint32_t    DownThreshold;
0134     uint32_t    UpThreshold;
0135     uint32_t    Reserved;
0136 };
0137 
0138 typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel;
0139 
0140 
0141 // MC ARB DRAM Timing registers.
0142 struct SMU73_Discrete_MCArbDramTimingTableEntry
0143 {
0144     uint32_t McArbDramTiming;
0145     uint32_t McArbDramTiming2;
0146     uint8_t  McArbBurstTime;
0147     uint8_t  TRRDS;
0148     uint8_t  TRRDL;
0149     uint8_t  padding;
0150 };
0151 
0152 typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry;
0153 
0154 struct SMU73_Discrete_MCArbDramTimingTable
0155 {
0156     SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
0157 };
0158 
0159 typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable;
0160 
0161 // UVD VCLK/DCLK state (level) definition.
0162 struct SMU73_Discrete_UvdLevel
0163 {
0164     uint32_t VclkFrequency;
0165     uint32_t DclkFrequency;
0166     uint32_t MinVoltage;
0167     uint8_t  VclkDivider;
0168     uint8_t  DclkDivider;
0169     uint8_t  padding[2];
0170 };
0171 
0172 typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel;
0173 
0174 // Clocks for other external blocks (VCE, ACP, SAMU).
0175 struct SMU73_Discrete_ExtClkLevel
0176 {
0177     uint32_t Frequency;
0178     uint32_t MinVoltage;
0179     uint8_t  Divider;
0180     uint8_t  padding[3];
0181 };
0182 
0183 typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel;
0184 
0185 struct SMU73_Discrete_StateInfo
0186 {
0187     uint32_t SclkFrequency;
0188     uint32_t MclkFrequency;
0189     uint32_t VclkFrequency;
0190     uint32_t DclkFrequency;
0191     uint32_t SamclkFrequency;
0192     uint32_t AclkFrequency;
0193     uint32_t EclkFrequency;
0194     uint16_t MvddVoltage;
0195     uint16_t padding16;
0196     uint8_t  DisplayWatermark;
0197     uint8_t  McArbIndex;
0198     uint8_t  McRegIndex;
0199     uint8_t  SeqIndex;
0200     uint8_t  SclkDid;
0201     int8_t   SclkIndex;
0202     int8_t   MclkIndex;
0203     uint8_t  PCIeGen;
0204 
0205 };
0206 
0207 typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo;
0208 
0209 struct SMU73_Discrete_DpmTable
0210 {
0211     // Multi-DPM controller settings
0212     SMU73_PIDController                  GraphicsPIDController;
0213     SMU73_PIDController                  MemoryPIDController;
0214     SMU73_PIDController                  LinkPIDController;
0215 
0216     uint32_t                            SystemFlags;
0217 
0218     // SMIO masks for voltage and phase controls
0219     uint32_t                            VRConfig;
0220     uint32_t                            SmioMask1;
0221     uint32_t                            SmioMask2;
0222     SMIO_Table                          SmioTable1;
0223     SMIO_Table                          SmioTable2;
0224 
0225     uint32_t                            MvddLevelCount;
0226 
0227 
0228     uint8_t                             BapmVddcVidHiSidd        [SMU73_MAX_LEVELS_VDDC];
0229     uint8_t                             BapmVddcVidLoSidd        [SMU73_MAX_LEVELS_VDDC];
0230     uint8_t                             BapmVddcVidHiSidd2       [SMU73_MAX_LEVELS_VDDC];
0231 
0232     uint8_t                             GraphicsDpmLevelCount;
0233     uint8_t                             MemoryDpmLevelCount;
0234     uint8_t                             LinkLevelCount;
0235     uint8_t                             MasterDeepSleepControl;
0236 
0237     uint8_t                             UvdLevelCount;
0238     uint8_t                             VceLevelCount;
0239     uint8_t                             AcpLevelCount;
0240     uint8_t                             SamuLevelCount;
0241 
0242     uint8_t                             ThermOutGpio;
0243     uint8_t                             ThermOutPolarity;
0244     uint8_t                             ThermOutMode;
0245     uint8_t                             BootPhases;
0246     uint32_t                            Reserved[4];
0247 
0248     // State table entries for each DPM state
0249     SMU73_Discrete_GraphicsLevel        GraphicsLevel           [SMU73_MAX_LEVELS_GRAPHICS];
0250     SMU73_Discrete_MemoryLevel          MemoryACPILevel;
0251     SMU73_Discrete_MemoryLevel          MemoryLevel             [SMU73_MAX_LEVELS_MEMORY];
0252     SMU73_Discrete_LinkLevel            LinkLevel               [SMU73_MAX_LEVELS_LINK];
0253     SMU73_Discrete_ACPILevel            ACPILevel;
0254     SMU73_Discrete_UvdLevel             UvdLevel                [SMU73_MAX_LEVELS_UVD];
0255     SMU73_Discrete_ExtClkLevel          VceLevel                [SMU73_MAX_LEVELS_VCE];
0256     SMU73_Discrete_ExtClkLevel          AcpLevel                [SMU73_MAX_LEVELS_ACP];
0257     SMU73_Discrete_ExtClkLevel          SamuLevel               [SMU73_MAX_LEVELS_SAMU];
0258     SMU73_Discrete_Ulv                  Ulv;
0259 
0260     uint32_t                            SclkStepSize;
0261     uint32_t                            Smio                    [SMU73_MAX_ENTRIES_SMIO];
0262 
0263     uint8_t                             UvdBootLevel;
0264     uint8_t                             VceBootLevel;
0265     uint8_t                             AcpBootLevel;
0266     uint8_t                             SamuBootLevel;
0267 
0268     uint8_t                             GraphicsBootLevel;
0269     uint8_t                             GraphicsVoltageChangeEnable;
0270     uint8_t                             GraphicsThermThrottleEnable;
0271     uint8_t                             GraphicsInterval;
0272 
0273     uint8_t                             VoltageInterval;
0274     uint8_t                             ThermalInterval;
0275     uint16_t                            TemperatureLimitHigh;
0276 
0277     uint16_t                            TemperatureLimitLow;
0278     uint8_t                             MemoryBootLevel;
0279     uint8_t                             MemoryVoltageChangeEnable;
0280 
0281     uint16_t                            BootMVdd;
0282     uint8_t                             MemoryInterval;
0283     uint8_t                             MemoryThermThrottleEnable;
0284 
0285     uint16_t                            VoltageResponseTime;
0286     uint16_t                            PhaseResponseTime;
0287 
0288     uint8_t                             PCIeBootLinkLevel;
0289     uint8_t                             PCIeGenInterval;
0290     uint8_t                             DTEInterval;
0291     uint8_t                             DTEMode;
0292 
0293     uint8_t                             SVI2Enable;
0294     uint8_t                             VRHotGpio;
0295     uint8_t                             AcDcGpio;
0296     uint8_t                             ThermGpio;
0297 
0298     uint16_t                            PPM_PkgPwrLimit;
0299     uint16_t                            PPM_TemperatureLimit;
0300 
0301     uint16_t                            DefaultTdp;
0302     uint16_t                            TargetTdp;
0303 
0304     uint16_t                            FpsHighThreshold;
0305     uint16_t                            FpsLowThreshold;
0306 
0307     uint16_t                            TemperatureLimitEdge;
0308     uint16_t                            TemperatureLimitHotspot;
0309     uint16_t                            TemperatureLimitLiquid1;
0310     uint16_t                            TemperatureLimitLiquid2;
0311     uint16_t                            TemperatureLimitVrVddc;
0312     uint16_t                            TemperatureLimitVrMvdd;
0313     uint16_t                            TemperatureLimitPlx;
0314 
0315     uint16_t                            FanGainEdge;
0316     uint16_t                            FanGainHotspot;
0317     uint16_t                            FanGainLiquid;
0318     uint16_t                            FanGainVrVddc;
0319     uint16_t                            FanGainVrMvdd;
0320     uint16_t                            FanGainPlx;
0321     uint16_t                            FanGainHbm;
0322 
0323     uint8_t                             Liquid1_I2C_address;
0324     uint8_t                             Liquid2_I2C_address;
0325     uint8_t                             Vr_I2C_address;
0326     uint8_t                             Plx_I2C_address;
0327 
0328     uint8_t                             GeminiMode;
0329     uint8_t                             spare17[3];
0330     uint32_t                            GeminiApertureHigh;
0331     uint32_t                            GeminiApertureLow;
0332 
0333     uint8_t                             Liquid_I2C_LineSCL;
0334     uint8_t                             Liquid_I2C_LineSDA;
0335     uint8_t                             Vr_I2C_LineSCL;
0336     uint8_t                             Vr_I2C_LineSDA;
0337     uint8_t                             Plx_I2C_LineSCL;
0338     uint8_t                             Plx_I2C_LineSDA;
0339 
0340     uint8_t                             spare1253[2];
0341     uint32_t                            spare123[2];
0342 
0343     uint8_t                             DTEAmbientTempBase;
0344     uint8_t                             DTETjOffset;
0345     uint8_t                             GpuTjMax;
0346     uint8_t                             GpuTjHyst;
0347 
0348     uint16_t                            BootVddc;
0349     uint16_t                            BootVddci;
0350 
0351     uint32_t                            BAPM_TEMP_GRADIENT;
0352 
0353     uint32_t                            LowSclkInterruptThreshold;
0354     uint32_t                            VddGfxReChkWait;
0355 
0356     uint8_t                             ClockStretcherAmount;
0357     uint8_t                             Sclk_CKS_masterEn0_7;
0358     uint8_t                             Sclk_CKS_masterEn8_15;
0359     uint8_t                             DPMFreezeAndForced;
0360 
0361     uint8_t                             Sclk_voltageOffset[8];
0362 
0363     SMU_ClockStretcherDataTable         ClockStretcherDataTable;
0364     SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
0365 };
0366 
0367 typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable;
0368 
0369 
0370 // --------------------------------------------------- Fan Table -----------------------------------------------------------
0371 struct SMU73_Discrete_FanTable
0372 {
0373     uint16_t FdoMode;
0374     int16_t  TempMin;
0375     int16_t  TempMed;
0376     int16_t  TempMax;
0377     int16_t  Slope1;
0378     int16_t  Slope2;
0379     int16_t  FdoMin;
0380     int16_t  HystUp;
0381     int16_t  HystDown;
0382     int16_t  HystSlope;
0383     int16_t  TempRespLim;
0384     int16_t  TempCurr;
0385     int16_t  SlopeCurr;
0386     int16_t  PwmCurr;
0387     uint32_t RefreshPeriod;
0388     int16_t  FdoMax;
0389     uint8_t  TempSrc;
0390     int8_t   Padding;
0391 };
0392 
0393 typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable;
0394 
0395 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
0396 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
0397 
0398 
0399 
0400 struct SMU7_MclkDpmScoreboard
0401 {
0402 
0403     uint32_t PercentageBusy;
0404 
0405     int32_t  PIDError;
0406     int32_t  PIDIntegral;
0407     int32_t  PIDOutput;
0408 
0409     uint32_t SigmaDeltaAccum;
0410     uint32_t SigmaDeltaOutput;
0411     uint32_t SigmaDeltaLevel;
0412 
0413     uint32_t UtilizationSetpoint;
0414 
0415     uint8_t  TdpClampMode;
0416     uint8_t  TdcClampMode;
0417     uint8_t  ThermClampMode;
0418     uint8_t  VoltageBusy;
0419 
0420     int8_t   CurrLevel;
0421     int8_t   TargLevel;
0422     uint8_t  LevelChangeInProgress;
0423     uint8_t  UpHyst;
0424 
0425     uint8_t  DownHyst;
0426     uint8_t  VoltageDownHyst;
0427     uint8_t  DpmEnable;
0428     uint8_t  DpmRunning;
0429 
0430     uint8_t  DpmForce;
0431     uint8_t  DpmForceLevel;
0432     uint8_t  DisplayWatermark;
0433     uint8_t  McArbIndex;
0434 
0435     uint32_t MinimumPerfMclk;
0436 
0437     uint8_t  AcpiReq;
0438     uint8_t  AcpiAck;
0439     uint8_t  MclkSwitchInProgress;
0440     uint8_t  MclkSwitchCritical;
0441 
0442     uint8_t  IgnoreVBlank;
0443     uint8_t  TargetMclkIndex;
0444     uint8_t  TargetMvddIndex;
0445     uint8_t  MclkSwitchResult;
0446 
0447     uint16_t VbiFailureCount;
0448     uint8_t  VbiWaitCounter;
0449     uint8_t  EnabledLevelsChange;
0450 
0451     uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY];
0452     uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY];
0453 
0454     void     (*TargetStateCalculator)(uint8_t);
0455     void     (*SavedTargetStateCalculator)(uint8_t);
0456 
0457     uint16_t AutoDpmInterval;
0458     uint16_t AutoDpmRange;
0459 
0460     uint16_t VbiTimeoutCount;
0461     uint16_t MclkSwitchingTime;
0462 
0463     uint8_t  fastSwitch;
0464     uint8_t  Save_PIC_VDDGFX_EXIT;
0465     uint8_t  Save_PIC_VDDGFX_ENTER;
0466     uint8_t  padding;
0467 
0468 };
0469 
0470 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
0471 
0472 struct SMU7_UlvScoreboard
0473 {
0474     uint8_t     EnterUlv;
0475     uint8_t     ExitUlv;
0476     uint8_t     UlvActive;
0477     uint8_t     WaitingForUlv;
0478     uint8_t     UlvEnable;
0479     uint8_t     UlvRunning;
0480     uint8_t     UlvMasterEnable;
0481     uint8_t     padding;
0482     uint32_t    UlvAbortedCount;
0483     uint32_t    UlvTimeStamp;
0484 };
0485 
0486 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
0487 
0488 struct VddgfxSavedRegisters
0489 {
0490   uint32_t GPU_DBG[3];
0491   uint32_t MEC_BaseAddress_Hi;
0492   uint32_t MEC_BaseAddress_Lo;
0493   uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
0494   uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
0495   uint32_t CP_INT_CNTL;
0496 };
0497 
0498 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
0499 
0500 struct SMU7_VddGfxScoreboard
0501 {
0502     uint8_t     VddGfxEnable;
0503     uint8_t     VddGfxActive;
0504     uint8_t     VPUResetOccured;
0505     uint8_t     padding;
0506 
0507     uint32_t    VddGfxEnteredCount;
0508     uint32_t    VddGfxAbortedCount;
0509 
0510     uint32_t    VddGfxVid;
0511 
0512     VddgfxSavedRegisters SavedRegisters;
0513 };
0514 
0515 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
0516 
0517 struct SMU7_TdcLimitScoreboard {
0518   uint8_t  Enable;
0519   uint8_t  Running;
0520   uint16_t Alpha;
0521   uint32_t FilteredIddc;
0522   uint32_t IddcLimit;
0523   uint32_t IddcHyst;
0524   SMU7_HystController_Data HystControllerData;
0525 };
0526 
0527 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
0528 
0529 struct SMU7_PkgPwrLimitScoreboard {
0530   uint8_t  Enable;
0531   uint8_t  Running;
0532   uint16_t Alpha;
0533   uint32_t FilteredPkgPwr;
0534   uint32_t Limit;
0535   uint32_t Hyst;
0536   uint32_t LimitFromDriver;
0537   SMU7_HystController_Data HystControllerData;
0538 };
0539 
0540 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
0541 
0542 struct SMU7_BapmScoreboard {
0543   uint32_t source_powers[SMU73_DTE_SOURCES];
0544   uint32_t source_powers_last[SMU73_DTE_SOURCES];
0545   int32_t entity_temperatures[SMU73_NUM_GPU_TES];
0546   int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES];
0547   int32_t Limit;
0548   int32_t Hyst;
0549   int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2];
0550   int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS];
0551   uint16_t ConfigTDPPowerScalar;
0552   uint16_t FanSpeedPowerScalar;
0553   uint16_t OverDrivePowerScalar;
0554   uint16_t OverDriveLimitScalar;
0555   uint16_t FinalPowerScalar;
0556   uint8_t VariantID;
0557   uint8_t spare997;
0558 
0559   SMU7_HystController_Data HystControllerData;
0560 
0561   int32_t temperature_gradient_slope;
0562   int32_t temperature_gradient;
0563   uint32_t measured_temperature;
0564 };
0565 
0566 
0567 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
0568 
0569 struct SMU7_AcpiScoreboard {
0570   uint32_t SavedInterruptMask[2];
0571   uint8_t LastACPIRequest;
0572   uint8_t CgBifResp;
0573   uint8_t RequestType;
0574   uint8_t Padding;
0575   SMU73_Discrete_ACPILevel D0Level;
0576 };
0577 
0578 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
0579 
0580 struct SMU_QuadraticCoeffs {
0581   int32_t m1;
0582   uint32_t b;
0583 
0584   int16_t m2;
0585   uint8_t m1_shift;
0586   uint8_t m2_shift;
0587 };
0588 
0589 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs;
0590 
0591 struct SMU73_Discrete_PmFuses {
0592   /* dw0-dw1 */
0593   uint8_t BapmVddCVidHiSidd[8];
0594 
0595   /* dw2-dw3 */
0596   uint8_t BapmVddCVidLoSidd[8];
0597 
0598   /* dw4-dw5 */
0599   uint8_t VddCVid[8];
0600 
0601   /* dw1*/
0602   uint8_t SviLoadLineEn;
0603   uint8_t SviLoadLineVddC;
0604   uint8_t SviLoadLineTrimVddC;
0605   uint8_t SviLoadLineOffsetVddC;
0606 
0607   /* dw2 */
0608   uint16_t TDC_VDDC_PkgLimit;
0609   uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
0610   uint8_t TDC_MAWt;
0611 
0612   /* dw3 */
0613   uint8_t TdcWaterfallCtl;
0614   uint8_t LPMLTemperatureMin;
0615   uint8_t LPMLTemperatureMax;
0616   uint8_t Reserved;
0617 
0618   /* dw4-dw7 */
0619   uint8_t LPMLTemperatureScaler[16];
0620 
0621   /* dw8-dw9 */
0622   int16_t FuzzyFan_ErrorSetDelta;
0623   int16_t FuzzyFan_ErrorRateSetDelta;
0624   int16_t FuzzyFan_PwmSetDelta;
0625   uint16_t Reserved6;
0626 
0627   /* dw10-dw14 */
0628   uint8_t GnbLPML[16];
0629 
0630   /* dw15 */
0631   uint8_t GnbLPMLMaxVid;
0632   uint8_t GnbLPMLMinVid;
0633   uint8_t Reserved1[2];
0634 
0635   /* dw16 */
0636   uint16_t BapmVddCBaseLeakageHiSidd;
0637   uint16_t BapmVddCBaseLeakageLoSidd;
0638 
0639   /* AVFS */
0640   uint16_t  VFT_Temp[3];
0641   uint16_t  padding;
0642 
0643   SMU_QuadraticCoeffs VFT_ATE[3];
0644 
0645   SMU_QuadraticCoeffs AVFS_GB;
0646   SMU_QuadraticCoeffs ATE_ACBTC_GB;
0647 
0648   SMU_QuadraticCoeffs P2V;
0649 
0650   uint32_t PsmCharzFreq;
0651 
0652   uint16_t InversionVoltage;
0653   uint16_t PsmCharzTemp;
0654 
0655   uint32_t EnabledAvfsModules;
0656 };
0657 
0658 typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses;
0659 
0660 struct SMU7_Discrete_Log_Header_Table {
0661   uint32_t    version;
0662   uint32_t    asic_id;
0663   uint16_t    flags;
0664   uint16_t    entry_size;
0665   uint32_t    total_size;
0666   uint32_t    num_of_entries;
0667   uint8_t     type;
0668   uint8_t     mode;
0669   uint8_t     filler_0[2];
0670   uint32_t    filler_1[2];
0671 };
0672 
0673 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
0674 
0675 struct SMU7_Discrete_Log_Cntl {
0676     uint8_t             Enabled;
0677     uint8_t             Type;
0678     uint8_t             padding[2];
0679     uint32_t            BufferSize;
0680     uint32_t            SamplesLogged;
0681     uint32_t            SampleSize;
0682     uint32_t            AddrL;
0683     uint32_t            AddrH;
0684 };
0685 
0686 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
0687 
0688 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
0689 
0690 struct SMU7_Discrete_Cac_Collection_Table {
0691   uint32_t temperature;
0692   uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
0693 };
0694 
0695 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
0696 
0697 struct SMU7_Discrete_Cac_Verification_Table {
0698   uint32_t VddcTotalPower;
0699   uint32_t VddcLeakagePower;
0700   uint32_t VddcConstantPower;
0701   uint32_t VddcGfxDynamicPower;
0702   uint32_t VddcUvdDynamicPower;
0703   uint32_t VddcVceDynamicPower;
0704   uint32_t VddcAcpDynamicPower;
0705   uint32_t VddcPcieDynamicPower;
0706   uint32_t VddcDceDynamicPower;
0707   uint32_t VddcCurrent;
0708   uint32_t VddcVoltage;
0709   uint32_t VddciTotalPower;
0710   uint32_t VddciLeakagePower;
0711   uint32_t VddciConstantPower;
0712   uint32_t VddciDynamicPower;
0713   uint32_t Vddr1TotalPower;
0714   uint32_t Vddr1LeakagePower;
0715   uint32_t Vddr1ConstantPower;
0716   uint32_t Vddr1DynamicPower;
0717   uint32_t spare[4];
0718   uint32_t temperature;
0719 };
0720 
0721 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
0722 
0723 struct SMU7_Discrete_Pm_Status_Table {
0724   //Thermal entities
0725   int32_t  T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT];
0726   int32_t  T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT];
0727   int32_t  T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT];
0728   uint32_t T_hbm_acc;
0729 
0730   //Voltage domains
0731   uint32_t I_calc_max;
0732   uint32_t I_calc_acc;
0733   uint32_t P_meas_acc;
0734   uint32_t V_meas_load_acc;
0735   uint32_t I_meas_acc;
0736   uint32_t P_meas_acc_vddci;
0737   uint32_t V_meas_load_acc_vddci;
0738   uint32_t I_meas_acc_vddci;
0739 
0740   //Frequency
0741   uint16_t Sclk_dpm_residency[8];
0742   uint16_t Uvd_dpm_residency[8];
0743   uint16_t Vce_dpm_residency[8];
0744 
0745   //Chip
0746   uint32_t P_roc_acc;
0747   uint32_t PkgPwr_max;
0748   uint32_t PkgPwr_acc;
0749   uint32_t MclkSwitchingTime_max;
0750   uint32_t MclkSwitchingTime_acc;
0751   uint32_t FanPwm_acc;
0752   uint32_t FanRpm_acc;
0753   uint32_t Gfx_busy_acc;
0754   uint32_t Mc_busy_acc;
0755   uint32_t Fps_acc;
0756 
0757   uint32_t AccCnt;
0758 };
0759 
0760 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
0761 
0762 //FIXME THESE NEED TO BE UPDATED
0763 #define SMU7_SCLK_CAC 0x561
0764 #define SMU7_MCLK_CAC 0xF9
0765 #define SMU7_VCLK_CAC 0x2DE
0766 #define SMU7_DCLK_CAC 0x2DE
0767 #define SMU7_ECLK_CAC 0x25E
0768 #define SMU7_ACLK_CAC 0x25E
0769 #define SMU7_SAMCLK_CAC 0x25E
0770 #define SMU7_DISPCLK_CAC 0x100
0771 #define SMU7_CAC_CONSTANT 0x2EE3430
0772 #define SMU7_CAC_CONSTANT_SHIFT 18
0773 
0774 #define SMU7_VDDCI_MCLK_CONST        1765
0775 #define SMU7_VDDCI_MCLK_CONST_SHIFT  16
0776 #define SMU7_VDDCI_VDDCI_CONST       50958
0777 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
0778 #define SMU7_VDDCI_CONST             11781
0779 #define SMU7_VDDCI_STROBE_PWR        1331
0780 
0781 #define SMU7_VDDR1_CONST            693
0782 #define SMU7_VDDR1_CAC_WEIGHT       20
0783 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
0784 #define SMU7_VDDR1_STROBE_PWR       512
0785 
0786 #define SMU7_AREA_COEFF_UVD 0xA78
0787 #define SMU7_AREA_COEFF_VCE 0x190A
0788 #define SMU7_AREA_COEFF_ACP 0x22D1
0789 #define SMU7_AREA_COEFF_SAMU 0x534
0790 
0791 //ThermOutMode values
0792 #define SMU7_THERM_OUT_MODE_DISABLE       0x0
0793 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
0794 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
0795 
0796 #pragma pack(pop)
0797 
0798 #endif
0799
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