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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef SMU72_DISCRETE_H
0025 #define SMU72_DISCRETE_H
0026 
0027 #include "smu72.h"
0028 
0029 #if !defined(SMC_MICROCODE)
0030 #pragma pack(push, 1)
0031 #endif
0032 
0033 struct SMIO_Pattern {
0034     uint16_t Voltage;
0035     uint8_t  Smio;
0036     uint8_t  padding;
0037 };
0038 
0039 typedef struct SMIO_Pattern SMIO_Pattern;
0040 
0041 struct SMIO_Table {
0042     SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
0043 };
0044 
0045 typedef struct SMIO_Table SMIO_Table;
0046 
0047 struct SMU72_Discrete_GraphicsLevel {
0048     SMU_VoltageLevel MinVoltage;
0049 
0050     uint32_t    SclkFrequency;
0051 
0052     uint8_t     pcieDpmLevel;
0053     uint8_t     DeepSleepDivId;
0054     uint16_t    ActivityLevel;
0055 
0056     uint32_t    CgSpllFuncCntl3;
0057     uint32_t    CgSpllFuncCntl4;
0058     uint32_t    SpllSpreadSpectrum;
0059     uint32_t    SpllSpreadSpectrum2;
0060     uint32_t    CcPwrDynRm;
0061     uint32_t    CcPwrDynRm1;
0062     uint8_t     SclkDid;
0063     uint8_t     DisplayWatermark;
0064     uint8_t     EnabledForActivity;
0065     uint8_t     EnabledForThrottle;
0066     uint8_t     UpHyst;
0067     uint8_t     DownHyst;
0068     uint8_t     VoltageDownHyst;
0069     uint8_t     PowerThrottle;
0070 };
0071 
0072 typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
0073 
0074 struct SMU72_Discrete_ACPILevel {
0075     uint32_t    Flags;
0076     SMU_VoltageLevel MinVoltage;
0077     uint32_t    SclkFrequency;
0078     uint8_t     SclkDid;
0079     uint8_t     DisplayWatermark;
0080     uint8_t     DeepSleepDivId;
0081     uint8_t     padding;
0082     uint32_t    CgSpllFuncCntl;
0083     uint32_t    CgSpllFuncCntl2;
0084     uint32_t    CgSpllFuncCntl3;
0085     uint32_t    CgSpllFuncCntl4;
0086     uint32_t    SpllSpreadSpectrum;
0087     uint32_t    SpllSpreadSpectrum2;
0088     uint32_t    CcPwrDynRm;
0089     uint32_t    CcPwrDynRm1;
0090 };
0091 
0092 typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
0093 
0094 struct SMU72_Discrete_Ulv {
0095     uint32_t    CcPwrDynRm;
0096     uint32_t    CcPwrDynRm1;
0097     uint16_t    VddcOffset;
0098     uint8_t     VddcOffsetVid;
0099     uint8_t     VddcPhase;
0100     uint32_t    Reserved;
0101 };
0102 
0103 typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
0104 
0105 struct SMU72_Discrete_MemoryLevel {
0106     SMU_VoltageLevel MinVoltage;
0107     uint32_t    MinMvdd;
0108 
0109     uint32_t    MclkFrequency;
0110 
0111     uint8_t     EdcReadEnable;
0112     uint8_t     EdcWriteEnable;
0113     uint8_t     RttEnable;
0114     uint8_t     StutterEnable;
0115 
0116     uint8_t     StrobeEnable;
0117     uint8_t     StrobeRatio;
0118     uint8_t     EnabledForThrottle;
0119     uint8_t     EnabledForActivity;
0120 
0121     uint8_t     UpHyst;
0122     uint8_t     DownHyst;
0123     uint8_t     VoltageDownHyst;
0124     uint8_t     padding;
0125 
0126     uint16_t    ActivityLevel;
0127     uint8_t     DisplayWatermark;
0128     uint8_t     padding1;
0129 
0130     uint32_t    MpllFuncCntl;
0131     uint32_t    MpllFuncCntl_1;
0132     uint32_t    MpllFuncCntl_2;
0133     uint32_t    MpllAdFuncCntl;
0134     uint32_t    MpllDqFuncCntl;
0135     uint32_t    MclkPwrmgtCntl;
0136     uint32_t    DllCntl;
0137     uint32_t    MpllSs1;
0138     uint32_t    MpllSs2;
0139 };
0140 
0141 typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
0142 
0143 struct SMU72_Discrete_LinkLevel {
0144     uint8_t     PcieGenSpeed;           /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
0145     uint8_t     PcieLaneCount;          /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
0146     uint8_t     EnabledForActivity;
0147     uint8_t     SPC;
0148     uint32_t    DownThreshold;
0149     uint32_t    UpThreshold;
0150     uint32_t    Reserved;
0151 };
0152 
0153 typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
0154 
0155 /* MC ARB DRAM Timing registers. */
0156 struct SMU72_Discrete_MCArbDramTimingTableEntry {
0157     uint32_t McArbDramTiming;
0158     uint32_t McArbDramTiming2;
0159     uint8_t  McArbBurstTime;
0160     uint8_t  padding[3];
0161 };
0162 
0163 typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
0164 
0165 struct SMU72_Discrete_MCArbDramTimingTable {
0166     SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
0167 };
0168 
0169 typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
0170 
0171 /* UVD VCLK/DCLK state (level) definition. */
0172 struct SMU72_Discrete_UvdLevel {
0173     uint32_t VclkFrequency;
0174     uint32_t DclkFrequency;
0175     SMU_VoltageLevel MinVoltage;
0176     uint8_t  VclkDivider;
0177     uint8_t  DclkDivider;
0178     uint8_t  padding[2];
0179 };
0180 
0181 typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
0182 
0183 /* Clocks for other external blocks (VCE, ACP, SAMU). */
0184 struct SMU72_Discrete_ExtClkLevel {
0185     uint32_t Frequency;
0186     SMU_VoltageLevel MinVoltage;
0187     uint8_t  Divider;
0188     uint8_t  padding[3];
0189 };
0190 
0191 typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
0192 
0193 struct SMU72_Discrete_StateInfo {
0194     uint32_t SclkFrequency;
0195     uint32_t MclkFrequency;
0196     uint32_t VclkFrequency;
0197     uint32_t DclkFrequency;
0198     uint32_t SamclkFrequency;
0199     uint32_t AclkFrequency;
0200     uint32_t EclkFrequency;
0201     uint16_t MvddVoltage;
0202     uint16_t padding16;
0203     uint8_t  DisplayWatermark;
0204     uint8_t  McArbIndex;
0205     uint8_t  McRegIndex;
0206     uint8_t  SeqIndex;
0207     uint8_t  SclkDid;
0208     int8_t   SclkIndex;
0209     int8_t   MclkIndex;
0210     uint8_t  PCIeGen;
0211 
0212 };
0213 
0214 typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
0215 
0216 struct SMU72_Discrete_DpmTable {
0217     /* Multi-DPM controller settings */
0218     SMU72_PIDController                  GraphicsPIDController;
0219     SMU72_PIDController                  MemoryPIDController;
0220     SMU72_PIDController                  LinkPIDController;
0221 
0222     uint32_t                            SystemFlags;
0223 
0224     /* SMIO masks for voltage and phase controls */
0225     uint32_t                            VRConfig;
0226     uint32_t                            SmioMask1;
0227     uint32_t                            SmioMask2;
0228     SMIO_Table                          SmioTable1;
0229     SMIO_Table                          SmioTable2;
0230 
0231     uint32_t                            VddcLevelCount;
0232     uint32_t                            VddciLevelCount;
0233     uint32_t                            VddGfxLevelCount;
0234     uint32_t                            MvddLevelCount;
0235 
0236     uint16_t                            VddcTable[SMU72_MAX_LEVELS_VDDC];
0237     uint16_t                            VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
0238     uint16_t                            VddciTable[SMU72_MAX_LEVELS_VDDCI];
0239 
0240     uint8_t                             BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
0241     uint8_t                             BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
0242     uint8_t                             BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
0243 
0244     uint8_t                             BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
0245     uint8_t                             BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
0246     uint8_t                             BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
0247 
0248     uint8_t                             GraphicsDpmLevelCount;
0249     uint8_t                             MemoryDpmLevelCount;
0250     uint8_t                             LinkLevelCount;
0251     uint8_t                             MasterDeepSleepControl;
0252 
0253     uint8_t                             UvdLevelCount;
0254     uint8_t                             VceLevelCount;
0255     uint8_t                             AcpLevelCount;
0256     uint8_t                             SamuLevelCount;
0257 
0258     uint8_t                             ThermOutGpio;
0259     uint8_t                             ThermOutPolarity;
0260     uint8_t                             ThermOutMode;
0261     uint8_t                             DPMFreezeAndForced;
0262     uint32_t                            Reserved[4];
0263 
0264     /* State table entries for each DPM state */
0265     SMU72_Discrete_GraphicsLevel        GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
0266     SMU72_Discrete_MemoryLevel          MemoryACPILevel;
0267     SMU72_Discrete_MemoryLevel          MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
0268     SMU72_Discrete_LinkLevel            LinkLevel[SMU72_MAX_LEVELS_LINK];
0269     SMU72_Discrete_ACPILevel            ACPILevel;
0270     SMU72_Discrete_UvdLevel             UvdLevel[SMU72_MAX_LEVELS_UVD];
0271     SMU72_Discrete_ExtClkLevel          VceLevel[SMU72_MAX_LEVELS_VCE];
0272     SMU72_Discrete_ExtClkLevel          AcpLevel[SMU72_MAX_LEVELS_ACP];
0273     SMU72_Discrete_ExtClkLevel          SamuLevel[SMU72_MAX_LEVELS_SAMU];
0274     SMU72_Discrete_Ulv                  Ulv;
0275 
0276     uint32_t                            SclkStepSize;
0277     uint32_t                            Smio[SMU72_MAX_ENTRIES_SMIO];
0278 
0279     uint8_t                             UvdBootLevel;
0280     uint8_t                             VceBootLevel;
0281     uint8_t                             AcpBootLevel;
0282     uint8_t                             SamuBootLevel;
0283 
0284     uint8_t                             GraphicsBootLevel;
0285     uint8_t                             GraphicsVoltageChangeEnable;
0286     uint8_t                             GraphicsThermThrottleEnable;
0287     uint8_t                             GraphicsInterval;
0288 
0289     uint8_t                             VoltageInterval;
0290     uint8_t                             ThermalInterval;
0291     uint16_t                            TemperatureLimitHigh;
0292 
0293     uint16_t                            TemperatureLimitLow;
0294     uint8_t                             MemoryBootLevel;
0295     uint8_t                             MemoryVoltageChangeEnable;
0296 
0297     uint16_t                            BootMVdd;
0298     uint8_t                             MemoryInterval;
0299     uint8_t                             MemoryThermThrottleEnable;
0300 
0301     uint16_t                            VoltageResponseTime;
0302     uint16_t                            PhaseResponseTime;
0303 
0304     uint8_t                             PCIeBootLinkLevel;
0305     uint8_t                             PCIeGenInterval;
0306     uint8_t                             DTEInterval;
0307     uint8_t                             DTEMode;
0308 
0309     uint8_t                             SVI2Enable;
0310     uint8_t                             VRHotGpio;
0311     uint8_t                             AcDcGpio;
0312     uint8_t                             ThermGpio;
0313 
0314     uint16_t                            PPM_PkgPwrLimit;
0315     uint16_t                            PPM_TemperatureLimit;
0316 
0317     uint16_t                            DefaultTdp;
0318     uint16_t                            TargetTdp;
0319 
0320     uint16_t                            FpsHighThreshold;
0321     uint16_t                            FpsLowThreshold;
0322 
0323     uint16_t                            BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
0324     uint16_t                            BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
0325 
0326     uint8_t                             DTEAmbientTempBase;
0327     uint8_t                             DTETjOffset;
0328     uint8_t                             GpuTjMax;
0329     uint8_t                             GpuTjHyst;
0330 
0331     SMU_VoltageLevel                    BootVoltage;
0332 
0333     uint32_t                            BAPM_TEMP_GRADIENT;
0334 
0335     uint32_t                            LowSclkInterruptThreshold;
0336     uint32_t                            VddGfxReChkWait;
0337 
0338     uint8_t                             ClockStretcherAmount;
0339 
0340     uint8_t                             Sclk_CKS_masterEn0_7;
0341     uint8_t                             Sclk_CKS_masterEn8_15;
0342     uint8_t                             padding[1];
0343 
0344     uint8_t                             Sclk_voltageOffset[8];
0345 
0346     SMU_ClockStretcherDataTable         ClockStretcherDataTable;
0347     SMU_CKS_LOOKUPTable                 CKS_LOOKUPTable;
0348 };
0349 
0350 typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
0351 
0352 /* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
0353 #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
0354 #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
0355 
0356 struct SMU72_Discrete_MCRegisterAddress {
0357     uint16_t s0;
0358     uint16_t s1;
0359 };
0360 
0361 typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
0362 
0363 struct SMU72_Discrete_MCRegisterSet {
0364     uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0365 };
0366 
0367 typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
0368 
0369 struct SMU72_Discrete_MCRegisters {
0370     uint8_t                             last;
0371     uint8_t                             reserved[3];
0372     SMU72_Discrete_MCRegisterAddress     address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0373     SMU72_Discrete_MCRegisterSet         data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
0374 };
0375 
0376 typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
0377 
0378 
0379 /* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
0380 
0381 struct SMU72_Discrete_FanTable {
0382     uint16_t FdoMode;
0383     int16_t  TempMin;
0384     int16_t  TempMed;
0385     int16_t  TempMax;
0386     int16_t  Slope1;
0387     int16_t  Slope2;
0388     int16_t  FdoMin;
0389     int16_t  HystUp;
0390     int16_t  HystDown;
0391     int16_t  HystSlope;
0392     int16_t  TempRespLim;
0393     int16_t  TempCurr;
0394     int16_t  SlopeCurr;
0395     int16_t  PwmCurr;
0396     uint32_t RefreshPeriod;
0397     int16_t  FdoMax;
0398     uint8_t  TempSrc;
0399     int8_t   FanControl_GL_Flag;
0400 };
0401 
0402 typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
0403 
0404 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
0405 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
0406 
0407 struct SMU7_MclkDpmScoreboard {
0408 
0409     uint32_t PercentageBusy;
0410 
0411     int32_t  PIDError;
0412     int32_t  PIDIntegral;
0413     int32_t  PIDOutput;
0414 
0415     uint32_t SigmaDeltaAccum;
0416     uint32_t SigmaDeltaOutput;
0417     uint32_t SigmaDeltaLevel;
0418 
0419     uint32_t UtilizationSetpoint;
0420 
0421     uint8_t  TdpClampMode;
0422     uint8_t  TdcClampMode;
0423     uint8_t  ThermClampMode;
0424     uint8_t  VoltageBusy;
0425 
0426     int8_t   CurrLevel;
0427     int8_t   TargLevel;
0428     uint8_t  LevelChangeInProgress;
0429     uint8_t  UpHyst;
0430 
0431     uint8_t  DownHyst;
0432     uint8_t  VoltageDownHyst;
0433     uint8_t  DpmEnable;
0434     uint8_t  DpmRunning;
0435 
0436     uint8_t  DpmForce;
0437     uint8_t  DpmForceLevel;
0438     uint8_t  DisplayWatermark;
0439     uint8_t  McArbIndex;
0440 
0441     uint32_t MinimumPerfMclk;
0442 
0443     uint8_t  AcpiReq;
0444     uint8_t  AcpiAck;
0445     uint8_t  MclkSwitchInProgress;
0446     uint8_t  MclkSwitchCritical;
0447 
0448     uint8_t  IgnoreVBlank;
0449     uint8_t  TargetMclkIndex;
0450     uint8_t  TargetMvddIndex;
0451     uint8_t  MclkSwitchResult;
0452 
0453     uint16_t VbiFailureCount;
0454     uint8_t  VbiWaitCounter;
0455     uint8_t  EnabledLevelsChange;
0456 
0457     uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
0458     uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
0459 
0460     void     (*TargetStateCalculator)(uint8_t);
0461     void     (*SavedTargetStateCalculator)(uint8_t);
0462 
0463     uint16_t AutoDpmInterval;
0464     uint16_t AutoDpmRange;
0465 
0466     uint16_t VbiTimeoutCount;
0467     uint16_t MclkSwitchingTime;
0468 
0469     uint8_t  fastSwitch;
0470     uint8_t  Save_PIC_VDDGFX_EXIT;
0471     uint8_t  Save_PIC_VDDGFX_ENTER;
0472     uint8_t  padding;
0473 
0474 };
0475 
0476 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
0477 
0478 struct SMU7_UlvScoreboard {
0479     uint8_t     EnterUlv;
0480     uint8_t     ExitUlv;
0481     uint8_t     UlvActive;
0482     uint8_t     WaitingForUlv;
0483     uint8_t     UlvEnable;
0484     uint8_t     UlvRunning;
0485     uint8_t     UlvMasterEnable;
0486     uint8_t     padding;
0487     uint32_t    UlvAbortedCount;
0488     uint32_t    UlvTimeStamp;
0489 };
0490 
0491 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
0492 
0493 struct VddgfxSavedRegisters {
0494     uint32_t GPU_DBG[3];
0495     uint32_t MEC_BaseAddress_Hi;
0496     uint32_t MEC_BaseAddress_Lo;
0497     uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
0498     uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
0499     uint32_t CP_INT_CNTL;
0500 };
0501 
0502 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
0503 
0504 struct SMU7_VddGfxScoreboard {
0505     uint8_t     VddGfxEnable;
0506     uint8_t     VddGfxActive;
0507     uint8_t     VPUResetOccured;
0508     uint8_t     padding;
0509 
0510     uint32_t    VddGfxEnteredCount;
0511     uint32_t    VddGfxAbortedCount;
0512 
0513     uint32_t    VddGfxVid;
0514 
0515     VddgfxSavedRegisters SavedRegisters;
0516 };
0517 
0518 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
0519 
0520 struct SMU7_TdcLimitScoreboard {
0521     uint8_t  Enable;
0522     uint8_t  Running;
0523     uint16_t Alpha;
0524     uint32_t FilteredIddc;
0525     uint32_t IddcLimit;
0526     uint32_t IddcHyst;
0527     SMU7_HystController_Data HystControllerData;
0528 };
0529 
0530 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
0531 
0532 struct SMU7_PkgPwrLimitScoreboard {
0533     uint8_t  Enable;
0534     uint8_t  Running;
0535     uint16_t Alpha;
0536     uint32_t FilteredPkgPwr;
0537     uint32_t Limit;
0538     uint32_t Hyst;
0539     uint32_t LimitFromDriver;
0540     SMU7_HystController_Data HystControllerData;
0541 };
0542 
0543 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
0544 
0545 struct SMU7_BapmScoreboard {
0546     uint32_t source_powers[SMU72_DTE_SOURCES];
0547     uint32_t source_powers_last[SMU72_DTE_SOURCES];
0548     int32_t entity_temperatures[SMU72_NUM_GPU_TES];
0549     int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
0550     int32_t Limit;
0551     int32_t Hyst;
0552     int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
0553     int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
0554     uint16_t ConfigTDPPowerScalar;
0555     uint16_t FanSpeedPowerScalar;
0556     uint16_t OverDrivePowerScalar;
0557     uint16_t OverDriveLimitScalar;
0558     uint16_t FinalPowerScalar;
0559     uint8_t VariantID;
0560     uint8_t spare997;
0561 
0562     SMU7_HystController_Data HystControllerData;
0563 
0564     int32_t temperature_gradient_slope;
0565     int32_t temperature_gradient;
0566     uint32_t measured_temperature;
0567 };
0568 
0569 
0570 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
0571 
0572 struct SMU7_AcpiScoreboard {
0573     uint32_t SavedInterruptMask[2];
0574     uint8_t LastACPIRequest;
0575     uint8_t CgBifResp;
0576     uint8_t RequestType;
0577     uint8_t Padding;
0578     SMU72_Discrete_ACPILevel D0Level;
0579 };
0580 
0581 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
0582 
0583 struct SMU72_Discrete_PmFuses {
0584     /* dw1  */
0585     uint8_t SviLoadLineEn;
0586     uint8_t SviLoadLineVddC;
0587     uint8_t SviLoadLineTrimVddC;
0588     uint8_t SviLoadLineOffsetVddC;
0589 
0590     /* dw2 */
0591     uint16_t TDC_VDDC_PkgLimit;
0592     uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
0593     uint8_t TDC_MAWt;
0594 
0595     /* dw3 */
0596     uint8_t TdcWaterfallCtl;
0597     uint8_t LPMLTemperatureMin;
0598     uint8_t LPMLTemperatureMax;
0599     uint8_t Reserved;
0600 
0601     /* dw4-dw7  */
0602     uint8_t LPMLTemperatureScaler[16];
0603 
0604     /* dw8-dw9  */
0605     int16_t FuzzyFan_ErrorSetDelta;
0606     int16_t FuzzyFan_ErrorRateSetDelta;
0607     int16_t FuzzyFan_PwmSetDelta;
0608     uint16_t Reserved6;
0609 
0610     /* dw10-dw14  */
0611     uint8_t GnbLPML[16];
0612 
0613     /* dw15 */
0614     uint8_t GnbLPMLMaxVid;
0615     uint8_t GnbLPMLMinVid;
0616     uint8_t Reserved1[2];
0617 
0618     /* dw16 */
0619     uint16_t BapmVddCBaseLeakageHiSidd;
0620     uint16_t BapmVddCBaseLeakageLoSidd;
0621 };
0622 
0623 typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
0624 
0625 struct SMU7_Discrete_Log_Header_Table {
0626     uint32_t    version;
0627     uint32_t    asic_id;
0628     uint16_t    flags;
0629     uint16_t    entry_size;
0630     uint32_t    total_size;
0631     uint32_t    num_of_entries;
0632     uint8_t     type;
0633     uint8_t     mode;
0634     uint8_t     filler_0[2];
0635     uint32_t    filler_1[2];
0636 };
0637 
0638 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
0639 
0640 struct SMU7_Discrete_Log_Cntl {
0641     uint8_t             Enabled;
0642     uint8_t             Type;
0643     uint8_t             padding[2];
0644     uint32_t            BufferSize;
0645     uint32_t            SamplesLogged;
0646     uint32_t            SampleSize;
0647     uint32_t            AddrL;
0648     uint32_t            AddrH;
0649 };
0650 
0651 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
0652 
0653 #define CAC_ACC_NW_NUM_OF_SIGNALS 87
0654 
0655 struct SMU7_Discrete_Cac_Collection_Table {
0656     uint32_t temperature;
0657     uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
0658 };
0659 
0660 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
0661 
0662 struct SMU7_Discrete_Cac_Verification_Table {
0663     uint32_t VddcTotalPower;
0664     uint32_t VddcLeakagePower;
0665     uint32_t VddcConstantPower;
0666     uint32_t VddcGfxDynamicPower;
0667     uint32_t VddcUvdDynamicPower;
0668     uint32_t VddcVceDynamicPower;
0669     uint32_t VddcAcpDynamicPower;
0670     uint32_t VddcPcieDynamicPower;
0671     uint32_t VddcDceDynamicPower;
0672     uint32_t VddcCurrent;
0673     uint32_t VddcVoltage;
0674     uint32_t VddciTotalPower;
0675     uint32_t VddciLeakagePower;
0676     uint32_t VddciConstantPower;
0677     uint32_t VddciDynamicPower;
0678     uint32_t Vddr1TotalPower;
0679     uint32_t Vddr1LeakagePower;
0680     uint32_t Vddr1ConstantPower;
0681     uint32_t Vddr1DynamicPower;
0682     uint32_t spare[4];
0683     uint32_t temperature;
0684 };
0685 
0686 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
0687 
0688 struct SMU7_Discrete_Pm_Status_Table {
0689     /* Thermal entities */
0690     int32_t T_meas_max;
0691     int32_t T_meas_acc;
0692     int32_t T_calc_max;
0693     int32_t T_calc_acc;
0694     uint32_t P_scalar_acc;
0695     uint32_t P_calc_max;
0696     uint32_t P_calc_acc;
0697 
0698     /*Voltage domains */
0699     uint32_t I_calc_max;
0700     uint32_t I_calc_acc;
0701     uint32_t I_calc_acc_vddci;
0702     uint32_t V_calc_noload_acc;
0703     uint32_t V_calc_load_acc;
0704     uint32_t V_calc_noload_acc_vddci;
0705     uint32_t P_meas_acc;
0706     uint32_t V_meas_noload_acc;
0707     uint32_t V_meas_load_acc;
0708     uint32_t I_meas_acc;
0709     uint32_t P_meas_acc_vddci;
0710     uint32_t V_meas_noload_acc_vddci;
0711     uint32_t V_meas_load_acc_vddci;
0712     uint32_t I_meas_acc_vddci;
0713 
0714     /*Frequency */
0715     uint16_t Sclk_dpm_residency[8];
0716     uint16_t Uvd_dpm_residency[8];
0717     uint16_t Vce_dpm_residency[8];
0718     uint16_t Mclk_dpm_residency[4];
0719 
0720     /*Chip */
0721     uint32_t P_vddci_acc;
0722     uint32_t P_vddr1_acc;
0723     uint32_t P_nte1_acc;
0724     uint32_t PkgPwr_max;
0725     uint32_t PkgPwr_acc;
0726     uint32_t MclkSwitchingTime_max;
0727     uint32_t MclkSwitchingTime_acc;
0728     uint32_t FanPwm_acc;
0729     uint32_t FanRpm_acc;
0730 
0731     uint32_t AccCnt;
0732 };
0733 
0734 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
0735 
0736 /*FIXME THESE NEED TO BE UPDATED */
0737 #define SMU7_SCLK_CAC 0x561
0738 #define SMU7_MCLK_CAC 0xF9
0739 #define SMU7_VCLK_CAC 0x2DE
0740 #define SMU7_DCLK_CAC 0x2DE
0741 #define SMU7_ECLK_CAC 0x25E
0742 #define SMU7_ACLK_CAC 0x25E
0743 #define SMU7_SAMCLK_CAC 0x25E
0744 #define SMU7_DISPCLK_CAC 0x100
0745 #define SMU7_CAC_CONSTANT 0x2EE3430
0746 #define SMU7_CAC_CONSTANT_SHIFT 18
0747 
0748 #define SMU7_VDDCI_MCLK_CONST        1765
0749 #define SMU7_VDDCI_MCLK_CONST_SHIFT  16
0750 #define SMU7_VDDCI_VDDCI_CONST       50958
0751 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
0752 #define SMU7_VDDCI_CONST             11781
0753 
0754 #define SMU7_12C_VDDCI_MCLK_CONST        1623
0755 #define SMU7_12C_VDDCI_MCLK_CONST_SHIFT  15
0756 #define SMU7_12C_VDDCI_VDDCI_CONST       40088
0757 #define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
0758 #define SMU7_12C_VDDCI_CONST             20856
0759 
0760 #define SMU7_VDDCI_STROBE_PWR        1331
0761 
0762 #define SMU7_VDDR1_CONST            693
0763 #define SMU7_VDDR1_CAC_WEIGHT       20
0764 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
0765 #define SMU7_VDDR1_STROBE_PWR       512
0766 
0767 #define SMU7_AREA_COEFF_UVD 0xA78
0768 #define SMU7_AREA_COEFF_VCE 0x190A
0769 #define SMU7_AREA_COEFF_ACP 0x22D1
0770 #define SMU7_AREA_COEFF_SAMU 0x534
0771 
0772 /*ThermOutMode values */
0773 #define SMU7_THERM_OUT_MODE_DISABLE       0x0
0774 #define SMU7_THERM_OUT_MODE_THERM_ONLY    0x1
0775 #define SMU7_THERM_OUT_MODE_THERM_VRHOT   0x2
0776 
0777 #if !defined(SMC_MICROCODE)
0778 #pragma pack(pop)
0779 #endif
0780 
0781 
0782 #endif
0783
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