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0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef SMU72_H
0025 #define SMU72_H
0026 
0027 #if !defined(SMC_MICROCODE)
0028 #pragma pack(push, 1)
0029 #endif
0030 
0031 #define SMU__NUM_SCLK_DPM_STATE  8
0032 #define SMU__NUM_MCLK_DPM_LEVELS 4
0033 #define SMU__NUM_LCLK_DPM_LEVELS 8
0034 #define SMU__NUM_PCIE_DPM_LEVELS 8
0035 
0036 enum SID_OPTION {
0037     SID_OPTION_HI,
0038     SID_OPTION_LO,
0039     SID_OPTION_COUNT
0040 };
0041 
0042 enum Poly3rdOrderCoeff {
0043     LEAKAGE_TEMPERATURE_SCALAR,
0044     LEAKAGE_VOLTAGE_SCALAR,
0045     DYNAMIC_VOLTAGE_SCALAR,
0046     POLY_3RD_ORDER_COUNT
0047 };
0048 
0049 struct SMU7_Poly3rdOrder_Data {
0050     int32_t a;
0051     int32_t b;
0052     int32_t c;
0053     int32_t d;
0054     uint8_t a_shift;
0055     uint8_t b_shift;
0056     uint8_t c_shift;
0057     uint8_t x_shift;
0058 };
0059 
0060 typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
0061 
0062 struct Power_Calculator_Data {
0063     uint16_t NoLoadVoltage;
0064     uint16_t LoadVoltage;
0065     uint16_t Resistance;
0066     uint16_t Temperature;
0067     uint16_t BaseLeakage;
0068     uint16_t LkgTempScalar;
0069     uint16_t LkgVoltScalar;
0070     uint16_t LkgAreaScalar;
0071     uint16_t LkgPower;
0072     uint16_t DynVoltScalar;
0073     uint32_t Cac;
0074     uint32_t DynPower;
0075     uint32_t TotalCurrent;
0076     uint32_t TotalPower;
0077 };
0078 
0079 typedef struct Power_Calculator_Data PowerCalculatorData_t;
0080 
0081 struct Gc_Cac_Weight_Data {
0082     uint8_t index;
0083     uint32_t value;
0084 };
0085 
0086 typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
0087 
0088 
0089 typedef struct {
0090     uint32_t high;
0091     uint32_t low;
0092 } data_64_t;
0093 
0094 typedef struct {
0095     data_64_t high;
0096     data_64_t low;
0097 } data_128_t;
0098 
0099 #define SMU7_CONTEXT_ID_SMC        1
0100 #define SMU7_CONTEXT_ID_VBIOS      2
0101 
0102 #define SMU72_MAX_LEVELS_VDDC            16
0103 #define SMU72_MAX_LEVELS_VDDGFX          16
0104 #define SMU72_MAX_LEVELS_VDDCI           8
0105 #define SMU72_MAX_LEVELS_MVDD            4
0106 
0107 #define SMU_MAX_SMIO_LEVELS              4
0108 
0109 #define SMU72_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   /* SCLK + SQ DPM + ULV */
0110 #define SMU72_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   /* MCLK Levels DPM */
0111 #define SMU72_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  /* LCLK Levels */
0112 #define SMU72_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  /* PCIe speed and number of lanes. */
0113 #define SMU72_MAX_LEVELS_UVD             8   /* VCLK/DCLK levels for UVD. */
0114 #define SMU72_MAX_LEVELS_VCE             8   /* ECLK levels for VCE. */
0115 #define SMU72_MAX_LEVELS_ACP             8   /* ACLK levels for ACP. */
0116 #define SMU72_MAX_LEVELS_SAMU            8   /* SAMCLK levels for SAMU. */
0117 #define SMU72_MAX_ENTRIES_SMIO           32  /* Number of entries in SMIO table. */
0118 
0119 #define DPM_NO_LIMIT 0
0120 #define DPM_NO_UP 1
0121 #define DPM_GO_DOWN 2
0122 #define DPM_GO_UP 3
0123 
0124 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
0125 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
0126 
0127 #define GPIO_CLAMP_MODE_VRHOT      1
0128 #define GPIO_CLAMP_MODE_THERM      2
0129 #define GPIO_CLAMP_MODE_DC         4
0130 
0131 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
0132 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
0133 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
0134 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
0135 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
0136 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
0137 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
0138 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
0139 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
0140 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
0141 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
0142 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
0143 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
0144 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
0145 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
0146 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
0147 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
0148 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
0149 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
0150 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
0151 
0152 /* Virtualization Defines */
0153 #define CG_XDMA_MASK  0x1
0154 #define CG_XDMA_SHIFT 0
0155 #define CG_UVD_MASK   0x2
0156 #define CG_UVD_SHIFT  1
0157 #define CG_VCE_MASK   0x4
0158 #define CG_VCE_SHIFT  2
0159 #define CG_SAMU_MASK  0x8
0160 #define CG_SAMU_SHIFT 3
0161 #define CG_GFX_MASK   0x10
0162 #define CG_GFX_SHIFT  4
0163 #define CG_SDMA_MASK  0x20
0164 #define CG_SDMA_SHIFT 5
0165 #define CG_HDP_MASK   0x40
0166 #define CG_HDP_SHIFT  6
0167 #define CG_MC_MASK    0x80
0168 #define CG_MC_SHIFT   7
0169 #define CG_DRM_MASK   0x100
0170 #define CG_DRM_SHIFT  8
0171 #define CG_ROM_MASK   0x200
0172 #define CG_ROM_SHIFT  9
0173 #define CG_BIF_MASK   0x400
0174 #define CG_BIF_SHIFT  10
0175 
0176 #define SMU72_DTE_ITERATIONS 5
0177 #define SMU72_DTE_SOURCES 3
0178 #define SMU72_DTE_SINKS 1
0179 #define SMU72_NUM_CPU_TES 0
0180 #define SMU72_NUM_GPU_TES 1
0181 #define SMU72_NUM_NON_TES 2
0182 #define SMU72_DTE_FAN_SCALAR_MIN 0x100
0183 #define SMU72_DTE_FAN_SCALAR_MAX 0x166
0184 #define SMU72_DTE_FAN_TEMP_MAX 93
0185 #define SMU72_DTE_FAN_TEMP_MIN 83
0186 
0187 #if defined SMU__FUSION_ONLY
0188 #define SMU7_DTE_ITERATIONS 5
0189 #define SMU7_DTE_SOURCES 5
0190 #define SMU7_DTE_SINKS 3
0191 #define SMU7_NUM_CPU_TES 2
0192 #define SMU7_NUM_GPU_TES 1
0193 #define SMU7_NUM_NON_TES 2
0194 #endif
0195 
0196 struct SMU7_HystController_Data {
0197     uint8_t waterfall_up;
0198     uint8_t waterfall_down;
0199     uint8_t waterfall_limit;
0200     uint8_t spare;
0201     uint16_t release_cnt;
0202     uint16_t release_limit;
0203 };
0204 
0205 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
0206 
0207 struct SMU72_PIDController {
0208     uint32_t Ki;
0209     int32_t LFWindupUpperLim;
0210     int32_t LFWindupLowerLim;
0211     uint32_t StatePrecision;
0212     uint32_t LfPrecision;
0213     uint32_t LfOffset;
0214     uint32_t MaxState;
0215     uint32_t MaxLfFraction;
0216     uint32_t StateShift;
0217 };
0218 
0219 typedef struct SMU72_PIDController SMU72_PIDController;
0220 
0221 struct SMU7_LocalDpmScoreboard {
0222     uint32_t PercentageBusy;
0223 
0224     int32_t  PIDError;
0225     int32_t  PIDIntegral;
0226     int32_t  PIDOutput;
0227 
0228     uint32_t SigmaDeltaAccum;
0229     uint32_t SigmaDeltaOutput;
0230     uint32_t SigmaDeltaLevel;
0231 
0232     uint32_t UtilizationSetpoint;
0233 
0234     uint8_t  TdpClampMode;
0235     uint8_t  TdcClampMode;
0236     uint8_t  ThermClampMode;
0237     uint8_t  VoltageBusy;
0238 
0239     int8_t   CurrLevel;
0240     int8_t   TargLevel;
0241     uint8_t  LevelChangeInProgress;
0242     uint8_t  UpHyst;
0243 
0244     uint8_t  DownHyst;
0245     uint8_t  VoltageDownHyst;
0246     uint8_t  DpmEnable;
0247     uint8_t  DpmRunning;
0248 
0249     uint8_t  DpmForce;
0250     uint8_t  DpmForceLevel;
0251     uint8_t  DisplayWatermark;
0252     uint8_t  McArbIndex;
0253 
0254     uint32_t MinimumPerfSclk;
0255 
0256     uint8_t  AcpiReq;
0257     uint8_t  AcpiAck;
0258     uint8_t  GfxClkSlow;
0259     uint8_t  GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
0260 
0261     uint8_t  FpsFilterWeight;
0262     uint8_t  EnabledLevelsChange;
0263     uint8_t  DteClampMode;
0264     uint8_t  FpsClampMode;
0265 
0266     uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
0267     uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
0268 
0269     void     (*TargetStateCalculator)(uint8_t);
0270     void     (*SavedTargetStateCalculator)(uint8_t);
0271 
0272     uint16_t AutoDpmInterval;
0273     uint16_t AutoDpmRange;
0274 
0275     uint8_t  FpsEnabled;
0276     uint8_t  MaxPerfLevel;
0277     uint8_t  AllowLowClkInterruptToHost;
0278     uint8_t  FpsRunning;
0279 
0280     uint32_t MaxAllowedFrequency;
0281 
0282     uint32_t FilteredSclkFrequency;
0283     uint32_t LastSclkFrequency;
0284     uint32_t FilteredSclkFrequencyCnt;
0285 };
0286 
0287 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
0288 
0289 #define SMU7_MAX_VOLTAGE_CLIENTS 12
0290 
0291 typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
0292 
0293 struct SMU_VoltageLevel {
0294     uint8_t Vddc;
0295     uint8_t Vddci;
0296     uint8_t VddGfx;
0297     uint8_t Phases;
0298 };
0299 
0300 typedef struct SMU_VoltageLevel SMU_VoltageLevel;
0301 
0302 struct SMU7_VoltageScoreboard {
0303     SMU_VoltageLevel CurrentVoltage;
0304     SMU_VoltageLevel TargetVoltage;
0305     uint16_t MaxVid;
0306     uint8_t  HighestVidOffset;
0307     uint8_t  CurrentVidOffset;
0308 
0309     uint8_t  ControllerBusy;
0310     uint8_t  CurrentVid;
0311     uint8_t  CurrentVddciVid;
0312     uint8_t  VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
0313 
0314     SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
0315     uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
0316 
0317     uint8_t  TargetIndex;
0318     uint8_t  Delay;
0319     uint8_t  ControllerEnable;
0320     uint8_t  ControllerRunning;
0321     uint16_t CurrentStdVoltageHiSidd;
0322     uint16_t CurrentStdVoltageLoSidd;
0323     uint8_t  OverrideVoltage;
0324     uint8_t  VddcUseUlvOffset;
0325     uint8_t  VddGfxUseUlvOffset;
0326     uint8_t  padding;
0327 
0328     VoltageChangeHandler_t ChangeVddc;
0329     VoltageChangeHandler_t ChangeVddGfx;
0330     VoltageChangeHandler_t ChangeVddci;
0331     VoltageChangeHandler_t ChangePhase;
0332     VoltageChangeHandler_t ChangeMvdd;
0333 
0334     VoltageChangeHandler_t functionLinks[6];
0335 
0336     uint8_t *VddcFollower1;
0337     uint8_t *VddcFollower2;
0338     int16_t  Driver_OD_RequestedVidOffset1;
0339     int16_t  Driver_OD_RequestedVidOffset2;
0340 
0341 };
0342 
0343 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
0344 
0345 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
0346 
0347 struct SMU7_PCIeLinkSpeedScoreboard {
0348     uint8_t     DpmEnable;
0349     uint8_t     DpmRunning;
0350     uint8_t     DpmForce;
0351     uint8_t     DpmForceLevel;
0352 
0353     uint8_t     CurrentLinkSpeed;
0354     uint8_t     EnabledLevelsChange;
0355     uint16_t    AutoDpmInterval;
0356 
0357     uint16_t    AutoDpmRange;
0358     uint16_t    AutoDpmCount;
0359 
0360     uint8_t     DpmMode;
0361     uint8_t     AcpiReq;
0362     uint8_t     AcpiAck;
0363     uint8_t     CurrentLinkLevel;
0364 
0365 };
0366 
0367 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
0368 
0369 /* -------------------------------------------------------- CAC table ------------------------------------------------------ */
0370 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
0371 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
0372 #define SMU7_SCALE_I  7
0373 #define SMU7_SCALE_R 12
0374 
0375 struct SMU7_PowerScoreboard {
0376     PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
0377     PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
0378 
0379     uint32_t TotalGpuPower;
0380     uint32_t TdcCurrent;
0381 
0382     uint16_t   VddciTotalPower;
0383     uint16_t   sparesasfsdfd;
0384     uint16_t   Vddr1Power;
0385     uint16_t   RocPower;
0386 
0387     uint16_t   CalcMeasPowerBlend;
0388     uint8_t    SidOptionPower;
0389     uint8_t    SidOptionCurrent;
0390 
0391     uint32_t   WinTime;
0392 
0393     uint16_t Telemetry_1_slope;
0394     uint16_t Telemetry_2_slope;
0395     int32_t Telemetry_1_offset;
0396     int32_t Telemetry_2_offset;
0397 
0398     uint32_t VddcCurrentTelemetry;
0399     uint32_t VddGfxCurrentTelemetry;
0400     uint32_t VddcPowerTelemetry;
0401     uint32_t VddGfxPowerTelemetry;
0402     uint32_t VddciPowerTelemetry;
0403 
0404     uint32_t VddcPower;
0405     uint32_t VddGfxPower;
0406     uint32_t VddciPower;
0407 
0408     uint32_t TelemetryCurrent[2];
0409     uint32_t TelemetryVoltage[2];
0410     uint32_t TelemetryPower[2];
0411 };
0412 
0413 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
0414 
0415 struct SMU7_ThermalScoreboard {
0416     int16_t  GpuLimit;
0417     int16_t  GpuHyst;
0418     uint16_t CurrGnbTemp;
0419     uint16_t FilteredGnbTemp;
0420 
0421     uint8_t  ControllerEnable;
0422     uint8_t  ControllerRunning;
0423     uint8_t  AutoTmonCalInterval;
0424     uint8_t  AutoTmonCalEnable;
0425 
0426     uint8_t  ThermalDpmEnabled;
0427     uint8_t  SclkEnabledMask;
0428     uint8_t  spare[2];
0429     int32_t  temperature_gradient;
0430 
0431     SMU7_HystController_Data HystControllerData;
0432     int32_t  WeightedSensorTemperature;
0433     uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
0434     uint32_t Alpha;
0435 };
0436 
0437 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
0438 
0439 /* For FeatureEnables: */
0440 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
0441 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
0442 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
0443 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
0444 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
0445 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
0446 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
0447 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
0448 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
0449 
0450 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
0451 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
0452 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
0453 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
0454 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
0455 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
0456 
0457 /* All 'soft registers' should be uint32_t. */
0458 struct SMU72_SoftRegisters {
0459     uint32_t        RefClockFrequency;
0460     uint32_t        PmTimerPeriod;
0461     uint32_t        FeatureEnables;
0462 
0463     uint32_t        PreVBlankGap;
0464     uint32_t        VBlankTimeout;
0465     uint32_t        TrainTimeGap;
0466 
0467     uint32_t        MvddSwitchTime;
0468     uint32_t        LongestAcpiTrainTime;
0469     uint32_t        AcpiDelay;
0470     uint32_t        G5TrainTime;
0471     uint32_t        DelayMpllPwron;
0472     uint32_t        VoltageChangeTimeout;
0473 
0474     uint32_t        HandshakeDisables;
0475 
0476     uint8_t         DisplayPhy1Config;
0477     uint8_t         DisplayPhy2Config;
0478     uint8_t         DisplayPhy3Config;
0479     uint8_t         DisplayPhy4Config;
0480 
0481     uint8_t         DisplayPhy5Config;
0482     uint8_t         DisplayPhy6Config;
0483     uint8_t         DisplayPhy7Config;
0484     uint8_t         DisplayPhy8Config;
0485 
0486     uint32_t        AverageGraphicsActivity;
0487     uint32_t        AverageMemoryActivity;
0488     uint32_t        AverageGioActivity;
0489 
0490     uint8_t         SClkDpmEnabledLevels;
0491     uint8_t         MClkDpmEnabledLevels;
0492     uint8_t         LClkDpmEnabledLevels;
0493     uint8_t         PCIeDpmEnabledLevels;
0494 
0495     uint8_t         UVDDpmEnabledLevels;
0496     uint8_t         SAMUDpmEnabledLevels;
0497     uint8_t         ACPDpmEnabledLevels;
0498     uint8_t         VCEDpmEnabledLevels;
0499 
0500     uint32_t        DRAM_LOG_ADDR_H;
0501     uint32_t        DRAM_LOG_ADDR_L;
0502     uint32_t        DRAM_LOG_PHY_ADDR_H;
0503     uint32_t        DRAM_LOG_PHY_ADDR_L;
0504     uint32_t        DRAM_LOG_BUFF_SIZE;
0505     uint32_t        UlvEnterCount;
0506     uint32_t        UlvTime;
0507     uint32_t        UcodeLoadStatus;
0508     uint32_t        Reserved[2];
0509 
0510 };
0511 
0512 typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
0513 
0514 struct SMU72_Firmware_Header {
0515     uint32_t Digest[5];
0516     uint32_t Version;
0517     uint32_t HeaderSize;
0518     uint32_t Flags;
0519     uint32_t EntryPoint;
0520     uint32_t CodeSize;
0521     uint32_t ImageSize;
0522 
0523     uint32_t Rtos;
0524     uint32_t SoftRegisters;
0525     uint32_t DpmTable;
0526     uint32_t FanTable;
0527     uint32_t CacConfigTable;
0528     uint32_t CacStatusTable;
0529     uint32_t mcRegisterTable;
0530     uint32_t mcArbDramTimingTable;
0531     uint32_t PmFuseTable;
0532     uint32_t Globals;
0533     uint32_t ClockStretcherTable;
0534     uint32_t Reserved[41];
0535     uint32_t Signature;
0536 };
0537 
0538 typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
0539 
0540 #define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
0541 
0542 enum  DisplayConfig {
0543     PowerDown = 1,
0544     DP54x4,
0545     DP54x2,
0546     DP54x1,
0547     DP27x4,
0548     DP27x2,
0549     DP27x1,
0550     HDMI297,
0551     HDMI162,
0552     LVDS,
0553     DP324x4,
0554     DP324x2,
0555     DP324x1
0556 };
0557 
0558 #define MC_BLOCK_COUNT 1
0559 #define CPL_BLOCK_COUNT 5
0560 #define SE_BLOCK_COUNT 15
0561 #define GC_BLOCK_COUNT 24
0562 
0563 struct SMU7_Local_Cac {
0564     uint8_t BlockId;
0565     uint8_t SignalId;
0566     uint8_t Threshold;
0567     uint8_t Padding;
0568 };
0569 
0570 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
0571 
0572 struct SMU7_Local_Cac_Table {
0573     SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
0574     SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
0575     SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
0576     SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
0577 };
0578 
0579 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
0580 
0581 #if !defined(SMC_MICROCODE)
0582 #pragma pack(pop)
0583 #endif
0584 
0585 /* Description of Clock Gating bitmask for Tonga: */
0586 /* System Clock Gating */
0587 #define CG_SYS_BITMASK_FIRST_BIT      0  /* First bit of Sys CG bitmask */
0588 #define CG_SYS_BITMASK_LAST_BIT       9  /* Last bit of Sys CG bitmask */
0589 #define CG_SYS_BIF_MGLS_SHIFT         0
0590 #define CG_SYS_ROM_SHIFT              1
0591 #define CG_SYS_MC_MGCG_SHIFT          2
0592 #define CG_SYS_MC_MGLS_SHIFT          3
0593 #define CG_SYS_SDMA_MGCG_SHIFT        4
0594 #define CG_SYS_SDMA_MGLS_SHIFT        5
0595 #define CG_SYS_DRM_MGCG_SHIFT         6
0596 #define CG_SYS_HDP_MGCG_SHIFT         7
0597 #define CG_SYS_HDP_MGLS_SHIFT         8
0598 #define CG_SYS_DRM_MGLS_SHIFT         9
0599 
0600 #define CG_SYS_BIF_MGLS_MASK          0x1
0601 #define CG_SYS_ROM_MASK               0x2
0602 #define CG_SYS_MC_MGCG_MASK           0x4
0603 #define CG_SYS_MC_MGLS_MASK           0x8
0604 #define CG_SYS_SDMA_MGCG_MASK         0x10
0605 #define CG_SYS_SDMA_MGLS_MASK         0x20
0606 #define CG_SYS_DRM_MGCG_MASK          0x40
0607 #define CG_SYS_HDP_MGCG_MASK          0x80
0608 #define CG_SYS_HDP_MGLS_MASK          0x100
0609 #define CG_SYS_DRM_MGLS_MASK          0x200
0610 
0611 /* Graphics Clock Gating */
0612 #define CG_GFX_BITMASK_FIRST_BIT      16 /* First bit of Gfx CG bitmask */
0613 #define CG_GFX_BITMASK_LAST_BIT       20 /* Last bit of Gfx CG bitmask */
0614 #define CG_GFX_CGCG_SHIFT             16
0615 #define CG_GFX_CGLS_SHIFT             17
0616 #define CG_CPF_MGCG_SHIFT             18
0617 #define CG_RLC_MGCG_SHIFT             19
0618 #define CG_GFX_OTHERS_MGCG_SHIFT      20
0619 
0620 #define CG_GFX_CGCG_MASK              0x00010000
0621 #define CG_GFX_CGLS_MASK              0x00020000
0622 #define CG_CPF_MGCG_MASK              0x00040000
0623 #define CG_RLC_MGCG_MASK              0x00080000
0624 #define CG_GFX_OTHERS_MGCG_MASK       0x00100000
0625 
0626 /* Voltage Regulator Configuration */
0627 /* VR Config info is contained in dpmTable.VRConfig */
0628 
0629 #define VRCONF_VDDC_MASK         0x000000FF
0630 #define VRCONF_VDDC_SHIFT        0
0631 #define VRCONF_VDDGFX_MASK       0x0000FF00
0632 #define VRCONF_VDDGFX_SHIFT      8
0633 #define VRCONF_VDDCI_MASK        0x00FF0000
0634 #define VRCONF_VDDCI_SHIFT       16
0635 #define VRCONF_MVDD_MASK         0xFF000000
0636 #define VRCONF_MVDD_SHIFT        24
0637 
0638 #define VR_MERGED_WITH_VDDC      0
0639 #define VR_SVI2_PLANE_1          1
0640 #define VR_SVI2_PLANE_2          2
0641 #define VR_SMIO_PATTERN_1        3
0642 #define VR_SMIO_PATTERN_2        4
0643 #define VR_STATIC_VOLTAGE        5
0644 
0645 /* Clock Stretcher Configuration */
0646 
0647 #define CLOCK_STRETCHER_MAX_ENTRIES 0x4
0648 #define CKS_LOOKUPTable_MAX_ENTRIES 0x4
0649 
0650 /* The 'settings' field is subdivided in the following way: */
0651 #define CLOCK_STRETCHER_SETTING_DDT_MASK             0x01
0652 #define CLOCK_STRETCHER_SETTING_DDT_SHIFT            0x0
0653 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK  0x1E
0654 #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
0655 #define CLOCK_STRETCHER_SETTING_ENABLE_MASK          0x80
0656 #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT         0x7
0657 
0658 struct SMU_ClockStretcherDataTableEntry {
0659     uint8_t minVID;
0660     uint8_t maxVID;
0661 
0662     uint16_t setting;
0663 };
0664 typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
0665 
0666 struct SMU_ClockStretcherDataTable {
0667     SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
0668 };
0669 typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
0670 
0671 struct SMU_CKS_LOOKUPTableEntry {
0672     uint16_t minFreq;
0673     uint16_t maxFreq;
0674 
0675     uint8_t setting;
0676     uint8_t padding[3];
0677 };
0678 typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
0679 
0680 struct SMU_CKS_LOOKUPTable {
0681     SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
0682 };
0683 typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
0684 
0685 #endif
0686 
0687
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