powerplay/inc/smu71_discrete.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef SMU71_DISCRETE_H
0024 #define SMU71_DISCRETE_H
0025
0026 #include "smu71.h"
0027
0028 #if !defined(SMC_MICROCODE)
0029 #pragma pack(push, 1)
0030 #endif
0031
0032 #define VDDC_ON_SVI2  0x1
0033 #define VDDCI_ON_SVI2 0x2
0034 #define MVDD_ON_SVI2  0x4
0035
0036 struct SMU71_Discrete_VoltageLevel
0037 {
0038     uint16_t    Voltage;
0039     uint16_t    StdVoltageHiSidd;
0040     uint16_t    StdVoltageLoSidd;
0041     uint8_t     Smio;
0042     uint8_t     padding;
0043 };
0044
0045 typedef struct SMU71_Discrete_VoltageLevel SMU71_Discrete_VoltageLevel;
0046
0047 struct SMU71_Discrete_GraphicsLevel
0048 {
0049     uint32_t    MinVddc;
0050     uint32_t    MinVddcPhases;
0051
0052     uint32_t    SclkFrequency;
0053
0054     uint8_t     pcieDpmLevel;
0055     uint8_t     DeepSleepDivId;
0056     uint16_t    ActivityLevel;
0057
0058     uint32_t    CgSpllFuncCntl3;
0059     uint32_t    CgSpllFuncCntl4;
0060     uint32_t    SpllSpreadSpectrum;
0061     uint32_t    SpllSpreadSpectrum2;
0062     uint32_t    CcPwrDynRm;
0063     uint32_t    CcPwrDynRm1;
0064     uint8_t     SclkDid;
0065     uint8_t     DisplayWatermark;
0066     uint8_t     EnabledForActivity;
0067     uint8_t     EnabledForThrottle;
0068     uint8_t     UpHyst;
0069     uint8_t     DownHyst;
0070     uint8_t     VoltageDownHyst;
0071     uint8_t     PowerThrottle;
0072 };
0073
0074 typedef struct SMU71_Discrete_GraphicsLevel SMU71_Discrete_GraphicsLevel;
0075
0076 struct SMU71_Discrete_ACPILevel
0077 {
0078     uint32_t    Flags;
0079     uint32_t    MinVddc;
0080     uint32_t    MinVddcPhases;
0081     uint32_t    SclkFrequency;
0082     uint8_t     SclkDid;
0083     uint8_t     DisplayWatermark;
0084     uint8_t     DeepSleepDivId;
0085     uint8_t     padding;
0086     uint32_t    CgSpllFuncCntl;
0087     uint32_t    CgSpllFuncCntl2;
0088     uint32_t    CgSpllFuncCntl3;
0089     uint32_t    CgSpllFuncCntl4;
0090     uint32_t    SpllSpreadSpectrum;
0091     uint32_t    SpllSpreadSpectrum2;
0092     uint32_t    CcPwrDynRm;
0093     uint32_t    CcPwrDynRm1;
0094 };
0095
0096 typedef struct SMU71_Discrete_ACPILevel SMU71_Discrete_ACPILevel;
0097
0098 struct SMU71_Discrete_Ulv
0099 {
0100     uint32_t    CcPwrDynRm;
0101     uint32_t    CcPwrDynRm1;
0102     uint16_t    VddcOffset;
0103     uint8_t     VddcOffsetVid;
0104     uint8_t     VddcPhase;
0105     uint32_t    Reserved;
0106 };
0107
0108 typedef struct SMU71_Discrete_Ulv SMU71_Discrete_Ulv;
0109
0110 struct SMU71_Discrete_MemoryLevel
0111 {
0112     uint32_t    MinVddc;
0113     uint32_t    MinVddcPhases;
0114     uint32_t    MinVddci;
0115     uint32_t    MinMvdd;
0116
0117     uint32_t    MclkFrequency;
0118
0119     uint8_t     EdcReadEnable;
0120     uint8_t     EdcWriteEnable;
0121     uint8_t     RttEnable;
0122     uint8_t     StutterEnable;
0123
0124     uint8_t     StrobeEnable;
0125     uint8_t     StrobeRatio;
0126     uint8_t     EnabledForThrottle;
0127     uint8_t     EnabledForActivity;
0128
0129     uint8_t     UpHyst;
0130     uint8_t     DownHyst;
0131     uint8_t     VoltageDownHyst;
0132     uint8_t     padding;
0133
0134     uint16_t    ActivityLevel;
0135     uint8_t     DisplayWatermark;
0136     uint8_t     padding1;
0137
0138     uint32_t    MpllFuncCntl;
0139     uint32_t    MpllFuncCntl_1;
0140     uint32_t    MpllFuncCntl_2;
0141     uint32_t    MpllAdFuncCntl;
0142     uint32_t    MpllDqFuncCntl;
0143     uint32_t    MclkPwrmgtCntl;
0144     uint32_t    DllCntl;
0145     uint32_t    MpllSs1;
0146     uint32_t    MpllSs2;
0147 };
0148
0149 typedef struct SMU71_Discrete_MemoryLevel SMU71_Discrete_MemoryLevel;
0150
0151 struct SMU71_Discrete_LinkLevel
0152 {
0153     uint8_t     PcieGenSpeed;           ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
0154     uint8_t     PcieLaneCount;          ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
0155     uint8_t     EnabledForActivity;
0156     uint8_t     SPC;
0157     uint32_t    DownThreshold;
0158     uint32_t    UpThreshold;
0159     uint32_t    Reserved;
0160 };
0161
0162 typedef struct SMU71_Discrete_LinkLevel SMU71_Discrete_LinkLevel;
0163
0164
0165 #ifdef SMU__DYNAMIC_MCARB_SETTINGS
0166 // MC ARB DRAM Timing registers.
0167 struct SMU71_Discrete_MCArbDramTimingTableEntry
0168 {
0169     uint32_t McArbDramTiming;
0170     uint32_t McArbDramTiming2;
0171     uint8_t  McArbBurstTime;
0172     uint8_t  padding[3];
0173 };
0174
0175 typedef struct SMU71_Discrete_MCArbDramTimingTableEntry SMU71_Discrete_MCArbDramTimingTableEntry;
0176
0177 struct SMU71_Discrete_MCArbDramTimingTable
0178 {
0179     SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
0180 };
0181
0182 typedef struct SMU71_Discrete_MCArbDramTimingTable SMU71_Discrete_MCArbDramTimingTable;
0183 #endif
0184
0185 // UVD VCLK/DCLK state (level) definition.
0186 struct SMU71_Discrete_UvdLevel
0187 {
0188     uint32_t VclkFrequency;
0189     uint32_t DclkFrequency;
0190     uint16_t MinVddc;
0191     uint8_t  MinVddcPhases;
0192     uint8_t  VclkDivider;
0193     uint8_t  DclkDivider;
0194     uint8_t  padding[3];
0195 };
0196
0197 typedef struct SMU71_Discrete_UvdLevel SMU71_Discrete_UvdLevel;
0198
0199 // Clocks for other external blocks (VCE, ACP, SAMU).
0200 struct SMU71_Discrete_ExtClkLevel
0201 {
0202     uint32_t Frequency;
0203     uint16_t MinVoltage;
0204     uint8_t  MinPhases;
0205     uint8_t  Divider;
0206 };
0207
0208 typedef struct SMU71_Discrete_ExtClkLevel SMU71_Discrete_ExtClkLevel;
0209
0210 // Everything that we need to keep track of about the current state.
0211 // Use this instead of copies of the GraphicsLevel and MemoryLevel structures to keep track of state parameters
0212 // that need to be checked later.
0213 // We don't need to cache everything about a state, just a few parameters.
0214 struct SMU71_Discrete_StateInfo
0215 {
0216     uint32_t SclkFrequency;
0217     uint32_t MclkFrequency;
0218     uint32_t VclkFrequency;
0219     uint32_t DclkFrequency;
0220     uint32_t SamclkFrequency;
0221     uint32_t AclkFrequency;
0222     uint32_t EclkFrequency;
0223     uint16_t MvddVoltage;
0224     uint16_t padding16;
0225     uint8_t  DisplayWatermark;
0226     uint8_t  McArbIndex;
0227     uint8_t  McRegIndex;
0228     uint8_t  SeqIndex;
0229     uint8_t  SclkDid;
0230     int8_t   SclkIndex;
0231     int8_t   MclkIndex;
0232     uint8_t  PCIeGen;
0233
0234 };
0235
0236 typedef struct SMU71_Discrete_StateInfo SMU71_Discrete_StateInfo;
0237
0238
0239 struct SMU71_Discrete_DpmTable
0240 {
0241     // Multi-DPM controller settings
0242     SMU71_PIDController                  GraphicsPIDController;
0243     SMU71_PIDController                  MemoryPIDController;
0244     SMU71_PIDController                  LinkPIDController;
0245
0246     uint32_t                            SystemFlags;
0247
0248     // SMIO masks for voltage and phase controls
0249     uint32_t                            SmioMaskVddcVid;
0250     uint32_t                            SmioMaskVddcPhase;
0251     uint32_t                            SmioMaskVddciVid;
0252     uint32_t                            SmioMaskMvddVid;
0253
0254     uint32_t                            VddcLevelCount;
0255     uint32_t                            VddciLevelCount;
0256     uint32_t                            MvddLevelCount;
0257
0258     SMU71_Discrete_VoltageLevel          VddcLevel               [SMU71_MAX_LEVELS_VDDC];
0259     SMU71_Discrete_VoltageLevel          VddciLevel              [SMU71_MAX_LEVELS_VDDCI];
0260     SMU71_Discrete_VoltageLevel          MvddLevel               [SMU71_MAX_LEVELS_MVDD];
0261
0262     uint8_t                             GraphicsDpmLevelCount;
0263     uint8_t                             MemoryDpmLevelCount;
0264     uint8_t                             LinkLevelCount;
0265     uint8_t                             MasterDeepSleepControl;
0266
0267     uint32_t                            Reserved[5];
0268
0269     // State table entries for each DPM state
0270     SMU71_Discrete_GraphicsLevel         GraphicsLevel           [SMU71_MAX_LEVELS_GRAPHICS];
0271     SMU71_Discrete_MemoryLevel           MemoryACPILevel;
0272     SMU71_Discrete_MemoryLevel           MemoryLevel             [SMU71_MAX_LEVELS_MEMORY];
0273     SMU71_Discrete_LinkLevel             LinkLevel               [SMU71_MAX_LEVELS_LINK];
0274     SMU71_Discrete_ACPILevel             ACPILevel;
0275
0276     uint32_t                            SclkStepSize;
0277     uint32_t                            Smio                    [SMU71_MAX_ENTRIES_SMIO];
0278
0279     uint8_t                             GraphicsBootLevel;
0280     uint8_t                             GraphicsVoltageChangeEnable;
0281     uint8_t                             GraphicsThermThrottleEnable;
0282     uint8_t                             GraphicsInterval;
0283
0284     uint8_t                             VoltageInterval;
0285     uint8_t                             ThermalInterval;
0286     uint16_t                            TemperatureLimitHigh;
0287
0288     uint16_t                            TemperatureLimitLow;
0289     uint8_t                             MemoryBootLevel;
0290     uint8_t                             MemoryVoltageChangeEnable;
0291
0292     uint8_t                             MemoryInterval;
0293     uint8_t                             MemoryThermThrottleEnable;
0294     uint8_t                             MergedVddci;
0295     uint8_t                             padding2;
0296
0297     uint16_t                            VoltageResponseTime;
0298     uint16_t                            PhaseResponseTime;
0299
0300     uint8_t                             PCIeBootLinkLevel;
0301     uint8_t                             PCIeGenInterval;
0302     uint8_t                             DTEInterval;
0303     uint8_t                             DTEMode;
0304
0305     uint8_t                             SVI2Enable;
0306     uint8_t                             VRHotGpio;
0307     uint8_t                             AcDcGpio;
0308     uint8_t                             ThermGpio;
0309
0310     uint32_t                            DisplayCac;
0311
0312     uint16_t                            MaxPwr;
0313     uint16_t                            NomPwr;
0314
0315     uint16_t                            FpsHighThreshold;
0316     uint16_t                            FpsLowThreshold;
0317
0318     uint16_t                            BAPMTI_R  [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
0319     uint16_t                            BAPMTI_RC [SMU71_DTE_ITERATIONS][SMU71_DTE_SOURCES][SMU71_DTE_SINKS];
0320
0321     uint8_t                             DTEAmbientTempBase;
0322     uint8_t                             DTETjOffset;
0323     uint8_t                             GpuTjMax;
0324     uint8_t                             GpuTjHyst;
0325
0326     uint16_t                            BootVddc;
0327     uint16_t                            BootVddci;
0328
0329     uint16_t                            BootMVdd;
0330     uint16_t                            padding;
0331
0332     uint32_t                            BAPM_TEMP_GRADIENT;
0333
0334     uint32_t                            LowSclkInterruptThreshold;
0335     uint32_t                            VddGfxReChkWait;
0336
0337     uint16_t                            PPM_PkgPwrLimit;
0338     uint16_t                            PPM_TemperatureLimit;
0339
0340     uint16_t                            DefaultTdp;
0341     uint16_t                            TargetTdp;
0342 };
0343
0344 typedef struct SMU71_Discrete_DpmTable SMU71_Discrete_DpmTable;
0345
0346 // --------------------------------------------------- AC Timing Parameters ------------------------------------------------
0347 #define SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
0348 #define SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU71_MAX_LEVELS_MEMORY
0349
0350 struct SMU71_Discrete_MCRegisterAddress
0351 {
0352     uint16_t s0;
0353     uint16_t s1;
0354 };
0355
0356 typedef struct SMU71_Discrete_MCRegisterAddress SMU71_Discrete_MCRegisterAddress;
0357
0358 struct SMU71_Discrete_MCRegisterSet
0359 {
0360     uint32_t value[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0361 };
0362
0363 typedef struct SMU71_Discrete_MCRegisterSet SMU71_Discrete_MCRegisterSet;
0364
0365 struct SMU71_Discrete_MCRegisters
0366 {
0367     uint8_t                             last;
0368     uint8_t                             reserved[3];
0369     SMU71_Discrete_MCRegisterAddress     address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
0370     SMU71_Discrete_MCRegisterSet         data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
0371 };
0372
0373 typedef struct SMU71_Discrete_MCRegisters SMU71_Discrete_MCRegisters;
0374
0375
0376 // --------------------------------------------------- Fan Table -----------------------------------------------------------
0377 struct SMU71_Discrete_FanTable
0378 {
0379     uint16_t FdoMode;
0380     int16_t  TempMin;
0381     int16_t  TempMed;
0382     int16_t  TempMax;
0383     int16_t  Slope1;
0384     int16_t  Slope2;
0385     int16_t  FdoMin;
0386     int16_t  HystUp;
0387     int16_t  HystDown;
0388     int16_t  HystSlope;
0389     int16_t  TempRespLim;
0390     int16_t  TempCurr;
0391     int16_t  SlopeCurr;
0392     int16_t  PwmCurr;
0393     uint32_t RefreshPeriod;
0394     int16_t  FdoMax;
0395     uint8_t  TempSrc;
0396     int8_t   Padding;
0397 };
0398
0399 typedef struct SMU71_Discrete_FanTable SMU71_Discrete_FanTable;
0400
0401 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG             4
0402 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT         (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
0403
0404 struct SMU71_MclkDpmScoreboard
0405 {
0406
0407     uint32_t PercentageBusy;
0408
0409     int32_t  PIDError;
0410     int32_t  PIDIntegral;
0411     int32_t  PIDOutput;
0412
0413     uint32_t SigmaDeltaAccum;
0414     uint32_t SigmaDeltaOutput;
0415     uint32_t SigmaDeltaLevel;
0416
0417     uint32_t UtilizationSetpoint;
0418
0419     uint8_t  TdpClampMode;
0420     uint8_t  TdcClampMode;
0421     uint8_t  ThermClampMode;
0422     uint8_t  VoltageBusy;
0423
0424     int8_t   CurrLevel;
0425     int8_t   TargLevel;
0426     uint8_t  LevelChangeInProgress;
0427     uint8_t  UpHyst;
0428
0429     uint8_t  DownHyst;
0430     uint8_t  VoltageDownHyst;
0431     uint8_t  DpmEnable;
0432     uint8_t  DpmRunning;
0433
0434     uint8_t  DpmForce;
0435     uint8_t  DpmForceLevel;
0436     uint8_t  DisplayWatermark;
0437     uint8_t  McArbIndex;
0438
0439     uint32_t MinimumPerfMclk;
0440
0441     uint8_t  AcpiReq;
0442     uint8_t  AcpiAck;
0443     uint8_t  MclkSwitchInProgress;
0444     uint8_t  MclkSwitchCritical;
0445
0446     uint8_t  TargetMclkIndex;
0447     uint8_t  TargetMvddIndex;
0448     uint8_t  MclkSwitchResult;
0449
0450     uint8_t  EnabledLevelsChange;
0451
0452     uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_MEMORY];
0453     uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_MEMORY];
0454
0455     void     (*TargetStateCalculator)(uint8_t);
0456     void     (*SavedTargetStateCalculator)(uint8_t);
0457
0458     uint16_t AutoDpmInterval;
0459     uint16_t AutoDpmRange;
0460
0461     uint16_t  MclkSwitchingTime;
0462     uint8_t padding[2];
0463 };
0464
0465 typedef struct SMU71_MclkDpmScoreboard SMU71_MclkDpmScoreboard;
0466
0467 struct SMU71_UlvScoreboard
0468 {
0469     uint8_t     EnterUlv;
0470     uint8_t     ExitUlv;
0471     uint8_t     UlvActive;
0472     uint8_t     WaitingForUlv;
0473     uint8_t     UlvEnable;
0474     uint8_t     UlvRunning;
0475     uint8_t     UlvMasterEnable;
0476     uint8_t     padding;
0477     uint32_t    UlvAbortedCount;
0478     uint32_t    UlvTimeStamp;
0479 };
0480
0481 typedef struct SMU71_UlvScoreboard SMU71_UlvScoreboard;
0482
0483 struct SMU71_VddGfxScoreboard
0484 {
0485     uint8_t     VddGfxEnable;
0486     uint8_t     VddGfxActive;
0487     uint8_t     padding[2];
0488
0489     uint32_t    VddGfxEnteredCount;
0490     uint32_t    VddGfxAbortedCount;
0491 };
0492
0493 typedef struct SMU71_VddGfxScoreboard SMU71_VddGfxScoreboard;
0494
0495 struct SMU71_AcpiScoreboard {
0496   uint32_t SavedInterruptMask[2];
0497   uint8_t LastACPIRequest;
0498   uint8_t CgBifResp;
0499   uint8_t RequestType;
0500   uint8_t Padding;
0501   SMU71_Discrete_ACPILevel D0Level;
0502 };
0503
0504 typedef struct SMU71_AcpiScoreboard SMU71_AcpiScoreboard;
0505
0506
0507 struct SMU71_Discrete_PmFuses {
0508   // dw0-dw1
0509   uint8_t BapmVddCVidHiSidd[8];
0510
0511   // dw2-dw3
0512   uint8_t BapmVddCVidLoSidd[8];
0513
0514   // dw4-dw5
0515   uint8_t VddCVid[8];
0516
0517   // dw6
0518   uint8_t SviLoadLineEn;
0519   uint8_t SviLoadLineVddC;
0520   uint8_t SviLoadLineTrimVddC;
0521   uint8_t SviLoadLineOffsetVddC;
0522
0523   // dw7
0524   uint16_t TDC_VDDC_PkgLimit;
0525   uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
0526   uint8_t TDC_MAWt;
0527
0528   // dw8
0529   uint8_t TdcWaterfallCtl;
0530   uint8_t LPMLTemperatureMin;
0531   uint8_t LPMLTemperatureMax;
0532   uint8_t Reserved;
0533
0534   // dw9-dw12
0535   uint8_t LPMLTemperatureScaler[16];
0536
0537   // dw13-dw14
0538   int16_t FuzzyFan_ErrorSetDelta;
0539   int16_t FuzzyFan_ErrorRateSetDelta;
0540   int16_t FuzzyFan_PwmSetDelta;
0541   uint16_t Reserved6;
0542
0543   // dw15
0544   uint8_t GnbLPML[16];
0545
0546   // dw15
0547   uint8_t GnbLPMLMaxVid;
0548   uint8_t GnbLPMLMinVid;
0549   uint8_t Reserved1[2];
0550
0551   // dw16
0552   uint16_t BapmVddCBaseLeakageHiSidd;
0553   uint16_t BapmVddCBaseLeakageLoSidd;
0554 };
0555
0556 typedef struct SMU71_Discrete_PmFuses SMU71_Discrete_PmFuses;
0557
0558 struct SMU71_Discrete_Log_Header_Table {
0559   uint32_t    version;
0560   uint32_t    asic_id;
0561   uint16_t    flags;
0562   uint16_t    entry_size;
0563   uint32_t    total_size;
0564   uint32_t    num_of_entries;
0565   uint8_t     type;
0566   uint8_t     mode;
0567   uint8_t     filler_0[2];
0568   uint32_t    filler_1[2];
0569 };
0570
0571 typedef struct SMU71_Discrete_Log_Header_Table SMU71_Discrete_Log_Header_Table;
0572
0573 struct SMU71_Discrete_Log_Cntl {
0574     uint8_t             Enabled;
0575     uint8_t             Type;
0576     uint8_t             padding[2];
0577     uint32_t            BufferSize;
0578     uint32_t            SamplesLogged;
0579     uint32_t            SampleSize;
0580     uint32_t            AddrL;
0581     uint32_t            AddrH;
0582 };
0583
0584 typedef struct SMU71_Discrete_Log_Cntl SMU71_Discrete_Log_Cntl;
0585
0586 #if defined SMU__DGPU_ONLY
0587   #define CAC_ACC_NW_NUM_OF_SIGNALS 83
0588 #endif
0589
0590
0591 struct SMU71_Discrete_Cac_Collection_Table {
0592   uint32_t temperature;
0593   uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
0594   uint32_t filler[4];
0595 };
0596
0597 typedef struct SMU71_Discrete_Cac_Collection_Table SMU71_Discrete_Cac_Collection_Table;
0598
0599 struct SMU71_Discrete_Cac_Verification_Table {
0600   uint32_t VddcTotalPower;
0601   uint32_t VddcLeakagePower;
0602   uint32_t VddcConstantPower;
0603   uint32_t VddcGfxDynamicPower;
0604   uint32_t VddcUvdDynamicPower;
0605   uint32_t VddcVceDynamicPower;
0606   uint32_t VddcAcpDynamicPower;
0607   uint32_t VddcPcieDynamicPower;
0608   uint32_t VddcDceDynamicPower;
0609   uint32_t VddcCurrent;
0610   uint32_t VddcVoltage;
0611   uint32_t VddciTotalPower;
0612   uint32_t VddciLeakagePower;
0613   uint32_t VddciConstantPower;
0614   uint32_t VddciDynamicPower;
0615   uint32_t Vddr1TotalPower;
0616   uint32_t Vddr1LeakagePower;
0617   uint32_t Vddr1ConstantPower;
0618   uint32_t Vddr1DynamicPower;
0619   uint32_t spare[8];
0620   uint32_t temperature;
0621 };
0622
0623 typedef struct SMU71_Discrete_Cac_Verification_Table SMU71_Discrete_Cac_Verification_Table;
0624
0625 #if !defined(SMC_MICROCODE)
0626 #pragma pack(pop)
0627 #endif
0628
0629
0630 #endif
0631