powerplay/inc/smu71.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef SMU71_H
0024 #define SMU71_H
0025
0026 #if !defined(SMC_MICROCODE)
0027 #pragma pack(push, 1)
0028 #endif
0029
0030 #define SMU__NUM_PCIE_DPM_LEVELS 8
0031 #define SMU__NUM_SCLK_DPM_STATE 8
0032 #define SMU__NUM_MCLK_DPM_LEVELS 4
0033 #define SMU__VARIANT__ICELAND 1
0034 #define SMU__DGPU_ONLY 1
0035 #define SMU__DYNAMIC_MCARB_SETTINGS 1
0036
0037 enum SID_OPTION {
0038   SID_OPTION_HI,
0039   SID_OPTION_LO,
0040   SID_OPTION_COUNT
0041 };
0042
0043 typedef struct {
0044   uint32_t high;
0045   uint32_t low;
0046 } data_64_t;
0047
0048 typedef struct {
0049   data_64_t high;
0050   data_64_t low;
0051 } data_128_t;
0052
0053 #define SMU7_CONTEXT_ID_SMC        1
0054 #define SMU7_CONTEXT_ID_VBIOS      2
0055
0056 #define SMU71_MAX_LEVELS_VDDC            8
0057 #define SMU71_MAX_LEVELS_VDDCI           4
0058 #define SMU71_MAX_LEVELS_MVDD            4
0059 #define SMU71_MAX_LEVELS_VDDNB           8
0060
0061 #define SMU71_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE
0062 #define SMU71_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS
0063 #define SMU71_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS
0064 #define SMU71_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS
0065 #define SMU71_MAX_ENTRIES_SMIO           32
0066
0067 #define DPM_NO_LIMIT 0
0068 #define DPM_NO_UP 1
0069 #define DPM_GO_DOWN 2
0070 #define DPM_GO_UP 3
0071
0072 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
0073 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
0074
0075 #define GPIO_CLAMP_MODE_VRHOT      1
0076 #define GPIO_CLAMP_MODE_THERM      2
0077 #define GPIO_CLAMP_MODE_DC         4
0078
0079 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
0080 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
0081 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
0082 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
0083 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
0084 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
0085 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
0086 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
0087 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
0088 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
0089 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
0090 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
0091 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
0092 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
0093 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
0094 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
0095 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
0096 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
0097 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
0098 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
0099
0100
0101 #if defined SMU__DGPU_ONLY
0102 #define SMU71_DTE_ITERATIONS 5
0103 #define SMU71_DTE_SOURCES 3
0104 #define SMU71_DTE_SINKS 1
0105 #define SMU71_NUM_CPU_TES 0
0106 #define SMU71_NUM_GPU_TES 1
0107 #define SMU71_NUM_NON_TES 2
0108
0109 #endif
0110
0111 #if defined SMU__FUSION_ONLY
0112 #define SMU7_DTE_ITERATIONS 5
0113 #define SMU7_DTE_SOURCES 5
0114 #define SMU7_DTE_SINKS 3
0115 #define SMU7_NUM_CPU_TES 2
0116 #define SMU7_NUM_GPU_TES 1
0117 #define SMU7_NUM_NON_TES 2
0118
0119 #endif
0120
0121 struct SMU71_PIDController
0122 {
0123     uint32_t Ki;
0124     int32_t LFWindupUpperLim;
0125     int32_t LFWindupLowerLim;
0126     uint32_t StatePrecision;
0127     uint32_t LfPrecision;
0128     uint32_t LfOffset;
0129     uint32_t MaxState;
0130     uint32_t MaxLfFraction;
0131     uint32_t StateShift;
0132 };
0133
0134 typedef struct SMU71_PIDController SMU71_PIDController;
0135
0136 struct SMU7_LocalDpmScoreboard
0137 {
0138     uint32_t PercentageBusy;
0139
0140     int32_t  PIDError;
0141     int32_t  PIDIntegral;
0142     int32_t  PIDOutput;
0143
0144     uint32_t SigmaDeltaAccum;
0145     uint32_t SigmaDeltaOutput;
0146     uint32_t SigmaDeltaLevel;
0147
0148     uint32_t UtilizationSetpoint;
0149
0150     uint8_t  TdpClampMode;
0151     uint8_t  TdcClampMode;
0152     uint8_t  ThermClampMode;
0153     uint8_t  VoltageBusy;
0154
0155     int8_t   CurrLevel;
0156     int8_t   TargLevel;
0157     uint8_t  LevelChangeInProgress;
0158     uint8_t  UpHyst;
0159
0160     uint8_t  DownHyst;
0161     uint8_t  VoltageDownHyst;
0162     uint8_t  DpmEnable;
0163     uint8_t  DpmRunning;
0164
0165     uint8_t  DpmForce;
0166     uint8_t  DpmForceLevel;
0167     uint8_t  DisplayWatermark;
0168     uint8_t  McArbIndex;
0169
0170     uint32_t MinimumPerfSclk;
0171
0172     uint8_t  AcpiReq;
0173     uint8_t  AcpiAck;
0174     uint8_t  GfxClkSlow;
0175     uint8_t  GpioClampMode;
0176
0177     uint8_t  FpsFilterWeight;
0178     uint8_t  EnabledLevelsChange;
0179     uint8_t  DteClampMode;
0180     uint8_t  FpsClampMode;
0181
0182     uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_GRAPHICS];
0183     uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_GRAPHICS];
0184
0185     void     (*TargetStateCalculator)(uint8_t);
0186     void     (*SavedTargetStateCalculator)(uint8_t);
0187
0188     uint16_t AutoDpmInterval;
0189     uint16_t AutoDpmRange;
0190
0191     uint8_t  FpsEnabled;
0192     uint8_t  MaxPerfLevel;
0193     uint8_t  AllowLowClkInterruptToHost;
0194     uint8_t  FpsRunning;
0195
0196     uint32_t MaxAllowedFrequency;
0197 };
0198
0199 typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
0200
0201 #define SMU7_MAX_VOLTAGE_CLIENTS 12
0202
0203 struct SMU7_VoltageScoreboard
0204 {
0205     uint16_t CurrentVoltage;
0206     uint16_t HighestVoltage;
0207     uint16_t MaxVid;
0208     uint8_t  HighestVidOffset;
0209     uint8_t  CurrentVidOffset;
0210 #if defined (SMU__DGPU_ONLY)
0211     uint8_t  CurrentPhases;
0212     uint8_t  HighestPhases;
0213 #else
0214     uint8_t  AvsOffset;
0215     uint8_t  AvsOffsetApplied;
0216 #endif
0217     uint8_t  ControllerBusy;
0218     uint8_t  CurrentVid;
0219     uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
0220 #if defined (SMU__DGPU_ONLY)
0221     uint8_t  RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];
0222 #endif
0223     uint8_t  EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
0224     uint8_t  TargetIndex;
0225     uint8_t  Delay;
0226     uint8_t  ControllerEnable;
0227     uint8_t  ControllerRunning;
0228     uint16_t CurrentStdVoltageHiSidd;
0229     uint16_t CurrentStdVoltageLoSidd;
0230 #if defined (SMU__DGPU_ONLY)
0231     uint16_t RequestedVddci;
0232     uint16_t CurrentVddci;
0233     uint16_t HighestVddci;
0234     uint8_t  CurrentVddciVid;
0235     uint8_t  TargetVddciIndex;
0236 #endif
0237 };
0238
0239 typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
0240
0241 // -------------------------------------------------------------------------------------------------------------------------
0242 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
0243
0244 struct SMU7_PCIeLinkSpeedScoreboard
0245 {
0246     uint8_t     DpmEnable;
0247     uint8_t     DpmRunning;
0248     uint8_t     DpmForce;
0249     uint8_t     DpmForceLevel;
0250
0251     uint8_t     CurrentLinkSpeed;
0252     uint8_t     EnabledLevelsChange;
0253     uint16_t    AutoDpmInterval;
0254
0255     uint16_t    AutoDpmRange;
0256     uint16_t    AutoDpmCount;
0257
0258     uint8_t     DpmMode;
0259     uint8_t     AcpiReq;
0260     uint8_t     AcpiAck;
0261     uint8_t     CurrentLinkLevel;
0262
0263 };
0264
0265 typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
0266
0267 // -------------------------------------------------------- CAC table ------------------------------------------------------
0268 #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
0269 #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
0270
0271 #define SMU7_SCALE_I  7
0272 #define SMU7_SCALE_R 12
0273
0274 struct SMU7_PowerScoreboard
0275 {
0276     uint16_t   MinVoltage;
0277     uint16_t   MaxVoltage;
0278
0279     uint32_t   AvgGpuPower;
0280
0281     uint16_t   VddcLeakagePower[SID_OPTION_COUNT];
0282     uint16_t   VddcSclkConstantPower[SID_OPTION_COUNT];
0283     uint16_t   VddcSclkDynamicPower[SID_OPTION_COUNT];
0284     uint16_t   VddcNonSclkDynamicPower[SID_OPTION_COUNT];
0285     uint16_t   VddcTotalPower[SID_OPTION_COUNT];
0286     uint16_t   VddcTotalCurrent[SID_OPTION_COUNT];
0287     uint16_t   VddcLoadVoltage[SID_OPTION_COUNT];
0288     uint16_t   VddcNoLoadVoltage[SID_OPTION_COUNT];
0289
0290     uint16_t   DisplayPhyPower;
0291     uint16_t   PciePhyPower;
0292
0293     uint16_t   VddciTotalPower;
0294     uint16_t   Vddr1TotalPower;
0295
0296     uint32_t   RocPower;
0297
0298     uint32_t   last_power;
0299     uint32_t   enableWinAvg;
0300
0301     uint32_t   lkg_acc;
0302     uint16_t   VoltLkgeScaler;
0303     uint16_t   TempLkgeScaler;
0304
0305     uint32_t   uvd_cac_dclk;
0306     uint32_t   uvd_cac_vclk;
0307     uint32_t   vce_cac_eclk;
0308     uint32_t   samu_cac_samclk;
0309     uint32_t   display_cac_dispclk;
0310     uint32_t   acp_cac_aclk;
0311     uint32_t   unb_cac;
0312
0313     uint32_t   WinTime;
0314
0315     uint16_t  GpuPwr_MAWt;
0316     uint16_t  FilteredVddcTotalPower;
0317
0318     uint8_t   CalculationRepeats;
0319     uint8_t   WaterfallUp;
0320     uint8_t   WaterfallDown;
0321     uint8_t   WaterfallLimit;
0322 };
0323
0324 typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
0325
0326 // --------------------------------------------------------------------------------------------------
0327
0328 struct SMU7_ThermalScoreboard
0329 {
0330    int16_t  GpuLimit;
0331    int16_t  GpuHyst;
0332    uint16_t CurrGnbTemp;
0333    uint16_t FilteredGnbTemp;
0334    uint8_t  ControllerEnable;
0335    uint8_t  ControllerRunning;
0336    uint8_t  WaterfallUp;
0337    uint8_t  WaterfallDown;
0338    uint8_t  WaterfallLimit;
0339    uint8_t  padding[3];
0340 };
0341
0342 typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
0343
0344 // For FeatureEnables:
0345 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
0346 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
0347 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
0348 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
0349 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
0350 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
0351 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
0352 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
0353 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
0354
0355 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
0356 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
0357 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
0358 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
0359 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
0360 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
0361
0362 // All 'soft registers' should be uint32_t.
0363 struct SMU71_SoftRegisters
0364 {
0365     uint32_t        RefClockFrequency;
0366     uint32_t        PmTimerPeriod;
0367     uint32_t        FeatureEnables;
0368 #if defined (SMU__DGPU_ONLY)
0369     uint32_t        PreVBlankGap;
0370     uint32_t        VBlankTimeout;
0371     uint32_t        TrainTimeGap;
0372     uint32_t        MvddSwitchTime;
0373     uint32_t        LongestAcpiTrainTime;
0374     uint32_t        AcpiDelay;
0375     uint32_t        G5TrainTime;
0376     uint32_t        DelayMpllPwron;
0377     uint32_t        VoltageChangeTimeout;
0378 #endif
0379     uint32_t        HandshakeDisables;
0380
0381     uint8_t         DisplayPhy1Config;
0382     uint8_t         DisplayPhy2Config;
0383     uint8_t         DisplayPhy3Config;
0384     uint8_t         DisplayPhy4Config;
0385
0386     uint8_t         DisplayPhy5Config;
0387     uint8_t         DisplayPhy6Config;
0388     uint8_t         DisplayPhy7Config;
0389     uint8_t         DisplayPhy8Config;
0390
0391     uint32_t        AverageGraphicsActivity;
0392     uint32_t        AverageMemoryActivity;
0393     uint32_t        AverageGioActivity;
0394
0395     uint8_t         SClkDpmEnabledLevels;
0396     uint8_t         MClkDpmEnabledLevels;
0397     uint8_t         LClkDpmEnabledLevels;
0398     uint8_t         PCIeDpmEnabledLevels;
0399
0400     uint32_t        DRAM_LOG_ADDR_H;
0401     uint32_t        DRAM_LOG_ADDR_L;
0402     uint32_t        DRAM_LOG_PHY_ADDR_H;
0403     uint32_t        DRAM_LOG_PHY_ADDR_L;
0404     uint32_t        DRAM_LOG_BUFF_SIZE;
0405     uint32_t        UlvEnterCount;
0406     uint32_t        UlvTime;
0407     uint32_t        UcodeLoadStatus;
0408     uint8_t         DPMFreezeAndForced;
0409     uint8_t         Activity_Weight;
0410     uint8_t         Reserved8[2];
0411     uint32_t        Reserved;
0412 };
0413
0414 typedef struct SMU71_SoftRegisters SMU71_SoftRegisters;
0415
0416 struct SMU71_Firmware_Header
0417 {
0418     uint32_t Digest[5];
0419     uint32_t Version;
0420     uint32_t HeaderSize;
0421     uint32_t Flags;
0422     uint32_t EntryPoint;
0423     uint32_t CodeSize;
0424     uint32_t ImageSize;
0425
0426     uint32_t Rtos;
0427     uint32_t SoftRegisters;
0428     uint32_t DpmTable;
0429     uint32_t FanTable;
0430     uint32_t CacConfigTable;
0431     uint32_t CacStatusTable;
0432
0433     uint32_t mcRegisterTable;
0434
0435     uint32_t mcArbDramTimingTable;
0436
0437     uint32_t PmFuseTable;
0438     uint32_t Globals;
0439     uint32_t UvdDpmTable;
0440     uint32_t AcpDpmTable;
0441     uint32_t VceDpmTable;
0442     uint32_t SamuDpmTable;
0443     uint32_t UlvSettings;
0444     uint32_t Reserved[37];
0445     uint32_t Signature;
0446 };
0447
0448 typedef struct SMU71_Firmware_Header SMU71_Firmware_Header;
0449
0450 struct SMU7_HystController_Data
0451 {
0452     uint8_t waterfall_up;
0453     uint8_t waterfall_down;
0454     uint8_t pstate;
0455     uint8_t clamp_mode;
0456 };
0457
0458 typedef struct SMU7_HystController_Data SMU7_HystController_Data;
0459
0460 #define SMU71_FIRMWARE_HEADER_LOCATION 0x20000
0461
0462 enum  DisplayConfig {
0463     PowerDown = 1,
0464     DP54x4,
0465     DP54x2,
0466     DP54x1,
0467     DP27x4,
0468     DP27x2,
0469     DP27x1,
0470     HDMI297,
0471     HDMI162,
0472     LVDS,
0473     DP324x4,
0474     DP324x2,
0475     DP324x1
0476 };
0477
0478 //#define SX_BLOCK_COUNT 8
0479 //#define MC_BLOCK_COUNT 1
0480 //#define CPL_BLOCK_COUNT 27
0481
0482 #if defined SMU__VARIANT__ICELAND
0483   #define SX_BLOCK_COUNT 8
0484   #define MC_BLOCK_COUNT 1
0485   #define CPL_BLOCK_COUNT 29
0486 #endif
0487
0488 struct SMU7_Local_Cac {
0489   uint8_t BlockId;
0490   uint8_t SignalId;
0491   uint8_t Threshold;
0492   uint8_t Padding;
0493 };
0494
0495 typedef struct SMU7_Local_Cac SMU7_Local_Cac;
0496
0497 struct SMU7_Local_Cac_Table {
0498   SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT];
0499   SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
0500   SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
0501 };
0502
0503 typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
0504
0505 #if !defined(SMC_MICROCODE)
0506 #pragma pack(pop)
0507 #endif
0508
0509 #endif
0510