powerplay/inc/smu7.h

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU7_H
0025 #define SMU7_H
0026
0027 #pragma pack(push, 1)
0028
0029 #define SMU7_CONTEXT_ID_SMC        1
0030 #define SMU7_CONTEXT_ID_VBIOS      2
0031
0032
0033 #define SMU7_CONTEXT_ID_SMC        1
0034 #define SMU7_CONTEXT_ID_VBIOS      2
0035
0036 #define SMU7_MAX_LEVELS_VDDC            8
0037 #define SMU7_MAX_LEVELS_VDDCI           4
0038 #define SMU7_MAX_LEVELS_MVDD            4
0039 #define SMU7_MAX_LEVELS_VDDNB           8
0040
0041 #define SMU7_MAX_LEVELS_GRAPHICS        SMU__NUM_SCLK_DPM_STATE   // SCLK + SQ DPM + ULV
0042 #define SMU7_MAX_LEVELS_MEMORY          SMU__NUM_MCLK_DPM_LEVELS   // MCLK Levels DPM
0043 #define SMU7_MAX_LEVELS_GIO             SMU__NUM_LCLK_DPM_LEVELS  // LCLK Levels
0044 #define SMU7_MAX_LEVELS_LINK            SMU__NUM_PCIE_DPM_LEVELS  // PCIe speed and number of lanes.
0045 #define SMU7_MAX_LEVELS_UVD             8   // VCLK/DCLK levels for UVD.
0046 #define SMU7_MAX_LEVELS_VCE             8   // ECLK levels for VCE.
0047 #define SMU7_MAX_LEVELS_ACP             8   // ACLK levels for ACP.
0048 #define SMU7_MAX_LEVELS_SAMU            8   // SAMCLK levels for SAMU.
0049 #define SMU7_MAX_ENTRIES_SMIO           32  // Number of entries in SMIO table.
0050
0051 #define DPM_NO_LIMIT 0
0052 #define DPM_NO_UP 1
0053 #define DPM_GO_DOWN 2
0054 #define DPM_GO_UP 3
0055
0056 #define SMU7_FIRST_DPM_GRAPHICS_LEVEL    0
0057 #define SMU7_FIRST_DPM_MEMORY_LEVEL      0
0058
0059 #define GPIO_CLAMP_MODE_VRHOT      1
0060 #define GPIO_CLAMP_MODE_THERM      2
0061 #define GPIO_CLAMP_MODE_DC         4
0062
0063 #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
0064 #define SCRATCH_B_TARG_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
0065 #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
0066 #define SCRATCH_B_CURR_PCIE_INDEX_MASK  (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
0067 #define SCRATCH_B_TARG_UVD_INDEX_SHIFT  6
0068 #define SCRATCH_B_TARG_UVD_INDEX_MASK   (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
0069 #define SCRATCH_B_CURR_UVD_INDEX_SHIFT  9
0070 #define SCRATCH_B_CURR_UVD_INDEX_MASK   (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
0071 #define SCRATCH_B_TARG_VCE_INDEX_SHIFT  12
0072 #define SCRATCH_B_TARG_VCE_INDEX_MASK   (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
0073 #define SCRATCH_B_CURR_VCE_INDEX_SHIFT  15
0074 #define SCRATCH_B_CURR_VCE_INDEX_MASK   (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
0075 #define SCRATCH_B_TARG_ACP_INDEX_SHIFT  18
0076 #define SCRATCH_B_TARG_ACP_INDEX_MASK   (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
0077 #define SCRATCH_B_CURR_ACP_INDEX_SHIFT  21
0078 #define SCRATCH_B_CURR_ACP_INDEX_MASK   (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
0079 #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
0080 #define SCRATCH_B_TARG_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
0081 #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
0082 #define SCRATCH_B_CURR_SAMU_INDEX_MASK  (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
0083
0084
0085 /* Voltage Regulator Configuration */
0086 /* VR Config info is contained in dpmTable */
0087
0088 #define VRCONF_VDDC_MASK         0x000000FF
0089 #define VRCONF_VDDC_SHIFT        0
0090 #define VRCONF_VDDGFX_MASK       0x0000FF00
0091 #define VRCONF_VDDGFX_SHIFT      8
0092 #define VRCONF_VDDCI_MASK        0x00FF0000
0093 #define VRCONF_VDDCI_SHIFT       16
0094 #define VRCONF_MVDD_MASK         0xFF000000
0095 #define VRCONF_MVDD_SHIFT        24
0096
0097 #define VR_MERGED_WITH_VDDC      0
0098 #define VR_SVI2_PLANE_1          1
0099 #define VR_SVI2_PLANE_2          2
0100 #define VR_SMIO_PATTERN_1        3
0101 #define VR_SMIO_PATTERN_2        4
0102 #define VR_STATIC_VOLTAGE        5
0103
0104 struct SMU7_PIDController
0105 {
0106     uint32_t Ki;
0107     int32_t LFWindupUL;
0108     int32_t LFWindupLL;
0109     uint32_t StatePrecision;
0110     uint32_t LfPrecision;
0111     uint32_t LfOffset;
0112     uint32_t MaxState;
0113     uint32_t MaxLfFraction;
0114     uint32_t StateShift;
0115 };
0116
0117 typedef struct SMU7_PIDController SMU7_PIDController;
0118
0119 // -------------------------------------------------------------------------------------------------------------------------
0120 #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
0121
0122 #define SMU7_SCLK_DPM_CONFIG_MASK                        0x01
0123 #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK              0x02
0124 #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK              0x04
0125 #define SMU7_MCLK_DPM_CONFIG_MASK                        0x08
0126 #define SMU7_UVD_DPM_CONFIG_MASK                         0x10
0127 #define SMU7_VCE_DPM_CONFIG_MASK                         0x20
0128 #define SMU7_ACP_DPM_CONFIG_MASK                         0x40
0129 #define SMU7_SAMU_DPM_CONFIG_MASK                        0x80
0130 #define SMU7_PCIEGEN_DPM_CONFIG_MASK                    0x100
0131
0132 #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE                  0x00000001
0133 #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE                  0x00000002
0134 #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE                  0x00000100
0135 #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE                  0x00000200
0136 #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE                  0x00010000
0137 #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE                  0x00020000
0138
0139 struct SMU7_Firmware_Header
0140 {
0141     uint32_t Digest[5];
0142     uint32_t Version;
0143     uint32_t HeaderSize;
0144     uint32_t Flags;
0145     uint32_t EntryPoint;
0146     uint32_t CodeSize;
0147     uint32_t ImageSize;
0148
0149     uint32_t Rtos;
0150     uint32_t SoftRegisters;
0151     uint32_t DpmTable;
0152     uint32_t FanTable;
0153     uint32_t CacConfigTable;
0154     uint32_t CacStatusTable;
0155
0156     uint32_t mcRegisterTable;
0157
0158     uint32_t mcArbDramTimingTable;
0159
0160     uint32_t PmFuseTable;
0161     uint32_t Globals;
0162     uint32_t Reserved[42];
0163     uint32_t Signature;
0164 };
0165
0166 typedef struct SMU7_Firmware_Header SMU7_Firmware_Header;
0167
0168 #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000
0169
0170 enum  DisplayConfig {
0171     PowerDown = 1,
0172     DP54x4,
0173     DP54x2,
0174     DP54x1,
0175     DP27x4,
0176     DP27x2,
0177     DP27x1,
0178     HDMI297,
0179     HDMI162,
0180     LVDS,
0181     DP324x4,
0182     DP324x2,
0183     DP324x1
0184 };
0185
0186 #pragma pack(pop)
0187
0188 #endif
0189