powerplay/inc/smu11_driver_if.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU11_DRIVER_IF_H
0025 #define SMU11_DRIVER_IF_H
0026
0027 // *** IMPORTANT ***
0028 // SMU TEAM: Always increment the interface version if
0029 // any structure is changed in this file
0030 // Be aware of that the version should be updated in
0031 // smu_v11_0.h, rename is also needed.
0032 // #define SMU11_DRIVER_IF_VERSION 0x13
0033
0034 #define PPTABLE_V20_SMU_VERSION 3
0035
0036 #define NUM_GFXCLK_DPM_LEVELS  16
0037 #define NUM_VCLK_DPM_LEVELS    8
0038 #define NUM_DCLK_DPM_LEVELS    8
0039 #define NUM_ECLK_DPM_LEVELS    8
0040 #define NUM_MP0CLK_DPM_LEVELS  2
0041 #define NUM_SOCCLK_DPM_LEVELS  8
0042 #define NUM_UCLK_DPM_LEVELS    4
0043 #define NUM_FCLK_DPM_LEVELS    8
0044 #define NUM_DCEFCLK_DPM_LEVELS 8
0045 #define NUM_DISPCLK_DPM_LEVELS 8
0046 #define NUM_PIXCLK_DPM_LEVELS  8
0047 #define NUM_PHYCLK_DPM_LEVELS  8
0048 #define NUM_LINK_LEVELS        2
0049 #define NUM_XGMI_LEVELS        2
0050
0051 #define MAX_GFXCLK_DPM_LEVEL  (NUM_GFXCLK_DPM_LEVELS  - 1)
0052 #define MAX_VCLK_DPM_LEVEL    (NUM_VCLK_DPM_LEVELS    - 1)
0053 #define MAX_DCLK_DPM_LEVEL    (NUM_DCLK_DPM_LEVELS    - 1)
0054 #define MAX_ECLK_DPM_LEVEL    (NUM_ECLK_DPM_LEVELS    - 1)
0055 #define MAX_MP0CLK_DPM_LEVEL  (NUM_MP0CLK_DPM_LEVELS  - 1)
0056 #define MAX_SOCCLK_DPM_LEVEL  (NUM_SOCCLK_DPM_LEVELS  - 1)
0057 #define MAX_UCLK_DPM_LEVEL    (NUM_UCLK_DPM_LEVELS    - 1)
0058 #define MAX_FCLK_DPM_LEVEL    (NUM_FCLK_DPM_LEVELS    - 1)
0059 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
0060 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
0061 #define MAX_PIXCLK_DPM_LEVEL  (NUM_PIXCLK_DPM_LEVELS  - 1)
0062 #define MAX_PHYCLK_DPM_LEVEL  (NUM_PHYCLK_DPM_LEVELS  - 1)
0063 #define MAX_LINK_LEVEL        (NUM_LINK_LEVELS        - 1)
0064 #define MAX_XGMI_LEVEL        (NUM_XGMI_LEVELS        - 1)
0065
0066 #define PPSMC_GeminiModeNone   0
0067 #define PPSMC_GeminiModeMaster 1
0068 #define PPSMC_GeminiModeSlave  2
0069
0070
0071 #define FEATURE_DPM_PREFETCHER_BIT      0
0072 #define FEATURE_DPM_GFXCLK_BIT          1
0073 #define FEATURE_DPM_UCLK_BIT            2
0074 #define FEATURE_DPM_SOCCLK_BIT          3
0075 #define FEATURE_DPM_UVD_BIT             4
0076 #define FEATURE_DPM_VCE_BIT             5
0077 #define FEATURE_ULV_BIT                 6
0078 #define FEATURE_DPM_MP0CLK_BIT          7
0079 #define FEATURE_DPM_LINK_BIT            8
0080 #define FEATURE_DPM_DCEFCLK_BIT         9
0081 #define FEATURE_DS_GFXCLK_BIT           10
0082 #define FEATURE_DS_SOCCLK_BIT           11
0083 #define FEATURE_DS_LCLK_BIT             12
0084 #define FEATURE_PPT_BIT                 13
0085 #define FEATURE_TDC_BIT                 14
0086 #define FEATURE_THERMAL_BIT             15
0087 #define FEATURE_GFX_PER_CU_CG_BIT       16
0088 #define FEATURE_RM_BIT                  17
0089 #define FEATURE_DS_DCEFCLK_BIT          18
0090 #define FEATURE_ACDC_BIT                19
0091 #define FEATURE_VR0HOT_BIT              20
0092 #define FEATURE_VR1HOT_BIT              21
0093 #define FEATURE_FW_CTF_BIT              22
0094 #define FEATURE_LED_DISPLAY_BIT         23
0095 #define FEATURE_FAN_CONTROL_BIT         24
0096 #define FEATURE_GFX_EDC_BIT             25
0097 #define FEATURE_GFXOFF_BIT              26
0098 #define FEATURE_CG_BIT                  27
0099 #define FEATURE_DPM_FCLK_BIT            28
0100 #define FEATURE_DS_FCLK_BIT             29
0101 #define FEATURE_DS_MP1CLK_BIT           30
0102 #define FEATURE_DS_MP0CLK_BIT           31
0103 #define FEATURE_XGMI_BIT                32
0104 #define FEATURE_ECC_BIT                 33
0105 #define FEATURE_SPARE_34_BIT            34
0106 #define FEATURE_SPARE_35_BIT            35
0107 #define FEATURE_SPARE_36_BIT            36
0108 #define FEATURE_SPARE_37_BIT            37
0109 #define FEATURE_SPARE_38_BIT            38
0110 #define FEATURE_SPARE_39_BIT            39
0111 #define FEATURE_SPARE_40_BIT            40
0112 #define FEATURE_SPARE_41_BIT            41
0113 #define FEATURE_SPARE_42_BIT            42
0114 #define FEATURE_SPARE_43_BIT            43
0115 #define FEATURE_SPARE_44_BIT            44
0116 #define FEATURE_SPARE_45_BIT            45
0117 #define FEATURE_SPARE_46_BIT            46
0118 #define FEATURE_SPARE_47_BIT            47
0119 #define FEATURE_SPARE_48_BIT            48
0120 #define FEATURE_SPARE_49_BIT            49
0121 #define FEATURE_SPARE_50_BIT            50
0122 #define FEATURE_SPARE_51_BIT            51
0123 #define FEATURE_SPARE_52_BIT            52
0124 #define FEATURE_SPARE_53_BIT            53
0125 #define FEATURE_SPARE_54_BIT            54
0126 #define FEATURE_SPARE_55_BIT            55
0127 #define FEATURE_SPARE_56_BIT            56
0128 #define FEATURE_SPARE_57_BIT            57
0129 #define FEATURE_SPARE_58_BIT            58
0130 #define FEATURE_SPARE_59_BIT            59
0131 #define FEATURE_SPARE_60_BIT            60
0132 #define FEATURE_SPARE_61_BIT            61
0133 #define FEATURE_SPARE_62_BIT            62
0134 #define FEATURE_SPARE_63_BIT            63
0135
0136 #define NUM_FEATURES                    64
0137
0138 #define FEATURE_DPM_PREFETCHER_MASK     (1 << FEATURE_DPM_PREFETCHER_BIT     )
0139 #define FEATURE_DPM_GFXCLK_MASK         (1 << FEATURE_DPM_GFXCLK_BIT         )
0140 #define FEATURE_DPM_UCLK_MASK           (1 << FEATURE_DPM_UCLK_BIT           )
0141 #define FEATURE_DPM_SOCCLK_MASK         (1 << FEATURE_DPM_SOCCLK_BIT         )
0142 #define FEATURE_DPM_UVD_MASK            (1 << FEATURE_DPM_UVD_BIT            )
0143 #define FEATURE_DPM_VCE_MASK            (1 << FEATURE_DPM_VCE_BIT            )
0144 #define FEATURE_ULV_MASK                (1 << FEATURE_ULV_BIT                )
0145 #define FEATURE_DPM_MP0CLK_MASK         (1 << FEATURE_DPM_MP0CLK_BIT         )
0146 #define FEATURE_DPM_LINK_MASK           (1 << FEATURE_DPM_LINK_BIT           )
0147 #define FEATURE_DPM_DCEFCLK_MASK        (1 << FEATURE_DPM_DCEFCLK_BIT        )
0148 #define FEATURE_DS_GFXCLK_MASK          (1 << FEATURE_DS_GFXCLK_BIT          )
0149 #define FEATURE_DS_SOCCLK_MASK          (1 << FEATURE_DS_SOCCLK_BIT          )
0150 #define FEATURE_DS_LCLK_MASK            (1 << FEATURE_DS_LCLK_BIT            )
0151 #define FEATURE_PPT_MASK                (1 << FEATURE_PPT_BIT                )
0152 #define FEATURE_TDC_MASK                (1 << FEATURE_TDC_BIT                )
0153 #define FEATURE_THERMAL_MASK            (1 << FEATURE_THERMAL_BIT            )
0154 #define FEATURE_GFX_PER_CU_CG_MASK      (1 << FEATURE_GFX_PER_CU_CG_BIT      )
0155 #define FEATURE_RM_MASK                 (1 << FEATURE_RM_BIT                 )
0156 #define FEATURE_DS_DCEFCLK_MASK         (1 << FEATURE_DS_DCEFCLK_BIT         )
0157 #define FEATURE_ACDC_MASK               (1 << FEATURE_ACDC_BIT               )
0158 #define FEATURE_VR0HOT_MASK             (1 << FEATURE_VR0HOT_BIT             )
0159 #define FEATURE_VR1HOT_MASK             (1 << FEATURE_VR1HOT_BIT             )
0160 #define FEATURE_FW_CTF_MASK             (1 << FEATURE_FW_CTF_BIT             )
0161 #define FEATURE_LED_DISPLAY_MASK        (1 << FEATURE_LED_DISPLAY_BIT        )
0162 #define FEATURE_FAN_CONTROL_MASK        (1 << FEATURE_FAN_CONTROL_BIT        )
0163 #define FEATURE_GFX_EDC_MASK            (1 << FEATURE_GFX_EDC_BIT            )
0164 #define FEATURE_GFXOFF_MASK             (1 << FEATURE_GFXOFF_BIT             )
0165 #define FEATURE_CG_MASK                 (1 << FEATURE_CG_BIT                 )
0166 #define FEATURE_DPM_FCLK_MASK           (1 << FEATURE_DPM_FCLK_BIT           )
0167 #define FEATURE_DS_FCLK_MASK            (1 << FEATURE_DS_FCLK_BIT            )
0168 #define FEATURE_DS_MP1CLK_MASK          (1 << FEATURE_DS_MP1CLK_BIT          )
0169 #define FEATURE_DS_MP0CLK_MASK          (1 << FEATURE_DS_MP0CLK_BIT          )
0170 #define FEATURE_XGMI_MASK               (1ULL << FEATURE_XGMI_BIT               )
0171 #define FEATURE_ECC_MASK                (1ULL << FEATURE_ECC_BIT                )
0172
0173 #define DPM_OVERRIDE_DISABLE_SOCCLK_PID             0x00000001
0174 #define DPM_OVERRIDE_DISABLE_UCLK_PID               0x00000002
0175 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK    0x00000004
0176 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK      0x00000008
0177 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK   0x00000010
0178 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK     0x00000020
0179 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK   0x00000040
0180 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK     0x00000080
0181 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK    0x00000100
0182 #define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK      0x00000200
0183 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK   0x00000400
0184 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK     0x00000800
0185 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK 0x00001000
0186 #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK   0x00002000
0187 #define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH    0x00004000
0188 #define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH    0x00008000
0189 #define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH      0x00010000
0190 #define DPM_OVERRIDE_ENABLE_GFXOFF_FCLK_SWITCH      0x00020000
0191
0192 #define I2C_CONTROLLER_ENABLED     1
0193 #define I2C_CONTROLLER_DISABLED    0
0194
0195 #define VR_MAPPING_VR_SELECT_MASK  0x01
0196 #define VR_MAPPING_VR_SELECT_SHIFT 0x00
0197
0198 #define VR_MAPPING_PLANE_SELECT_MASK  0x02
0199 #define VR_MAPPING_PLANE_SELECT_SHIFT 0x01
0200
0201
0202 #define PSI_SEL_VR0_PLANE0_PSI0  0x01
0203 #define PSI_SEL_VR0_PLANE0_PSI1  0x02
0204 #define PSI_SEL_VR0_PLANE1_PSI0  0x04
0205 #define PSI_SEL_VR0_PLANE1_PSI1  0x08
0206 #define PSI_SEL_VR1_PLANE0_PSI0  0x10
0207 #define PSI_SEL_VR1_PLANE0_PSI1  0x20
0208 #define PSI_SEL_VR1_PLANE1_PSI0  0x40
0209 #define PSI_SEL_VR1_PLANE1_PSI1  0x80
0210
0211
0212 #define THROTTLER_STATUS_PADDING_BIT      0
0213 #define THROTTLER_STATUS_TEMP_EDGE_BIT    1
0214 #define THROTTLER_STATUS_TEMP_HOTSPOT_BIT 2
0215 #define THROTTLER_STATUS_TEMP_HBM_BIT     3
0216 #define THROTTLER_STATUS_TEMP_VR_GFX_BIT  4
0217 #define THROTTLER_STATUS_TEMP_VR_SOC_BIT  5
0218 #define THROTTLER_STATUS_TEMP_VR_MEM0_BIT 6
0219 #define THROTTLER_STATUS_TEMP_VR_MEM1_BIT 7
0220 #define THROTTLER_STATUS_TEMP_LIQUID_BIT  8
0221 #define THROTTLER_STATUS_TEMP_PLX_BIT     9
0222 #define THROTTLER_STATUS_TEMP_SKIN_BIT    10
0223 #define THROTTLER_STATUS_TDC_GFX_BIT      11
0224 #define THROTTLER_STATUS_TDC_SOC_BIT      12
0225 #define THROTTLER_STATUS_PPT_BIT          13
0226 #define THROTTLER_STATUS_FIT_BIT          14
0227 #define THROTTLER_STATUS_PPM_BIT          15
0228
0229
0230 #define TABLE_TRANSFER_OK         0x0
0231 #define TABLE_TRANSFER_FAILED     0xFF
0232
0233
0234 #define WORKLOAD_DEFAULT_BIT              0
0235 #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
0236 #define WORKLOAD_PPLIB_POWER_SAVING_BIT   2
0237 #define WORKLOAD_PPLIB_VIDEO_BIT          3
0238 #define WORKLOAD_PPLIB_VR_BIT             4
0239 #define WORKLOAD_PPLIB_COMPUTE_BIT        5
0240 #define WORKLOAD_PPLIB_CUSTOM_BIT         6
0241 #define WORKLOAD_PPLIB_COUNT              7
0242
0243
0244 #define XGMI_STATE_D0 1
0245 #define XGMI_STATE_D3 0
0246
0247 typedef enum {
0248   I2C_CONTROLLER_PORT_0 = 0,
0249   I2C_CONTROLLER_PORT_1 = 1,
0250 } I2cControllerPort_e;
0251
0252 typedef enum {
0253   I2C_CONTROLLER_NAME_VR_GFX = 0,
0254   I2C_CONTROLLER_NAME_VR_SOC,
0255   I2C_CONTROLLER_NAME_VR_VDDCI,
0256   I2C_CONTROLLER_NAME_VR_HBM,
0257   I2C_CONTROLLER_NAME_LIQUID_0,
0258   I2C_CONTROLLER_NAME_LIQUID_1,
0259   I2C_CONTROLLER_NAME_PLX,
0260   I2C_CONTROLLER_NAME_COUNT,
0261 } I2cControllerName_e;
0262
0263 typedef enum {
0264   I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0,
0265   I2C_CONTROLLER_THROTTLER_VR_GFX,
0266   I2C_CONTROLLER_THROTTLER_VR_SOC,
0267   I2C_CONTROLLER_THROTTLER_VR_VDDCI,
0268   I2C_CONTROLLER_THROTTLER_VR_HBM,
0269   I2C_CONTROLLER_THROTTLER_LIQUID_0,
0270   I2C_CONTROLLER_THROTTLER_LIQUID_1,
0271   I2C_CONTROLLER_THROTTLER_PLX,
0272 } I2cControllerThrottler_e;
0273
0274 typedef enum {
0275   I2C_CONTROLLER_PROTOCOL_VR_XPDE132G5,
0276   I2C_CONTROLLER_PROTOCOL_VR_IR35217,
0277   I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
0278   I2C_CONTROLLER_PROTOCOL_SPARE_0,
0279   I2C_CONTROLLER_PROTOCOL_SPARE_1,
0280   I2C_CONTROLLER_PROTOCOL_SPARE_2,
0281 } I2cControllerProtocol_e;
0282
0283 typedef enum {
0284   I2C_CONTROLLER_SPEED_SLOW = 0,
0285   I2C_CONTROLLER_SPEED_FAST = 1,
0286 } I2cControllerSpeed_e;
0287
0288 typedef struct {
0289   uint32_t Enabled;
0290   uint32_t SlaveAddress;
0291   uint32_t ControllerPort;
0292   uint32_t ControllerName;
0293
0294   uint32_t ThermalThrottler;
0295   uint32_t I2cProtocol;
0296   uint32_t I2cSpeed;
0297 } I2cControllerConfig_t;
0298
0299 typedef struct {
0300   uint32_t a;
0301   uint32_t b;
0302   uint32_t c;
0303 } QuadraticInt_t;
0304
0305 typedef struct {
0306   uint32_t m;
0307   uint32_t b;
0308 } LinearInt_t;
0309
0310 typedef struct {
0311   uint32_t a;
0312   uint32_t b;
0313   uint32_t c;
0314 } DroopInt_t;
0315
0316 typedef enum {
0317   PPCLK_GFXCLK,
0318   PPCLK_VCLK,
0319   PPCLK_DCLK,
0320   PPCLK_ECLK,
0321   PPCLK_SOCCLK,
0322   PPCLK_UCLK,
0323   PPCLK_DCEFCLK,
0324   PPCLK_DISPCLK,
0325   PPCLK_PIXCLK,
0326   PPCLK_PHYCLK,
0327   PPCLK_FCLK,
0328   PPCLK_COUNT,
0329 } PPCLK_e;
0330
0331 typedef enum {
0332   POWER_SOURCE_AC,
0333   POWER_SOURCE_DC,
0334   POWER_SOURCE_COUNT,
0335 } POWER_SOURCE_e;
0336
0337 typedef enum {
0338   VOLTAGE_MODE_AVFS = 0,
0339   VOLTAGE_MODE_AVFS_SS,
0340   VOLTAGE_MODE_SS,
0341   VOLTAGE_MODE_COUNT,
0342 } VOLTAGE_MODE_e;
0343
0344
0345 typedef enum {
0346   AVFS_VOLTAGE_GFX = 0,
0347   AVFS_VOLTAGE_SOC,
0348   AVFS_VOLTAGE_COUNT,
0349 } AVFS_VOLTAGE_TYPE_e;
0350
0351
0352 typedef struct {
0353   uint8_t        VoltageMode;
0354   uint8_t        SnapToDiscrete;
0355   uint8_t        NumDiscreteLevels;
0356   uint8_t        padding;
0357   LinearInt_t    ConversionToAvfsClk;
0358   QuadraticInt_t SsCurve;
0359 } DpmDescriptor_t;
0360
0361 typedef struct {
0362   uint32_t Version;
0363
0364
0365   uint32_t FeaturesToRun[2];
0366
0367
0368   uint16_t SocketPowerLimitAc0;
0369   uint16_t SocketPowerLimitAc0Tau;
0370   uint16_t SocketPowerLimitAc1;
0371   uint16_t SocketPowerLimitAc1Tau;
0372   uint16_t SocketPowerLimitAc2;
0373   uint16_t SocketPowerLimitAc2Tau;
0374   uint16_t SocketPowerLimitAc3;
0375   uint16_t SocketPowerLimitAc3Tau;
0376   uint16_t SocketPowerLimitDc;
0377   uint16_t SocketPowerLimitDcTau;
0378   uint16_t TdcLimitSoc;
0379   uint16_t TdcLimitSocTau;
0380   uint16_t TdcLimitGfx;
0381   uint16_t TdcLimitGfxTau;
0382
0383   uint16_t TedgeLimit;
0384   uint16_t ThotspotLimit;
0385   uint16_t ThbmLimit;
0386   uint16_t Tvr_gfxLimit;
0387   uint16_t Tvr_memLimit;
0388   uint16_t Tliquid1Limit;
0389   uint16_t Tliquid2Limit;
0390   uint16_t TplxLimit;
0391   uint32_t FitLimit;
0392
0393   uint16_t PpmPowerLimit;
0394   uint16_t PpmTemperatureThreshold;
0395
0396   uint8_t  MemoryOnPackage;
0397   uint8_t  padding8_limits;
0398   uint16_t Tvr_SocLimit;
0399
0400   uint16_t  UlvVoltageOffsetSoc;
0401   uint16_t  UlvVoltageOffsetGfx;
0402
0403   uint8_t  UlvSmnclkDid;
0404   uint8_t  UlvMp1clkDid;
0405   uint8_t  UlvGfxclkBypass;
0406   uint8_t  Padding234;
0407
0408
0409   uint16_t     MinVoltageGfx;
0410   uint16_t     MinVoltageSoc;
0411   uint16_t     MaxVoltageGfx;
0412   uint16_t     MaxVoltageSoc;
0413
0414   uint16_t     LoadLineResistanceGfx;
0415   uint16_t     LoadLineResistanceSoc;
0416
0417   DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
0418
0419   uint16_t       FreqTableGfx      [NUM_GFXCLK_DPM_LEVELS  ];
0420   uint16_t       FreqTableVclk     [NUM_VCLK_DPM_LEVELS    ];
0421   uint16_t       FreqTableDclk     [NUM_DCLK_DPM_LEVELS    ];
0422   uint16_t       FreqTableEclk     [NUM_ECLK_DPM_LEVELS    ];
0423   uint16_t       FreqTableSocclk   [NUM_SOCCLK_DPM_LEVELS  ];
0424   uint16_t       FreqTableUclk     [NUM_UCLK_DPM_LEVELS    ];
0425   uint16_t       FreqTableFclk     [NUM_FCLK_DPM_LEVELS    ];
0426   uint16_t       FreqTableDcefclk  [NUM_DCEFCLK_DPM_LEVELS ];
0427   uint16_t       FreqTableDispclk  [NUM_DISPCLK_DPM_LEVELS ];
0428   uint16_t       FreqTablePixclk   [NUM_PIXCLK_DPM_LEVELS  ];
0429   uint16_t       FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ];
0430
0431   uint16_t       DcModeMaxFreq     [PPCLK_COUNT            ];
0432   uint16_t       Padding8_Clks;
0433
0434   uint16_t       Mp0clkFreq        [NUM_MP0CLK_DPM_LEVELS];
0435   uint16_t       Mp0DpmVoltage     [NUM_MP0CLK_DPM_LEVELS];
0436
0437
0438   uint16_t        GfxclkFidle;
0439   uint16_t        GfxclkSlewRate;
0440   uint16_t        CksEnableFreq;
0441   uint16_t        Padding789;
0442   QuadraticInt_t  CksVoltageOffset;
0443   uint8_t         Padding567[4];
0444   uint16_t        GfxclkDsMaxFreq;
0445   uint8_t         GfxclkSource;
0446   uint8_t         Padding456;
0447
0448   uint8_t      LowestUclkReservedForUlv;
0449   uint8_t      Padding8_Uclk[3];
0450
0451
0452   uint8_t      PcieGenSpeed[NUM_LINK_LEVELS];
0453   uint8_t      PcieLaneCount[NUM_LINK_LEVELS];
0454   uint16_t     LclkFreq[NUM_LINK_LEVELS];
0455
0456
0457   uint16_t     EnableTdpm;
0458   uint16_t     TdpmHighHystTemperature;
0459   uint16_t     TdpmLowHystTemperature;
0460   uint16_t     GfxclkFreqHighTempLimit;
0461
0462
0463   uint16_t     FanStopTemp;
0464   uint16_t     FanStartTemp;
0465
0466   uint16_t     FanGainEdge;
0467   uint16_t     FanGainHotspot;
0468   uint16_t     FanGainLiquid;
0469   uint16_t     FanGainVrGfx;
0470   uint16_t     FanGainVrSoc;
0471   uint16_t     FanGainPlx;
0472   uint16_t     FanGainHbm;
0473   uint16_t     FanPwmMin;
0474   uint16_t     FanAcousticLimitRpm;
0475   uint16_t     FanThrottlingRpm;
0476   uint16_t     FanMaximumRpm;
0477   uint16_t     FanTargetTemperature;
0478   uint16_t     FanTargetGfxclk;
0479   uint8_t      FanZeroRpmEnable;
0480   uint8_t      FanTachEdgePerRev;
0481
0482
0483
0484   int16_t      FuzzyFan_ErrorSetDelta;
0485   int16_t      FuzzyFan_ErrorRateSetDelta;
0486   int16_t      FuzzyFan_PwmSetDelta;
0487   uint16_t     FuzzyFan_Reserved;
0488
0489
0490   uint8_t           OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
0491   uint8_t           Padding8_Avfs[2];
0492
0493   QuadraticInt_t    qAvfsGb[AVFS_VOLTAGE_COUNT];
0494   DroopInt_t        dBtcGbGfxCksOn;
0495   DroopInt_t        dBtcGbGfxCksOff;
0496   DroopInt_t        dBtcGbGfxAfll;
0497   DroopInt_t        dBtcGbSoc;
0498   LinearInt_t       qAgingGb[AVFS_VOLTAGE_COUNT];
0499
0500   QuadraticInt_t    qStaticVoltageOffset[AVFS_VOLTAGE_COUNT];
0501
0502   uint16_t          DcTol[AVFS_VOLTAGE_COUNT];
0503
0504   uint8_t           DcBtcEnabled[AVFS_VOLTAGE_COUNT];
0505   uint8_t           Padding8_GfxBtc[2];
0506
0507   int16_t           DcBtcMin[AVFS_VOLTAGE_COUNT];
0508   uint16_t          DcBtcMax[AVFS_VOLTAGE_COUNT];
0509
0510
0511   uint8_t           XgmiLinkSpeed   [NUM_XGMI_LEVELS];
0512   uint8_t           XgmiLinkWidth   [NUM_XGMI_LEVELS];
0513   uint16_t          XgmiFclkFreq    [NUM_XGMI_LEVELS];
0514   uint16_t          XgmiUclkFreq    [NUM_XGMI_LEVELS];
0515   uint16_t          XgmiSocclkFreq  [NUM_XGMI_LEVELS];
0516   uint16_t          XgmiSocVoltage  [NUM_XGMI_LEVELS];
0517
0518   uint32_t          DebugOverrides;
0519   QuadraticInt_t    ReservedEquation0;
0520   QuadraticInt_t    ReservedEquation1;
0521   QuadraticInt_t    ReservedEquation2;
0522   QuadraticInt_t    ReservedEquation3;
0523
0524   uint16_t     MinVoltageUlvGfx;
0525   uint16_t     MinVoltageUlvSoc;
0526
0527   uint16_t     MGpuFanBoostLimitRpm;
0528   uint16_t     padding16_Fan;
0529
0530   uint16_t     FanGainVrMem0;
0531   uint16_t     FanGainVrMem1;
0532
0533   uint16_t     DcBtcGb[AVFS_VOLTAGE_COUNT];
0534
0535   uint32_t     Reserved[11];
0536
0537   uint32_t     Padding32[3];
0538
0539   uint16_t     MaxVoltageStepGfx;
0540   uint16_t     MaxVoltageStepSoc;
0541
0542   uint8_t      VddGfxVrMapping;
0543   uint8_t      VddSocVrMapping;
0544   uint8_t      VddMem0VrMapping;
0545   uint8_t      VddMem1VrMapping;
0546
0547   uint8_t      GfxUlvPhaseSheddingMask;
0548   uint8_t      SocUlvPhaseSheddingMask;
0549   uint8_t      ExternalSensorPresent;
0550   uint8_t      Padding8_V;
0551
0552
0553   uint16_t     GfxMaxCurrent;
0554   int8_t       GfxOffset;
0555   uint8_t      Padding_TelemetryGfx;
0556
0557   uint16_t     SocMaxCurrent;
0558   int8_t       SocOffset;
0559   uint8_t      Padding_TelemetrySoc;
0560
0561   uint16_t     Mem0MaxCurrent;
0562   int8_t       Mem0Offset;
0563   uint8_t      Padding_TelemetryMem0;
0564
0565   uint16_t     Mem1MaxCurrent;
0566   int8_t       Mem1Offset;
0567   uint8_t      Padding_TelemetryMem1;
0568
0569
0570   uint8_t      AcDcGpio;
0571   uint8_t      AcDcPolarity;
0572   uint8_t      VR0HotGpio;
0573   uint8_t      VR0HotPolarity;
0574
0575   uint8_t      VR1HotGpio;
0576   uint8_t      VR1HotPolarity;
0577   uint8_t      Padding1;
0578   uint8_t      Padding2;
0579
0580
0581
0582   uint8_t      LedPin0;
0583   uint8_t      LedPin1;
0584   uint8_t      LedPin2;
0585   uint8_t      padding8_4;
0586
0587
0588   uint8_t      PllGfxclkSpreadEnabled;
0589   uint8_t      PllGfxclkSpreadPercent;
0590   uint16_t     PllGfxclkSpreadFreq;
0591
0592   uint8_t      UclkSpreadEnabled;
0593   uint8_t      UclkSpreadPercent;
0594   uint16_t     UclkSpreadFreq;
0595
0596   uint8_t      FclkSpreadEnabled;
0597   uint8_t      FclkSpreadPercent;
0598   uint16_t     FclkSpreadFreq;
0599
0600   uint8_t      FllGfxclkSpreadEnabled;
0601   uint8_t      FllGfxclkSpreadPercent;
0602   uint16_t     FllGfxclkSpreadFreq;
0603
0604   I2cControllerConfig_t I2cControllers[I2C_CONTROLLER_NAME_COUNT];
0605
0606   uint32_t     BoardReserved[10];
0607
0608
0609   uint32_t     MmHubPadding[8];
0610
0611 } PPTable_t;
0612
0613 typedef struct {
0614
0615   uint16_t     GfxclkAverageLpfTau;
0616   uint16_t     SocclkAverageLpfTau;
0617   uint16_t     UclkAverageLpfTau;
0618   uint16_t     GfxActivityLpfTau;
0619   uint16_t     UclkActivityLpfTau;
0620   uint16_t     SocketPowerLpfTau;
0621
0622
0623   uint32_t     MmHubPadding[8];
0624 } DriverSmuConfig_t;
0625
0626 typedef struct {
0627
0628   uint16_t      GfxclkFmin;
0629   uint16_t      GfxclkFmax;
0630   uint16_t      GfxclkFreq1;
0631   uint16_t      GfxclkVolt1;
0632   uint16_t      GfxclkFreq2;
0633   uint16_t      GfxclkVolt2;
0634   uint16_t      GfxclkFreq3;
0635   uint16_t      GfxclkVolt3;
0636   uint16_t      UclkFmax;
0637   int16_t       OverDrivePct;
0638   uint16_t      FanMaximumRpm;
0639   uint16_t      FanMinimumPwm;
0640   uint16_t      FanTargetTemperature;
0641   uint16_t      MaxOpTemp;
0642   uint16_t      FanZeroRpmEnable;
0643   uint16_t      Padding;
0644
0645 } OverDriveTable_t;
0646
0647 typedef struct {
0648   uint16_t CurrClock[PPCLK_COUNT];
0649   uint16_t AverageGfxclkFrequency;
0650   uint16_t AverageSocclkFrequency;
0651   uint16_t AverageUclkFrequency  ;
0652   uint16_t AverageGfxActivity    ;
0653   uint16_t AverageUclkActivity   ;
0654   uint8_t  CurrSocVoltageOffset  ;
0655   uint8_t  CurrGfxVoltageOffset  ;
0656   uint8_t  CurrMemVidOffset      ;
0657   uint8_t  Padding8              ;
0658   uint16_t CurrSocketPower       ;
0659   uint16_t TemperatureEdge       ;
0660   uint16_t TemperatureHotspot    ;
0661   uint16_t TemperatureHBM        ;
0662   uint16_t TemperatureVrGfx      ;
0663   uint16_t TemperatureVrSoc      ;
0664   uint16_t TemperatureVrMem0     ;
0665   uint16_t TemperatureVrMem1     ;
0666   uint16_t TemperatureLiquid     ;
0667   uint16_t TemperaturePlx        ;
0668   uint32_t ThrottlerStatus       ;
0669
0670   uint8_t  LinkDpmLevel;
0671   uint16_t AverageSocketPower;
0672   uint8_t  Padding;
0673
0674
0675   uint32_t     MmHubPadding[7];
0676 } SmuMetrics_t;
0677
0678 typedef struct {
0679   uint16_t MinClock;
0680   uint16_t MaxClock;
0681   uint16_t MinUclk;
0682   uint16_t MaxUclk;
0683
0684   uint8_t  WmSetting;
0685   uint8_t  Padding[3];
0686 } WatermarkRowGeneric_t;
0687
0688 #define NUM_WM_RANGES 4
0689
0690 typedef enum {
0691   WM_SOCCLK = 0,
0692   WM_DCEFCLK,
0693   WM_COUNT_PP,
0694 } WM_CLOCK_e;
0695
0696 typedef struct {
0697
0698   WatermarkRowGeneric_t WatermarkRow[WM_COUNT_PP][NUM_WM_RANGES];
0699
0700   uint32_t     MmHubPadding[7];
0701 } Watermarks_t;
0702
0703 typedef struct {
0704   uint16_t avgPsmCount[45];
0705   uint16_t minPsmCount[45];
0706   float    avgPsmVoltage[45];
0707   float    minPsmVoltage[45];
0708
0709   uint16_t avgScsPsmCount;
0710   uint16_t minScsPsmCount;
0711   float    avgScsPsmVoltage;
0712   float    minScsPsmVoltage;
0713
0714
0715   uint32_t MmHubPadding[6];
0716 } AvfsDebugTable_t;
0717
0718 typedef struct {
0719   uint8_t  AvfsVersion;
0720   uint8_t  AvfsEn[AVFS_VOLTAGE_COUNT];
0721
0722   uint8_t  OverrideVFT[AVFS_VOLTAGE_COUNT];
0723   uint8_t  OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
0724
0725   uint8_t  OverrideTemperatures[AVFS_VOLTAGE_COUNT];
0726   uint8_t  OverrideVInversion[AVFS_VOLTAGE_COUNT];
0727   uint8_t  OverrideP2V[AVFS_VOLTAGE_COUNT];
0728   uint8_t  OverrideP2VCharzFreq[AVFS_VOLTAGE_COUNT];
0729
0730   int32_t VFT0_m1[AVFS_VOLTAGE_COUNT];
0731   int32_t VFT0_m2[AVFS_VOLTAGE_COUNT];
0732   int32_t VFT0_b[AVFS_VOLTAGE_COUNT];
0733
0734   int32_t VFT1_m1[AVFS_VOLTAGE_COUNT];
0735   int32_t VFT1_m2[AVFS_VOLTAGE_COUNT];
0736   int32_t VFT1_b[AVFS_VOLTAGE_COUNT];
0737
0738   int32_t VFT2_m1[AVFS_VOLTAGE_COUNT];
0739   int32_t VFT2_m2[AVFS_VOLTAGE_COUNT];
0740   int32_t VFT2_b[AVFS_VOLTAGE_COUNT];
0741
0742   int32_t AvfsGb0_m1[AVFS_VOLTAGE_COUNT];
0743   int32_t AvfsGb0_m2[AVFS_VOLTAGE_COUNT];
0744   int32_t AvfsGb0_b[AVFS_VOLTAGE_COUNT];
0745
0746   int32_t AcBtcGb_m1[AVFS_VOLTAGE_COUNT];
0747   int32_t AcBtcGb_m2[AVFS_VOLTAGE_COUNT];
0748   int32_t AcBtcGb_b[AVFS_VOLTAGE_COUNT];
0749
0750   uint32_t AvfsTempCold[AVFS_VOLTAGE_COUNT];
0751   uint32_t AvfsTempMid[AVFS_VOLTAGE_COUNT];
0752   uint32_t AvfsTempHot[AVFS_VOLTAGE_COUNT];
0753
0754   uint32_t VInversion[AVFS_VOLTAGE_COUNT];
0755
0756
0757   int32_t P2V_m1[AVFS_VOLTAGE_COUNT];
0758   int32_t P2V_m2[AVFS_VOLTAGE_COUNT];
0759   int32_t P2V_b[AVFS_VOLTAGE_COUNT];
0760
0761   uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT];
0762
0763   uint32_t EnabledAvfsModules;
0764
0765   uint32_t MmHubPadding[7];
0766 } AvfsFuseOverride_t;
0767
0768 typedef struct {
0769
0770   uint8_t   Gfx_ActiveHystLimit;
0771   uint8_t   Gfx_IdleHystLimit;
0772   uint8_t   Gfx_FPS;
0773   uint8_t   Gfx_MinActiveFreqType;
0774   uint8_t   Gfx_BoosterFreqType;
0775   uint8_t   Gfx_UseRlcBusy;
0776   uint16_t  Gfx_MinActiveFreq;
0777   uint16_t  Gfx_BoosterFreq;
0778   uint16_t  Gfx_PD_Data_time_constant;
0779   uint32_t  Gfx_PD_Data_limit_a;
0780   uint32_t  Gfx_PD_Data_limit_b;
0781   uint32_t  Gfx_PD_Data_limit_c;
0782   uint32_t  Gfx_PD_Data_error_coeff;
0783   uint32_t  Gfx_PD_Data_error_rate_coeff;
0784
0785   uint8_t   Soc_ActiveHystLimit;
0786   uint8_t   Soc_IdleHystLimit;
0787   uint8_t   Soc_FPS;
0788   uint8_t   Soc_MinActiveFreqType;
0789   uint8_t   Soc_BoosterFreqType;
0790   uint8_t   Soc_UseRlcBusy;
0791   uint16_t  Soc_MinActiveFreq;
0792   uint16_t  Soc_BoosterFreq;
0793   uint16_t  Soc_PD_Data_time_constant;
0794   uint32_t  Soc_PD_Data_limit_a;
0795   uint32_t  Soc_PD_Data_limit_b;
0796   uint32_t  Soc_PD_Data_limit_c;
0797   uint32_t  Soc_PD_Data_error_coeff;
0798   uint32_t  Soc_PD_Data_error_rate_coeff;
0799
0800   uint8_t   Mem_ActiveHystLimit;
0801   uint8_t   Mem_IdleHystLimit;
0802   uint8_t   Mem_FPS;
0803   uint8_t   Mem_MinActiveFreqType;
0804   uint8_t   Mem_BoosterFreqType;
0805   uint8_t   Mem_UseRlcBusy;
0806   uint16_t  Mem_MinActiveFreq;
0807   uint16_t  Mem_BoosterFreq;
0808   uint16_t  Mem_PD_Data_time_constant;
0809   uint32_t  Mem_PD_Data_limit_a;
0810   uint32_t  Mem_PD_Data_limit_b;
0811   uint32_t  Mem_PD_Data_limit_c;
0812   uint32_t  Mem_PD_Data_error_coeff;
0813   uint32_t  Mem_PD_Data_error_rate_coeff;
0814
0815   uint8_t   Fclk_ActiveHystLimit;
0816   uint8_t   Fclk_IdleHystLimit;
0817   uint8_t   Fclk_FPS;
0818   uint8_t   Fclk_MinActiveFreqType;
0819   uint8_t   Fclk_BoosterFreqType;
0820   uint8_t   Fclk_UseRlcBusy;
0821   uint16_t  Fclk_MinActiveFreq;
0822   uint16_t  Fclk_BoosterFreq;
0823   uint16_t  Fclk_PD_Data_time_constant;
0824   uint32_t  Fclk_PD_Data_limit_a;
0825   uint32_t  Fclk_PD_Data_limit_b;
0826   uint32_t  Fclk_PD_Data_limit_c;
0827   uint32_t  Fclk_PD_Data_error_coeff;
0828   uint32_t  Fclk_PD_Data_error_rate_coeff;
0829
0830 } DpmActivityMonitorCoeffInt_t;
0831
0832 #define TABLE_PPTABLE                 0
0833 #define TABLE_WATERMARKS              1
0834 #define TABLE_AVFS                    2
0835 #define TABLE_AVFS_PSM_DEBUG          3
0836 #define TABLE_AVFS_FUSE_OVERRIDE      4
0837 #define TABLE_PMSTATUSLOG             5
0838 #define TABLE_SMU_METRICS             6
0839 #define TABLE_DRIVER_SMU_CONFIG       7
0840 #define TABLE_ACTIVITY_MONITOR_COEFF  8
0841 #define TABLE_OVERDRIVE               9
0842 #define TABLE_COUNT                  10
0843
0844
0845 #define UCLK_SWITCH_SLOW 0
0846 #define UCLK_SWITCH_FAST 1
0847
0848
0849 #define SQ_Enable_MASK 0x1
0850 #define SQ_IR_MASK 0x2
0851 #define SQ_PCC_MASK 0x4
0852 #define SQ_EDC_MASK 0x8
0853
0854 #define TCP_Enable_MASK 0x100
0855 #define TCP_IR_MASK 0x200
0856 #define TCP_PCC_MASK 0x400
0857 #define TCP_EDC_MASK 0x800
0858
0859 #define TD_Enable_MASK 0x10000
0860 #define TD_IR_MASK 0x20000
0861 #define TD_PCC_MASK 0x40000
0862 #define TD_EDC_MASK 0x80000
0863
0864 #define DB_Enable_MASK 0x1000000
0865 #define DB_IR_MASK 0x2000000
0866 #define DB_PCC_MASK 0x4000000
0867 #define DB_EDC_MASK 0x8000000
0868
0869 #define SQ_Enable_SHIFT 0
0870 #define SQ_IR_SHIFT 1
0871 #define SQ_PCC_SHIFT 2
0872 #define SQ_EDC_SHIFT 3
0873
0874 #define TCP_Enable_SHIFT 8
0875 #define TCP_IR_SHIFT 9
0876 #define TCP_PCC_SHIFT 10
0877 #define TCP_EDC_SHIFT 11
0878
0879 #define TD_Enable_SHIFT 16
0880 #define TD_IR_SHIFT 17
0881 #define TD_PCC_SHIFT 18
0882 #define TD_EDC_SHIFT 19
0883
0884 #define DB_Enable_SHIFT 24
0885 #define DB_IR_SHIFT 25
0886 #define DB_PCC_SHIFT 26
0887 #define DB_EDC_SHIFT 27
0888
0889 #define REMOVE_FMAX_MARGIN_BIT     0x0
0890 #define REMOVE_DCTOL_MARGIN_BIT    0x1
0891 #define REMOVE_PLATFORM_MARGIN_BIT 0x2
0892
0893 #endif