powerplay/inc/smu10_driver_if.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef SMU10_DRIVER_IF_H
0025 #define SMU10_DRIVER_IF_H
0026
0027 #define SMU10_DRIVER_IF_VERSION 0x6
0028
0029 #define NUM_DSPCLK_LEVELS 8
0030
0031 typedef struct {
0032     int32_t value;
0033     uint32_t numFractionalBits;
0034 } FloatInIntFormat_t;
0035
0036 typedef enum {
0037     DSPCLK_DCEFCLK = 0,
0038     DSPCLK_DISPCLK,
0039     DSPCLK_PIXCLK,
0040     DSPCLK_PHYCLK,
0041     DSPCLK_COUNT,
0042 } DSPCLK_e;
0043
0044 typedef struct {
0045     uint16_t Freq;
0046     uint16_t Vid;
0047 } DisplayClockTable_t;
0048
0049
0050 typedef struct {
0051     uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
0052     uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
0053     uint16_t MinMclk;
0054     uint16_t MaxMclk;
0055
0056     uint8_t  WmSetting;
0057     uint8_t  WmType;
0058     uint8_t  Padding[2];
0059 } WatermarkRowGeneric_t;
0060
0061 #define NUM_WM_RANGES 4
0062
0063 typedef enum {
0064     WM_SOCCLK = 0,
0065     WM_DCFCLK,
0066     WM_COUNT,
0067 } WM_CLOCK_e;
0068
0069 typedef struct {
0070     WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
0071     uint32_t              MmHubPadding[7];
0072 } Watermarks_t;
0073
0074 typedef enum {
0075     CUSTOM_DPM_SETTING_GFXCLK,
0076     CUSTOM_DPM_SETTING_CCLK,
0077     CUSTOM_DPM_SETTING_FCLK_CCX,
0078     CUSTOM_DPM_SETTING_FCLK_GFX,
0079     CUSTOM_DPM_SETTING_FCLK_STALLS,
0080     CUSTOM_DPM_SETTING_LCLK,
0081     CUSTOM_DPM_SETTING_COUNT,
0082 } CUSTOM_DPM_SETTING_e;
0083
0084 typedef struct {
0085     uint8_t             ActiveHystLimit;
0086     uint8_t             IdleHystLimit;
0087     uint8_t             FPS;
0088     uint8_t             MinActiveFreqType;
0089     FloatInIntFormat_t  MinActiveFreq;
0090     FloatInIntFormat_t  PD_Data_limit;
0091     FloatInIntFormat_t  PD_Data_time_constant;
0092     FloatInIntFormat_t  PD_Data_error_coeff;
0093     FloatInIntFormat_t  PD_Data_error_rate_coeff;
0094 } DpmActivityMonitorCoeffExt_t;
0095
0096 typedef struct {
0097     DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
0098 } CustomDpmSettings_t;
0099
0100 #define NUM_SOCCLK_DPM_LEVELS  8
0101 #define NUM_DCEFCLK_DPM_LEVELS 4
0102 #define NUM_FCLK_DPM_LEVELS    4
0103 #define NUM_MEMCLK_DPM_LEVELS  4
0104
0105 typedef struct {
0106     uint32_t  Freq; /* In MHz */
0107     uint32_t  Vol;  /* Millivolts with 2 fractional bits */
0108 } DpmClock_t;
0109
0110 typedef struct {
0111     DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
0112     DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
0113     DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
0114     DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
0115 } DpmClocks_t;
0116
0117 #endif