powerplay/inc/power_state.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef PP_POWERSTATE_H
0024 #define PP_POWERSTATE_H
0025
0026 struct pp_hw_power_state {
0027     unsigned int magic;
0028 };
0029
0030 struct pp_power_state;
0031
0032
0033 #define PP_INVALID_POWER_STATE_ID (0)
0034
0035
0036 /*
0037  * An item of a list containing Power States.
0038  */
0039
0040 struct PP_StateLinkedList {
0041     struct pp_power_state *next;
0042     struct pp_power_state *prev;
0043 };
0044
0045
0046 enum PP_StateUILabel {
0047     PP_StateUILabel_None,
0048     PP_StateUILabel_Battery,
0049     PP_StateUILabel_MiddleLow,
0050     PP_StateUILabel_Balanced,
0051     PP_StateUILabel_MiddleHigh,
0052     PP_StateUILabel_Performance,
0053     PP_StateUILabel_BACO
0054 };
0055
0056 enum PP_StateClassificationFlag {
0057     PP_StateClassificationFlag_Boot                = 0x0001,
0058     PP_StateClassificationFlag_Thermal             = 0x0002,
0059     PP_StateClassificationFlag_LimitedPowerSource  = 0x0004,
0060     PP_StateClassificationFlag_Rest                = 0x0008,
0061     PP_StateClassificationFlag_Forced              = 0x0010,
0062     PP_StateClassificationFlag_User3DPerformance   = 0x0020,
0063     PP_StateClassificationFlag_User2DPerformance   = 0x0040,
0064     PP_StateClassificationFlag_3DPerformance       = 0x0080,
0065     PP_StateClassificationFlag_ACOverdriveTemplate   = 0x0100,
0066     PP_StateClassificationFlag_Uvd                 = 0x0200,
0067     PP_StateClassificationFlag_3DPerformanceLow    = 0x0400,
0068     PP_StateClassificationFlag_ACPI                = 0x0800,
0069     PP_StateClassificationFlag_HD2                 = 0x1000,
0070     PP_StateClassificationFlag_UvdHD               = 0x2000,
0071     PP_StateClassificationFlag_UvdSD               = 0x4000,
0072     PP_StateClassificationFlag_UserDCPerformance    = 0x8000,
0073     PP_StateClassificationFlag_DCOverdriveTemplate   = 0x10000,
0074     PP_StateClassificationFlag_BACO                  = 0x20000,
0075     PP_StateClassificationFlag_LimitedPowerSource_2  = 0x40000,
0076     PP_StateClassificationFlag_ULV                   = 0x80000,
0077     PP_StateClassificationFlag_UvdMVC               = 0x100000,
0078 };
0079
0080 typedef unsigned int PP_StateClassificationFlags;
0081
0082 struct PP_StateClassificationBlock {
0083     enum PP_StateUILabel         ui_label;
0084     enum PP_StateClassificationFlag  flags;
0085     int                          bios_index;
0086     bool                      temporary_state;
0087     bool                      to_be_deleted;
0088 };
0089
0090 struct PP_StatePcieBlock {
0091     unsigned int lanes;
0092 };
0093
0094 enum PP_RefreshrateSource {
0095     PP_RefreshrateSource_EDID,
0096     PP_RefreshrateSource_Explicit
0097 };
0098
0099 struct PP_StateDisplayBlock {
0100     bool              disableFrameModulation;
0101     bool              limitRefreshrate;
0102     enum PP_RefreshrateSource refreshrateSource;
0103     int                  explicitRefreshrate;
0104     int                  edidRefreshrateIndex;
0105     bool              enableVariBright;
0106 };
0107
0108 struct PP_StateMemroyBlock {
0109     bool              dllOff;
0110     uint8_t                 m3arb;
0111     uint8_t                 unused[3];
0112 };
0113
0114 struct PP_StateSoftwareAlgorithmBlock {
0115     bool disableLoadBalancing;
0116     bool enableSleepForTimestamps;
0117 };
0118
0119 #define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
0120
0121 /**
0122  * Type to hold a temperature range.
0123  */
0124 struct PP_TemperatureRange {
0125     int min;
0126     int max;
0127     int edge_emergency_max;
0128     int hotspot_min;
0129     int hotspot_crit_max;
0130     int hotspot_emergency_max;
0131     int mem_min;
0132     int mem_crit_max;
0133     int mem_emergency_max;
0134 };
0135
0136 struct PP_StateValidationBlock {
0137     bool singleDisplayOnly;
0138     bool disallowOnDC;
0139     uint8_t supportedPowerLevels;
0140 };
0141
0142 struct PP_UVD_CLOCKS {
0143     uint32_t VCLK;
0144     uint32_t DCLK;
0145 };
0146
0147 /**
0148 * Structure to hold a PowerPlay Power State.
0149 */
0150 struct pp_power_state {
0151     uint32_t                            id;
0152     struct PP_StateLinkedList                  orderedList;
0153     struct PP_StateLinkedList                  allStatesList;
0154
0155     struct PP_StateClassificationBlock         classification;
0156     struct PP_StateValidationBlock             validation;
0157     struct PP_StatePcieBlock                   pcie;
0158     struct PP_StateDisplayBlock                display;
0159     struct PP_StateMemroyBlock                 memory;
0160     struct PP_TemperatureRange                 temperatures;
0161     struct PP_StateSoftwareAlgorithmBlock      software;
0162     struct PP_UVD_CLOCKS                       uvd_clocks;
0163     struct pp_hw_power_state  hardware;
0164 };
0165
0166 enum PP_MMProfilingState {
0167     PP_MMProfilingState_NA = 0,
0168     PP_MMProfilingState_Started,
0169     PP_MMProfilingState_Stopped
0170 };
0171
0172 struct pp_clock_engine_request {
0173     unsigned long client_type;
0174     unsigned long ctx_id;
0175     uint64_t  context_handle;
0176     unsigned long sclk;
0177     unsigned long sclk_hard_min;
0178     unsigned long mclk;
0179     unsigned long iclk;
0180     unsigned long evclk;
0181     unsigned long ecclk;
0182     unsigned long ecclk_hard_min;
0183     unsigned long vclk;
0184     unsigned long dclk;
0185     unsigned long sclk_over_drive;
0186     unsigned long mclk_over_drive;
0187     unsigned long sclk_threshold;
0188     unsigned long flag;
0189     unsigned long vclk_ceiling;
0190     unsigned long dclk_ceiling;
0191     unsigned long num_cus;
0192     unsigned long pm_flag;
0193     enum PP_MMProfilingState mm_profiling_state;
0194 };
0195
0196 #endif