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0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _HWMGR_H_
0024 #define _HWMGR_H_
0025 
0026 #include <linux/seq_file.h>
0027 #include "amd_powerplay.h"
0028 #include "hardwaremanager.h"
0029 #include "hwmgr_ppt.h"
0030 #include "ppatomctrl.h"
0031 #include "power_state.h"
0032 #include "smu_helper.h"
0033 
0034 struct pp_hwmgr;
0035 struct phm_fan_speed_info;
0036 struct pp_atomctrl_voltage_table;
0037 
0038 #define VOLTAGE_SCALE 4
0039 #define VOLTAGE_VID_OFFSET_SCALE1   625
0040 #define VOLTAGE_VID_OFFSET_SCALE2   100
0041 
0042 enum DISPLAY_GAP {
0043     DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */
0044     DISPLAY_GAP_VBLANK       = 1,   /* Wait for vblank. */
0045     DISPLAY_GAP_WATERMARK    = 2,   /* Wait for MCHG watermark. (Note that HW may deassert WM in VBI depending on DC_STUTTER_CNTL.) */
0046     DISPLAY_GAP_IGNORE       = 3    /* Do not wait. */
0047 };
0048 typedef enum DISPLAY_GAP DISPLAY_GAP;
0049 
0050 enum BACO_STATE {
0051     BACO_STATE_OUT = 0,
0052     BACO_STATE_IN,
0053 };
0054 
0055 struct vi_dpm_level {
0056     bool enabled;
0057     uint32_t value;
0058     uint32_t param1;
0059 };
0060 
0061 struct vi_dpm_table {
0062     uint32_t count;
0063     struct vi_dpm_level dpm_level[];
0064 };
0065 
0066 #define PCIE_PERF_REQ_REMOVE_REGISTRY   0
0067 #define PCIE_PERF_REQ_FORCE_LOWPOWER    1
0068 #define PCIE_PERF_REQ_GEN1         2
0069 #define PCIE_PERF_REQ_GEN2         3
0070 #define PCIE_PERF_REQ_GEN3         4
0071 
0072 enum PHM_BackEnd_Magic {
0073     PHM_Dummy_Magic       = 0xAA5555AA,
0074     PHM_RV770_Magic       = 0xDCBAABCD,
0075     PHM_Kong_Magic        = 0x239478DF,
0076     PHM_NIslands_Magic    = 0x736C494E,
0077     PHM_Sumo_Magic        = 0x8339FA11,
0078     PHM_SIslands_Magic    = 0x369431AC,
0079     PHM_Trinity_Magic     = 0x96751873,
0080     PHM_CIslands_Magic    = 0x38AC78B0,
0081     PHM_Kv_Magic          = 0xDCBBABC0,
0082     PHM_VIslands_Magic    = 0x20130307,
0083     PHM_Cz_Magic          = 0x67DCBA25,
0084     PHM_Rv_Magic          = 0x20161121
0085 };
0086 
0087 struct phm_set_power_state_input {
0088     const struct pp_hw_power_state *pcurrent_state;
0089     const struct pp_hw_power_state *pnew_state;
0090 };
0091 
0092 struct phm_clock_array {
0093     uint32_t count;
0094     uint32_t values[];
0095 };
0096 
0097 struct phm_clock_voltage_dependency_record {
0098     uint32_t clk;
0099     uint32_t v;
0100 };
0101 
0102 struct phm_vceclock_voltage_dependency_record {
0103     uint32_t ecclk;
0104     uint32_t evclk;
0105     uint32_t v;
0106 };
0107 
0108 struct phm_uvdclock_voltage_dependency_record {
0109     uint32_t vclk;
0110     uint32_t dclk;
0111     uint32_t v;
0112 };
0113 
0114 struct phm_samuclock_voltage_dependency_record {
0115     uint32_t samclk;
0116     uint32_t v;
0117 };
0118 
0119 struct phm_acpclock_voltage_dependency_record {
0120     uint32_t acpclk;
0121     uint32_t v;
0122 };
0123 
0124 struct phm_clock_voltage_dependency_table {
0125     uint32_t count;                         /* Number of entries. */
0126     struct phm_clock_voltage_dependency_record entries[];       /* Dynamically allocate count entries. */
0127 };
0128 
0129 struct phm_phase_shedding_limits_record {
0130     uint32_t  Voltage;
0131     uint32_t    Sclk;
0132     uint32_t    Mclk;
0133 };
0134 
0135 struct phm_uvd_clock_voltage_dependency_record {
0136     uint32_t vclk;
0137     uint32_t dclk;
0138     uint32_t v;
0139 };
0140 
0141 struct phm_uvd_clock_voltage_dependency_table {
0142     uint8_t count;
0143     struct phm_uvd_clock_voltage_dependency_record entries[];
0144 };
0145 
0146 struct phm_acp_clock_voltage_dependency_record {
0147     uint32_t acpclk;
0148     uint32_t v;
0149 };
0150 
0151 struct phm_acp_clock_voltage_dependency_table {
0152     uint32_t count;
0153     struct phm_acp_clock_voltage_dependency_record entries[];
0154 };
0155 
0156 struct phm_vce_clock_voltage_dependency_record {
0157     uint32_t ecclk;
0158     uint32_t evclk;
0159     uint32_t v;
0160 };
0161 
0162 struct phm_phase_shedding_limits_table {
0163     uint32_t                           count;
0164     struct phm_phase_shedding_limits_record  entries[];
0165 };
0166 
0167 struct phm_vceclock_voltage_dependency_table {
0168     uint8_t count;                                    /* Number of entries. */
0169     struct phm_vceclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
0170 };
0171 
0172 struct phm_uvdclock_voltage_dependency_table {
0173     uint8_t count;                                    /* Number of entries. */
0174     struct phm_uvdclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
0175 };
0176 
0177 struct phm_samuclock_voltage_dependency_table {
0178     uint8_t count;                                    /* Number of entries. */
0179     struct phm_samuclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
0180 };
0181 
0182 struct phm_acpclock_voltage_dependency_table {
0183     uint32_t count;                                    /* Number of entries. */
0184     struct phm_acpclock_voltage_dependency_record entries[1]; /* Dynamically allocate count entries. */
0185 };
0186 
0187 struct phm_vce_clock_voltage_dependency_table {
0188     uint8_t count;
0189     struct phm_vce_clock_voltage_dependency_record entries[];
0190 };
0191 
0192 
0193 enum SMU_ASIC_RESET_MODE
0194 {
0195     SMU_ASIC_RESET_MODE_0,
0196     SMU_ASIC_RESET_MODE_1,
0197     SMU_ASIC_RESET_MODE_2,
0198 };
0199 
0200 struct pp_smumgr_func {
0201     char *name;
0202     int (*smu_init)(struct pp_hwmgr  *hwmgr);
0203     int (*smu_fini)(struct pp_hwmgr  *hwmgr);
0204     int (*start_smu)(struct pp_hwmgr  *hwmgr);
0205     int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,
0206                     uint32_t firmware);
0207     int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
0208     int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
0209                         uint32_t firmware);
0210     uint32_t (*get_argument)(struct pp_hwmgr  *hwmgr);
0211     int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
0212     int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
0213                       uint16_t msg, uint32_t parameter);
0214     int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,
0215                      void **table);
0216     int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);
0217     int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
0218     int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
0219     int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
0220     int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
0221     int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
0222     int (*init_smc_table)(struct pp_hwmgr *hwmgr);
0223     int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
0224     int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
0225     int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
0226     uint32_t (*get_offsetof)(uint32_t type, uint32_t member);
0227     uint32_t (*get_mac_definition)(uint32_t value);
0228     bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
0229     bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
0230     int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
0231     int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
0232     int (*stop_smc)(struct pp_hwmgr *hwmgr);
0233 };
0234 
0235 struct pp_hwmgr_func {
0236     int (*backend_init)(struct pp_hwmgr *hw_mgr);
0237     int (*backend_fini)(struct pp_hwmgr *hw_mgr);
0238     int (*asic_setup)(struct pp_hwmgr *hw_mgr);
0239     int (*get_power_state_size)(struct pp_hwmgr *hw_mgr);
0240 
0241     int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
0242                 struct pp_power_state  *prequest_ps,
0243             const struct pp_power_state *pcurrent_ps);
0244 
0245     int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
0246 
0247     int (*force_dpm_level)(struct pp_hwmgr *hw_mgr,
0248                     enum amd_dpm_forced_level level);
0249 
0250     int (*dynamic_state_management_enable)(
0251                         struct pp_hwmgr *hw_mgr);
0252     int (*dynamic_state_management_disable)(
0253                         struct pp_hwmgr *hw_mgr);
0254 
0255     int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
0256                      struct pp_hw_power_state *hw_ps);
0257 
0258     int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
0259                 unsigned long, struct pp_power_state *);
0260     int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
0261     int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
0262     void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
0263     void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
0264     void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
0265     uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
0266     uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
0267     int (*power_state_set)(struct pp_hwmgr *hwmgr,
0268                         const void *state);
0269     int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
0270     int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
0271     int (*display_config_changed)(struct pp_hwmgr *hwmgr);
0272     int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
0273     int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
0274                         const uint32_t *msg_id);
0275     int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
0276     int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
0277     int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
0278     int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
0279     void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
0280     uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
0281     int (*set_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t speed);
0282     int (*get_fan_speed_pwm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
0283     int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t speed);
0284     int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
0285     int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
0286     int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
0287     int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
0288     bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
0289     int (*check_states_equal)(struct pp_hwmgr *hwmgr,
0290                     const struct pp_hw_power_state *pstate1,
0291                     const struct pp_hw_power_state *pstate2,
0292                     bool *equal);
0293     int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
0294     int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
0295                 bool cc6_disable, bool pstate_disable,
0296                 bool pstate_switch_disable);
0297     int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
0298             struct amd_pp_simple_clock_info *info);
0299     int (*get_performance_level)(struct pp_hwmgr *, const struct pp_hw_power_state *,
0300             PHM_PerformanceLevelDesignation, uint32_t, PHM_PerformanceLevel *);
0301     int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
0302                 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
0303     int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
0304     int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
0305             enum amd_pp_clock_type type,
0306             struct pp_clock_levels_with_latency *clocks);
0307     int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
0308             enum amd_pp_clock_type type,
0309             struct pp_clock_levels_with_voltage *clocks);
0310     int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
0311     int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
0312             struct pp_display_clock_request *clock);
0313     int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
0314     int (*power_off_asic)(struct pp_hwmgr *hwmgr);
0315     int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
0316     int (*emit_clock_levels)(struct pp_hwmgr *hwmgr,
0317                  enum pp_clock_type type, char *buf, int *offset);
0318     int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
0319     int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
0320     int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
0321     int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
0322     int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
0323     int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
0324     int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
0325     int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
0326     int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
0327     int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
0328     int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
0329     int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
0330     int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
0331                     uint32_t virtual_addr_low,
0332                     uint32_t virtual_addr_hi,
0333                     uint32_t mc_addr_low,
0334                     uint32_t mc_addr_hi,
0335                     uint32_t size);
0336     int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
0337                     struct PP_TemperatureRange *range);
0338     int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
0339     int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
0340     int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
0341                     enum PP_OD_DPM_TABLE_COMMAND type,
0342                     long *input, uint32_t size);
0343     int (*set_fine_grain_clk_vol)(struct pp_hwmgr *hwmgr,
0344                       enum PP_OD_DPM_TABLE_COMMAND type,
0345                       long *input, uint32_t size);
0346     int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
0347     int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
0348     int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
0349     int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
0350     int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
0351     int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
0352     int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
0353     int (*set_hard_min_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
0354     int (*set_soft_max_gfxclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
0355     int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
0356     int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
0357     int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
0358     int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
0359     int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
0360     int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
0361     int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
0362     int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
0363     int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
0364     int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
0365     int (*disable_power_features_for_compute_performance)(struct pp_hwmgr *hwmgr,
0366                     bool disable);
0367     ssize_t (*get_gpu_metrics)(struct pp_hwmgr *hwmgr, void **table);
0368     int (*gfx_state_change)(struct pp_hwmgr *hwmgr, uint32_t state);
0369 };
0370 
0371 struct pp_table_func {
0372     int (*pptable_init)(struct pp_hwmgr *hw_mgr);
0373     int (*pptable_fini)(struct pp_hwmgr *hw_mgr);
0374     int (*pptable_get_number_of_vce_state_table_entries)(struct pp_hwmgr *hw_mgr);
0375     int (*pptable_get_vce_state_table_entry)(
0376                         struct pp_hwmgr *hwmgr,
0377                         unsigned long i,
0378                         struct amd_vce_state *vce_state,
0379                         void **clock_info,
0380                         unsigned long *flag);
0381 };
0382 
0383 union phm_cac_leakage_record {
0384     struct {
0385         uint16_t Vddc;          /* in CI, we use it for StdVoltageHiSidd */
0386         uint32_t Leakage;       /* in CI, we use it for StdVoltageLoSidd */
0387     };
0388     struct {
0389         uint16_t Vddc1;
0390         uint16_t Vddc2;
0391         uint16_t Vddc3;
0392     };
0393 };
0394 
0395 struct phm_cac_leakage_table {
0396     uint32_t count;
0397     union phm_cac_leakage_record entries[];
0398 };
0399 
0400 struct phm_samu_clock_voltage_dependency_record {
0401     uint32_t samclk;
0402     uint32_t v;
0403 };
0404 
0405 
0406 struct phm_samu_clock_voltage_dependency_table {
0407     uint8_t count;
0408     struct phm_samu_clock_voltage_dependency_record entries[];
0409 };
0410 
0411 struct phm_cac_tdp_table {
0412     uint16_t usTDP;
0413     uint16_t usConfigurableTDP;
0414     uint16_t usTDC;
0415     uint16_t usBatteryPowerLimit;
0416     uint16_t usSmallPowerLimit;
0417     uint16_t usLowCACLeakage;
0418     uint16_t usHighCACLeakage;
0419     uint16_t usMaximumPowerDeliveryLimit;
0420     uint16_t usEDCLimit;
0421     uint16_t usOperatingTempMinLimit;
0422     uint16_t usOperatingTempMaxLimit;
0423     uint16_t usOperatingTempStep;
0424     uint16_t usOperatingTempHyst;
0425     uint16_t usDefaultTargetOperatingTemp;
0426     uint16_t usTargetOperatingTemp;
0427     uint16_t usPowerTuneDataSetID;
0428     uint16_t usSoftwareShutdownTemp;
0429     uint16_t usClockStretchAmount;
0430     uint16_t usTemperatureLimitHotspot;
0431     uint16_t usTemperatureLimitLiquid1;
0432     uint16_t usTemperatureLimitLiquid2;
0433     uint16_t usTemperatureLimitVrVddc;
0434     uint16_t usTemperatureLimitVrMvdd;
0435     uint16_t usTemperatureLimitPlx;
0436     uint8_t  ucLiquid1_I2C_address;
0437     uint8_t  ucLiquid2_I2C_address;
0438     uint8_t  ucLiquid_I2C_Line;
0439     uint8_t  ucVr_I2C_address;
0440     uint8_t  ucVr_I2C_Line;
0441     uint8_t  ucPlx_I2C_address;
0442     uint8_t  ucPlx_I2C_Line;
0443     uint32_t usBoostPowerLimit;
0444     uint8_t  ucCKS_LDO_REFSEL;
0445     uint8_t  ucHotSpotOnly;
0446 };
0447 
0448 struct phm_tdp_table {
0449     uint16_t usTDP;
0450     uint16_t usConfigurableTDP;
0451     uint16_t usTDC;
0452     uint16_t usBatteryPowerLimit;
0453     uint16_t usSmallPowerLimit;
0454     uint16_t usLowCACLeakage;
0455     uint16_t usHighCACLeakage;
0456     uint16_t usMaximumPowerDeliveryLimit;
0457     uint16_t usEDCLimit;
0458     uint16_t usOperatingTempMinLimit;
0459     uint16_t usOperatingTempMaxLimit;
0460     uint16_t usOperatingTempStep;
0461     uint16_t usOperatingTempHyst;
0462     uint16_t usDefaultTargetOperatingTemp;
0463     uint16_t usTargetOperatingTemp;
0464     uint16_t usPowerTuneDataSetID;
0465     uint16_t usSoftwareShutdownTemp;
0466     uint16_t usClockStretchAmount;
0467     uint16_t usTemperatureLimitTedge;
0468     uint16_t usTemperatureLimitHotspot;
0469     uint16_t usTemperatureLimitLiquid1;
0470     uint16_t usTemperatureLimitLiquid2;
0471     uint16_t usTemperatureLimitHBM;
0472     uint16_t usTemperatureLimitVrVddc;
0473     uint16_t usTemperatureLimitVrMvdd;
0474     uint16_t usTemperatureLimitPlx;
0475     uint8_t  ucLiquid1_I2C_address;
0476     uint8_t  ucLiquid2_I2C_address;
0477     uint8_t  ucLiquid_I2C_Line;
0478     uint8_t  ucVr_I2C_address;
0479     uint8_t  ucVr_I2C_Line;
0480     uint8_t  ucPlx_I2C_address;
0481     uint8_t  ucPlx_I2C_Line;
0482     uint8_t  ucLiquid_I2C_LineSDA;
0483     uint8_t  ucVr_I2C_LineSDA;
0484     uint8_t  ucPlx_I2C_LineSDA;
0485     uint32_t usBoostPowerLimit;
0486     uint16_t usBoostStartTemperature;
0487     uint16_t usBoostStopTemperature;
0488     uint32_t  ulBoostClock;
0489 };
0490 
0491 struct phm_ppm_table {
0492     uint8_t   ppm_design;
0493     uint16_t  cpu_core_number;
0494     uint32_t  platform_tdp;
0495     uint32_t  small_ac_platform_tdp;
0496     uint32_t  platform_tdc;
0497     uint32_t  small_ac_platform_tdc;
0498     uint32_t  apu_tdp;
0499     uint32_t  dgpu_tdp;
0500     uint32_t  dgpu_ulv_power;
0501     uint32_t  tj_max;
0502 };
0503 
0504 struct phm_vq_budgeting_record {
0505     uint32_t ulCUs;
0506     uint32_t ulSustainableSOCPowerLimitLow;
0507     uint32_t ulSustainableSOCPowerLimitHigh;
0508     uint32_t ulMinSclkLow;
0509     uint32_t ulMinSclkHigh;
0510     uint8_t  ucDispConfig;
0511     uint32_t ulDClk;
0512     uint32_t ulEClk;
0513     uint32_t ulSustainableSclk;
0514     uint32_t ulSustainableCUs;
0515 };
0516 
0517 struct phm_vq_budgeting_table {
0518     uint8_t numEntries;
0519     struct phm_vq_budgeting_record entries[1];
0520 };
0521 
0522 struct phm_clock_and_voltage_limits {
0523     uint32_t sclk;
0524     uint32_t mclk;
0525     uint32_t gfxclk;
0526     uint16_t vddc;
0527     uint16_t vddci;
0528     uint16_t vddgfx;
0529     uint16_t vddmem;
0530 };
0531 
0532 /* Structure to hold PPTable information */
0533 
0534 struct phm_ppt_v1_information {
0535     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
0536     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
0537     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
0538     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
0539     struct phm_clock_array *valid_sclk_values;
0540     struct phm_clock_array *valid_mclk_values;
0541     struct phm_clock_array *valid_socclk_values;
0542     struct phm_clock_array *valid_dcefclk_values;
0543     struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
0544     struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
0545     struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
0546     struct phm_ppm_table *ppm_parameter_table;
0547     struct phm_cac_tdp_table *cac_dtp_table;
0548     struct phm_tdp_table *tdp_table;
0549     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
0550     struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
0551     struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
0552     struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
0553     struct phm_ppt_v1_pcie_table *pcie_table;
0554     struct phm_ppt_v1_gpio_table *gpio_table;
0555     uint16_t us_ulv_voltage_offset;
0556     uint16_t us_ulv_smnclk_did;
0557     uint16_t us_ulv_mp1clk_did;
0558     uint16_t us_ulv_gfxclk_bypass;
0559     uint16_t us_gfxclk_slew_rate;
0560     uint16_t us_min_gfxclk_freq_limit;
0561 };
0562 
0563 struct phm_ppt_v2_information {
0564     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_sclk;
0565     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_mclk;
0566     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_socclk;
0567     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dcefclk;
0568     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_pixclk;
0569     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_dispclk;
0570     struct phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_on_phyclk;
0571     struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_dep_table;
0572 
0573     struct phm_clock_voltage_dependency_table *vddc_dep_on_dalpwrl;
0574 
0575     struct phm_clock_array *valid_sclk_values;
0576     struct phm_clock_array *valid_mclk_values;
0577     struct phm_clock_array *valid_socclk_values;
0578     struct phm_clock_array *valid_dcefclk_values;
0579 
0580     struct phm_clock_and_voltage_limits max_clock_voltage_on_dc;
0581     struct phm_clock_and_voltage_limits max_clock_voltage_on_ac;
0582 
0583     struct phm_ppm_table *ppm_parameter_table;
0584     struct phm_cac_tdp_table *cac_dtp_table;
0585     struct phm_tdp_table *tdp_table;
0586 
0587     struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table;
0588     struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table;
0589     struct phm_ppt_v1_voltage_lookup_table *vddmem_lookup_table;
0590     struct phm_ppt_v1_voltage_lookup_table *vddci_lookup_table;
0591 
0592     struct phm_ppt_v1_pcie_table *pcie_table;
0593 
0594     uint16_t us_ulv_voltage_offset;
0595     uint16_t us_ulv_smnclk_did;
0596     uint16_t us_ulv_mp1clk_did;
0597     uint16_t us_ulv_gfxclk_bypass;
0598     uint16_t us_gfxclk_slew_rate;
0599     uint16_t us_min_gfxclk_freq_limit;
0600 
0601     uint8_t  uc_gfx_dpm_voltage_mode;
0602     uint8_t  uc_soc_dpm_voltage_mode;
0603     uint8_t  uc_uclk_dpm_voltage_mode;
0604     uint8_t  uc_uvd_dpm_voltage_mode;
0605     uint8_t  uc_vce_dpm_voltage_mode;
0606     uint8_t  uc_mp0_dpm_voltage_mode;
0607     uint8_t  uc_dcef_dpm_voltage_mode;
0608 };
0609 
0610 struct phm_ppt_v3_information
0611 {
0612     uint8_t uc_thermal_controller_type;
0613 
0614     uint16_t us_small_power_limit1;
0615     uint16_t us_small_power_limit2;
0616     uint16_t us_boost_power_limit;
0617 
0618     uint16_t us_od_turbo_power_limit;
0619     uint16_t us_od_powersave_power_limit;
0620     uint16_t us_software_shutdown_temp;
0621 
0622     uint32_t *power_saving_clock_max;
0623     uint32_t *power_saving_clock_min;
0624 
0625     uint8_t *od_feature_capabilities;
0626     uint32_t *od_settings_max;
0627     uint32_t *od_settings_min;
0628 
0629     void *smc_pptable;
0630 };
0631 
0632 struct phm_dynamic_state_info {
0633     struct phm_clock_voltage_dependency_table *vddc_dependency_on_sclk;
0634     struct phm_clock_voltage_dependency_table *vddci_dependency_on_mclk;
0635     struct phm_clock_voltage_dependency_table *vddc_dependency_on_mclk;
0636     struct phm_clock_voltage_dependency_table *mvdd_dependency_on_mclk;
0637     struct phm_clock_voltage_dependency_table *vddc_dep_on_dal_pwrl;
0638     struct phm_clock_array                    *valid_sclk_values;
0639     struct phm_clock_array                    *valid_mclk_values;
0640     struct phm_clock_and_voltage_limits       max_clock_voltage_on_dc;
0641     struct phm_clock_and_voltage_limits       max_clock_voltage_on_ac;
0642     uint32_t                                  mclk_sclk_ratio;
0643     uint32_t                                  sclk_mclk_delta;
0644     uint32_t                                  vddc_vddci_delta;
0645     uint32_t                                  min_vddc_for_pcie_gen2;
0646     struct phm_cac_leakage_table              *cac_leakage_table;
0647     struct phm_phase_shedding_limits_table  *vddc_phase_shed_limits_table;
0648 
0649     struct phm_vce_clock_voltage_dependency_table
0650                         *vce_clock_voltage_dependency_table;
0651     struct phm_uvd_clock_voltage_dependency_table
0652                         *uvd_clock_voltage_dependency_table;
0653     struct phm_acp_clock_voltage_dependency_table
0654                         *acp_clock_voltage_dependency_table;
0655     struct phm_samu_clock_voltage_dependency_table
0656                        *samu_clock_voltage_dependency_table;
0657 
0658     struct phm_ppm_table                          *ppm_parameter_table;
0659     struct phm_cac_tdp_table                      *cac_dtp_table;
0660     struct phm_clock_voltage_dependency_table   *vdd_gfx_dependency_on_sclk;
0661 };
0662 
0663 struct pp_fan_info {
0664     bool bNoFan;
0665     uint8_t   ucTachometerPulsesPerRevolution;
0666     uint32_t   ulMinRPM;
0667     uint32_t   ulMaxRPM;
0668 };
0669 
0670 struct pp_advance_fan_control_parameters {
0671     uint16_t  usTMin;                          /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
0672     uint16_t  usTMed;                          /* The middle temperature where we change slopes. */
0673     uint16_t  usTHigh;                         /* The high temperature for setting the second slope. */
0674     uint16_t  usPWMMin;                        /* The minimum PWM value in percent (0.01% increments). */
0675     uint16_t  usPWMMed;                        /* The PWM value (in percent) at TMed. */
0676     uint16_t  usPWMHigh;                       /* The PWM value at THigh. */
0677     uint8_t   ucTHyst;                         /* Temperature hysteresis. Integer. */
0678     uint32_t   ulCycleDelay;                   /* The time between two invocations of the fan control routine in microseconds. */
0679     uint16_t  usTMax;                          /* The max temperature */
0680     uint8_t   ucFanControlMode;
0681     uint16_t  usFanPWMMinLimit;
0682     uint16_t  usFanPWMMaxLimit;
0683     uint16_t  usFanPWMStep;
0684     uint16_t  usDefaultMaxFanPWM;
0685     uint16_t  usFanOutputSensitivity;
0686     uint16_t  usDefaultFanOutputSensitivity;
0687     uint16_t  usMaxFanPWM;                     /* The max Fan PWM value for Fuzzy Fan Control feature */
0688     uint16_t  usFanRPMMinLimit;                /* Minimum limit range in percentage, need to calculate based on minRPM/MaxRpm */
0689     uint16_t  usFanRPMMaxLimit;                /* Maximum limit range in percentage, usually set to 100% by default */
0690     uint16_t  usFanRPMStep;                    /* Step increments/decerements, in percent */
0691     uint16_t  usDefaultMaxFanRPM;              /* The max Fan RPM value for Fuzzy Fan Control feature, default from PPTable */
0692     uint16_t  usMaxFanRPM;                     /* The max Fan RPM value for Fuzzy Fan Control feature, user defined */
0693     uint16_t  usFanCurrentLow;                 /* Low current */
0694     uint16_t  usFanCurrentHigh;                /* High current */
0695     uint16_t  usFanRPMLow;                     /* Low RPM */
0696     uint16_t  usFanRPMHigh;                    /* High RPM */
0697     uint32_t   ulMinFanSCLKAcousticLimit;      /* Minimum Fan Controller SCLK Frequency Acoustic Limit. */
0698     uint8_t   ucTargetTemperature;             /* Advanced fan controller target temperature. */
0699     uint8_t   ucMinimumPWMLimit;               /* The minimum PWM that the advanced fan controller can set.  This should be set to the highest PWM that will run the fan at its lowest RPM. */
0700     uint16_t  usFanGainEdge;                   /* The following is added for Fiji */
0701     uint16_t  usFanGainHotspot;
0702     uint16_t  usFanGainLiquid;
0703     uint16_t  usFanGainVrVddc;
0704     uint16_t  usFanGainVrMvdd;
0705     uint16_t  usFanGainPlx;
0706     uint16_t  usFanGainHbm;
0707     uint8_t   ucEnableZeroRPM;
0708     uint8_t   ucFanStopTemperature;
0709     uint8_t   ucFanStartTemperature;
0710     uint32_t  ulMaxFanSCLKAcousticLimit;       /* Maximum Fan Controller SCLK Frequency Acoustic Limit. */
0711     uint32_t  ulTargetGfxClk;
0712     uint16_t  usZeroRPMStartTemperature;
0713     uint16_t  usZeroRPMStopTemperature;
0714     uint16_t  usMGpuThrottlingRPMLimit;
0715 };
0716 
0717 struct pp_thermal_controller_info {
0718     uint8_t ucType;
0719     uint8_t ucI2cLine;
0720     uint8_t ucI2cAddress;
0721     uint8_t use_hw_fan_control;
0722     struct pp_fan_info fanInfo;
0723     struct pp_advance_fan_control_parameters advanceFanControlParameters;
0724 };
0725 
0726 struct phm_microcode_version_info {
0727     uint32_t SMC;
0728     uint32_t DMCU;
0729     uint32_t MC;
0730     uint32_t NB;
0731 };
0732 
0733 enum PP_TABLE_VERSION {
0734     PP_TABLE_V0 = 0,
0735     PP_TABLE_V1,
0736     PP_TABLE_V2,
0737     PP_TABLE_MAX
0738 };
0739 
0740 /**
0741  * The main hardware manager structure.
0742  */
0743 #define Workload_Policy_Max 6
0744 
0745 struct pp_hwmgr {
0746     void *adev;
0747     uint32_t chip_family;
0748     uint32_t chip_id;
0749     uint32_t smu_version;
0750     bool not_vf;
0751     bool pm_en;
0752     bool pp_one_vf;
0753     struct mutex msg_lock;
0754 
0755     uint32_t pp_table_version;
0756     void *device;
0757     struct pp_smumgr *smumgr;
0758     const void *soft_pp_table;
0759     uint32_t soft_pp_table_size;
0760     void *hardcode_pp_table;
0761     bool need_pp_table_upload;
0762 
0763     struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
0764     uint32_t num_vce_state_tables;
0765 
0766     enum amd_dpm_forced_level dpm_level;
0767     enum amd_dpm_forced_level saved_dpm_level;
0768     enum amd_dpm_forced_level request_dpm_level;
0769     uint32_t usec_timeout;
0770     void *pptable;
0771     struct phm_platform_descriptor platform_descriptor;
0772     void *backend;
0773 
0774     void *smu_backend;
0775     const struct pp_smumgr_func *smumgr_funcs;
0776     bool is_kicker;
0777 
0778     enum PP_DAL_POWERLEVEL dal_power_level;
0779     struct phm_dynamic_state_info dyn_state;
0780     const struct pp_hwmgr_func *hwmgr_func;
0781     const struct pp_table_func *pptable_func;
0782 
0783     struct pp_power_state    *ps;
0784     uint32_t num_ps;
0785     struct pp_thermal_controller_info thermal_controller;
0786     bool fan_ctrl_is_in_default_mode;
0787     uint32_t fan_ctrl_default_mode;
0788     bool fan_ctrl_enabled;
0789     uint32_t tmin;
0790     struct phm_microcode_version_info microcode_version_info;
0791     uint32_t ps_size;
0792     struct pp_power_state    *current_ps;
0793     struct pp_power_state    *request_ps;
0794     struct pp_power_state    *boot_ps;
0795     struct pp_power_state    *uvd_ps;
0796     const struct amd_pp_display_configuration *display_config;
0797     uint32_t feature_mask;
0798     bool avfs_supported;
0799     /* UMD Pstate */
0800     bool en_umd_pstate;
0801     uint32_t power_profile_mode;
0802     uint32_t default_power_profile_mode;
0803     uint32_t pstate_sclk;
0804     uint32_t pstate_mclk;
0805     bool od_enabled;
0806     uint32_t power_limit;
0807     uint32_t default_power_limit;
0808     uint32_t workload_mask;
0809     uint32_t workload_prority[Workload_Policy_Max];
0810     uint32_t workload_setting[Workload_Policy_Max];
0811     bool gfxoff_state_changed_by_workload;
0812 };
0813 
0814 int hwmgr_early_init(struct pp_hwmgr *hwmgr);
0815 int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
0816 int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
0817 int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
0818 int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
0819 int hwmgr_suspend(struct pp_hwmgr *hwmgr);
0820 int hwmgr_resume(struct pp_hwmgr *hwmgr);
0821 
0822 int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
0823                 enum amd_pp_task task_id,
0824                 enum amd_pm_state_type *user_state);
0825 
0826 
0827 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
0828 
0829 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
0830 int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
0831 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
0832 int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
0833 
0834 #endif /* _HWMGR_H_ */
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