powerplay/inc/hardwaremanager.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _HARDWARE_MANAGER_H_
0024 #define _HARDWARE_MANAGER_H_
0025
0026
0027
0028 struct pp_hwmgr;
0029 struct pp_hw_power_state;
0030 struct pp_power_state;
0031 enum amd_dpm_forced_level;
0032 struct PP_TemperatureRange;
0033
0034
0035 struct phm_fan_speed_info {
0036     uint32_t min_percent;
0037     uint32_t max_percent;
0038     uint32_t min_rpm;
0039     uint32_t max_rpm;
0040     bool supports_percent_read;
0041     bool supports_percent_write;
0042     bool supports_rpm_read;
0043     bool supports_rpm_write;
0044 };
0045
0046 /* Automatic Power State Throttling */
0047 enum PHM_AutoThrottleSource
0048 {
0049     PHM_AutoThrottleSource_Thermal,
0050     PHM_AutoThrottleSource_External
0051 };
0052
0053 typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
0054
0055 enum phm_platform_caps {
0056     PHM_PlatformCaps_AtomBiosPpV1 = 0,
0057     PHM_PlatformCaps_PowerPlaySupport,
0058     PHM_PlatformCaps_ACOverdriveSupport,
0059     PHM_PlatformCaps_BacklightSupport,
0060     PHM_PlatformCaps_ThermalController,
0061     PHM_PlatformCaps_BiosPowerSourceControl,
0062     PHM_PlatformCaps_DisableVoltageTransition,
0063     PHM_PlatformCaps_DisableEngineTransition,
0064     PHM_PlatformCaps_DisableMemoryTransition,
0065     PHM_PlatformCaps_DynamicPowerManagement,
0066     PHM_PlatformCaps_EnableASPML0s,
0067     PHM_PlatformCaps_EnableASPML1,
0068     PHM_PlatformCaps_OD5inACSupport,
0069     PHM_PlatformCaps_OD5inDCSupport,
0070     PHM_PlatformCaps_SoftStateOD5,
0071     PHM_PlatformCaps_NoOD5Support,
0072     PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
0073     PHM_PlatformCaps_ActivityReporting,
0074     PHM_PlatformCaps_EnableBackbias,
0075     PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
0076     PHM_PlatformCaps_ShowPowerBudgetWarning,
0077     PHM_PlatformCaps_PowerBudgetWaiverAvailable,
0078     PHM_PlatformCaps_GFXClockGatingSupport,
0079     PHM_PlatformCaps_MMClockGatingSupport,
0080     PHM_PlatformCaps_AutomaticDCTransition,
0081     PHM_PlatformCaps_GeminiPrimary,
0082     PHM_PlatformCaps_MemorySpreadSpectrumSupport,
0083     PHM_PlatformCaps_EngineSpreadSpectrumSupport,
0084     PHM_PlatformCaps_StepVddc,
0085     PHM_PlatformCaps_DynamicPCIEGen2Support,
0086     PHM_PlatformCaps_SMC,
0087     PHM_PlatformCaps_FaultyInternalThermalReading,          /* Internal thermal controller reports faulty temperature value when DAC2 is active */
0088     PHM_PlatformCaps_EnableVoltageControl,                  /* indicates voltage can be controlled */
0089     PHM_PlatformCaps_EnableSideportControl,                 /* indicates Sideport can be controlled */
0090     PHM_PlatformCaps_VideoPlaybackEEUNotification,          /* indicates EEU notification of video start/stop is required */
0091     PHM_PlatformCaps_TurnOffPll_ASPML1,                     /* PCIE Turn Off PLL in ASPM L1 */
0092     PHM_PlatformCaps_EnableHTLinkControl,                   /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
0093     PHM_PlatformCaps_PerformanceStateOnly,                  /* indicates only performance power state to be used on current system. */
0094     PHM_PlatformCaps_ExclusiveModeAlwaysHigh,               /* In Exclusive (3D) mode always stay in High state. */
0095     PHM_PlatformCaps_DisableMGClockGating,                  /* to disable Medium Grain Clock Gating or not */
0096     PHM_PlatformCaps_DisableMGCGTSSM,                       /* TO disable Medium Grain Clock Gating Shader Complex control */
0097     PHM_PlatformCaps_UVDAlwaysHigh,                         /* In UVD mode always stay in High state */
0098     PHM_PlatformCaps_DisablePowerGating,                    /* to disable power gating */
0099     PHM_PlatformCaps_CustomThermalPolicy,                   /* indicates only performance power state to be used on current system. */
0100     PHM_PlatformCaps_StayInBootState,                       /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
0101     PHM_PlatformCaps_SMCAllowSeparateSWThermalState,        /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
0102     PHM_PlatformCaps_MultiUVDStateSupport,                  /* Powerplay state table supports multi UVD states. */
0103     PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,             /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
0104     PHM_PlatformCaps_EnableMCUHTLinkControl,                /* Enable HT link control by MCU */
0105     PHM_PlatformCaps_ABM,                                   /* ABM support.*/
0106     PHM_PlatformCaps_KongThermalPolicy,                     /* A thermal policy specific for Kong */
0107     PHM_PlatformCaps_SwitchVDDNB,                           /* if the users want to switch VDDNB */
0108     PHM_PlatformCaps_ULPS,                                  /* support ULPS mode either through ACPI state or ULPS state */
0109     PHM_PlatformCaps_NativeULPS,                            /* hardware capable of ULPS state (other than through the ACPI state) */
0110     PHM_PlatformCaps_EnableMVDDControl,                     /* indicates that memory voltage can be controlled */
0111     PHM_PlatformCaps_ControlVDDCI,                          /* Control VDDCI separately from VDDC. */
0112     PHM_PlatformCaps_DisableDCODT,                          /* indicates if DC ODT apply or not */
0113     PHM_PlatformCaps_DynamicACTiming,                       /* if the SMC dynamically re-programs MC SEQ register values */
0114     PHM_PlatformCaps_EnableThermalIntByGPIO,                /* enable throttle control through GPIO */
0115     PHM_PlatformCaps_BootStateOnAlert,                      /* Go to boot state on alerts, e.g. on an AC->DC transition. */
0116     PHM_PlatformCaps_DontWaitForVBlankOnAlert,              /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
0117     PHM_PlatformCaps_Force3DClockSupport,                   /* indicates if the platform supports force 3D clock. */
0118     PHM_PlatformCaps_MicrocodeFanControl,                   /* Fan is controlled by the SMC microcode. */
0119     PHM_PlatformCaps_AdjustUVDPriorityForSP,
0120     PHM_PlatformCaps_DisableLightSleep,                     /* Light sleep for evergreen family. */
0121     PHM_PlatformCaps_DisableMCLS,                           /* MC Light sleep */
0122     PHM_PlatformCaps_RegulatorHot,                          /* Enable throttling on 'regulator hot' events. */
0123     PHM_PlatformCaps_BACO,                                  /* Support Bus Alive Chip Off mode */
0124     PHM_PlatformCaps_DisableDPM,                            /* Disable DPM, supported from Llano */
0125     PHM_PlatformCaps_DynamicM3Arbiter,                      /* support dynamically change m3 arbitor parameters */
0126     PHM_PlatformCaps_SclkDeepSleep,                         /* support sclk deep sleep */
0127     PHM_PlatformCaps_DynamicPatchPowerState,                /* this ASIC supports to patch power state dynamically */
0128     PHM_PlatformCaps_ThermalAutoThrottling,                 /* enabling auto thermal throttling, */
0129     PHM_PlatformCaps_SumoThermalPolicy,                     /* A thermal policy specific for Sumo */
0130     PHM_PlatformCaps_PCIEPerformanceRequest,                /* support to change RC voltage */
0131     PHM_PlatformCaps_BLControlledByGPU,                     /* support varibright */
0132     PHM_PlatformCaps_PowerContainment,                      /* support DPM2 power containment (AKA TDP clamping) */
0133     PHM_PlatformCaps_SQRamping,                             /* support DPM2 SQ power throttle */
0134     PHM_PlatformCaps_CAC,                                   /* support Capacitance * Activity power estimation */
0135     PHM_PlatformCaps_NIChipsets,                            /* Northern Island and beyond chipsets */
0136     PHM_PlatformCaps_TrinityChipsets,                       /* Trinity chipset */
0137     PHM_PlatformCaps_EvergreenChipsets,                     /* Evergreen family chipset */
0138     PHM_PlatformCaps_PowerControl,                          /* Cayman and beyond chipsets */
0139     PHM_PlatformCaps_DisableLSClockGating,                  /* to disable Light Sleep control for HDP memories */
0140     PHM_PlatformCaps_BoostState,                            /* this ASIC supports boost state */
0141     PHM_PlatformCaps_UserMaxClockForMultiDisplays,          /* indicates if max memory clock is used for all status when multiple displays are connected */
0142     PHM_PlatformCaps_RegWriteDelay,                         /* indicates if back to back reg write delay is required */
0143     PHM_PlatformCaps_NonABMSupportInPPLib,                  /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
0144     PHM_PlatformCaps_GFXDynamicMGPowerGating,               /* Enable Dynamic MG PowerGating on Trinity */
0145     PHM_PlatformCaps_DisableSMUUVDHandshake,                /* Disable SMU UVD Handshake */
0146     PHM_PlatformCaps_DTE,                                   /* Support Digital Temperature Estimation */
0147     PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,            /* This is for the feature requested by David B., and Tonny W.*/
0148     PHM_PlatformCaps_UVDPowerGating,                        /* enable UVD power gating, supported from Llano */
0149     PHM_PlatformCaps_UVDDynamicPowerGating,                 /* enable UVD Dynamic power gating, supported from UVD5 */
0150     PHM_PlatformCaps_VCEPowerGating,                        /* Enable VCE power gating, supported for TN and later ASICs */
0151     PHM_PlatformCaps_SamuPowerGating,                       /* Enable SAMU power gating, supported for KV and later ASICs */
0152     PHM_PlatformCaps_UVDDPM,                                /* UVD clock DPM */
0153     PHM_PlatformCaps_VCEDPM,                                /* VCE clock DPM */
0154     PHM_PlatformCaps_SamuDPM,                               /* SAMU clock DPM */
0155     PHM_PlatformCaps_AcpDPM,                                /* ACP clock DPM */
0156     PHM_PlatformCaps_SclkDeepSleepAboveLow,                 /* Enable SCLK Deep Sleep on all DPM states */
0157     PHM_PlatformCaps_DynamicUVDState,                       /* Dynamic UVD State */
0158     PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
0159     PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,            /* Set UVD Clk With Dummy Back End */
0160     PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,            /* Set VCE Clk With Dummy Back End */
0161     PHM_PlatformCaps_WantACPClkWithDummyBackEnd,            /* Set SAM Clk With Dummy Back End */
0162     PHM_PlatformCaps_OD6inACSupport,                        /* indicates that the ASIC/back end supports OD6 */
0163     PHM_PlatformCaps_OD6inDCSupport,                        /* indicates that the ASIC/back end supports OD6 in DC */
0164     PHM_PlatformCaps_EnablePlatformPowerManagement,         /* indicates that Platform Power Management feature is supported */
0165     PHM_PlatformCaps_SurpriseRemoval,                       /* indicates that surprise removal feature is requested */
0166     PHM_PlatformCaps_NewCACVoltage,                         /* indicates new CAC voltage table support */
0167     PHM_PlatformCaps_DiDtSupport,                           /* for dI/dT feature */
0168     PHM_PlatformCaps_DBRamping,                             /* for dI/dT feature */
0169     PHM_PlatformCaps_TDRamping,                             /* for dI/dT feature */
0170     PHM_PlatformCaps_TCPRamping,                            /* for dI/dT feature */
0171     PHM_PlatformCaps_DBRRamping,                            /* for dI/dT feature */
0172     PHM_PlatformCaps_DiDtEDCEnable,                         /* for dI/dT feature */
0173     PHM_PlatformCaps_GCEDC,                                 /* for dI/dT feature */
0174     PHM_PlatformCaps_PSM,                                   /* for dI/dT feature */
0175     PHM_PlatformCaps_EnableSMU7ThermalManagement,           /* SMC will manage thermal events */
0176     PHM_PlatformCaps_FPS,                                   /* FPS support */
0177     PHM_PlatformCaps_ACP,                                   /* ACP support */
0178     PHM_PlatformCaps_SclkThrottleLowNotification,           /* SCLK Throttle Low Notification */
0179     PHM_PlatformCaps_XDMAEnabled,                           /* XDMA engine is enabled */
0180     PHM_PlatformCaps_UseDummyBackEnd,                       /* use dummy back end */
0181     PHM_PlatformCaps_EnableDFSBypass,                       /* Enable DFS bypass */
0182     PHM_PlatformCaps_VddNBDirectRequest,
0183     PHM_PlatformCaps_PauseMMSessions,
0184     PHM_PlatformCaps_UnTabledHardwareInterface,             /* Tableless/direct call hardware interface for CI and newer ASICs */
0185     PHM_PlatformCaps_SMU7,                                  /* indicates that vpuRecoveryBegin without SMU shutdown */
0186     PHM_PlatformCaps_RevertGPIO5Polarity,                   /* indicates revert GPIO5 plarity table support */
0187     PHM_PlatformCaps_Thermal2GPIO17,                        /* indicates thermal2GPIO17 table support */
0188     PHM_PlatformCaps_ThermalOutGPIO,                        /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
0189     PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,      /* Disable memory clock switch during Framelock */
0190     PHM_PlatformCaps_ForceMclkHigh,                         /* Disable memory clock switching by forcing memory clock high */
0191     PHM_PlatformCaps_VRHotGPIOConfigurable,                 /* indicates VR_HOT GPIO configurable */
0192     PHM_PlatformCaps_TempInversion,                         /* enable Temp Inversion feature */
0193     PHM_PlatformCaps_IOIC3,
0194     PHM_PlatformCaps_ConnectedStandby,
0195     PHM_PlatformCaps_EVV,
0196     PHM_PlatformCaps_EnableLongIdleBACOSupport,
0197     PHM_PlatformCaps_CombinePCCWithThermalSignal,
0198     PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
0199     PHM_PlatformCaps_StablePState,
0200     PHM_PlatformCaps_OD6PlusinACSupport,
0201     PHM_PlatformCaps_OD6PlusinDCSupport,
0202     PHM_PlatformCaps_ODThermalLimitUnlock,
0203     PHM_PlatformCaps_ReducePowerLimit,
0204     PHM_PlatformCaps_ODFuzzyFanControlSupport,
0205     PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
0206     PHM_PlatformCaps_ControlVDDGFX,
0207     PHM_PlatformCaps_BBBSupported,
0208     PHM_PlatformCaps_DisableVoltageIsland,
0209     PHM_PlatformCaps_FanSpeedInTableIsRPM,
0210     PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
0211     PHM_PlatformCaps_IcelandULPSSWWorkAround,
0212     PHM_PlatformCaps_FPSEnhancement,
0213     PHM_PlatformCaps_LoadPostProductionFirmware,
0214     PHM_PlatformCaps_VpuRecoveryInProgress,
0215     PHM_PlatformCaps_Falcon_QuickTransition,
0216     PHM_PlatformCaps_AVFS,
0217     PHM_PlatformCaps_ClockStretcher,
0218     PHM_PlatformCaps_TablelessHardwareInterface,
0219     PHM_PlatformCaps_EnableDriverEVV,
0220     PHM_PlatformCaps_SPLLShutdownSupport,
0221     PHM_PlatformCaps_VirtualBatteryState,
0222     PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
0223     PHM_PlatformCaps_DisableMclkSwitchForVR,
0224     PHM_PlatformCaps_SMU8,
0225     PHM_PlatformCaps_VRHotPolarityHigh,
0226     PHM_PlatformCaps_IPS_UlpsExclusive,
0227     PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
0228     PHM_PlatformCaps_GeminiAsymmetricPower,
0229     PHM_PlatformCaps_OCLPowerOptimization,
0230     PHM_PlatformCaps_MaxPCIEBandWidth,
0231     PHM_PlatformCaps_PerfPerWattOptimizationSupport,
0232     PHM_PlatformCaps_UVDClientMCTuning,
0233     PHM_PlatformCaps_ODNinACSupport,
0234     PHM_PlatformCaps_ODNinDCSupport,
0235     PHM_PlatformCaps_OD8inACSupport,
0236     PHM_PlatformCaps_OD8inDCSupport,
0237     PHM_PlatformCaps_UMDPState,
0238     PHM_PlatformCaps_AutoWattmanSupport,
0239     PHM_PlatformCaps_AutoWattmanEnable_CCCState,
0240     PHM_PlatformCaps_FreeSyncActive,
0241     PHM_PlatformCaps_EnableShadowPstate,
0242     PHM_PlatformCaps_customThermalManagement,
0243     PHM_PlatformCaps_staticFanControl,
0244     PHM_PlatformCaps_Virtual_System,
0245     PHM_PlatformCaps_LowestUclkReservedForUlv,
0246     PHM_PlatformCaps_EnableBoostState,
0247     PHM_PlatformCaps_AVFSSupport,
0248     PHM_PlatformCaps_ThermalPolicyDelay,
0249     PHM_PlatformCaps_CustomFanControlSupport,
0250     PHM_PlatformCaps_BAMACO,
0251     PHM_PlatformCaps_Max
0252 };
0253
0254 #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
0255
0256 /* Number of uint32_t entries used by CAPS table */
0257 #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
0258     ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
0259
0260 struct pp_hw_descriptor {
0261     uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
0262 };
0263
0264 enum PHM_PerformanceLevelDesignation {
0265     PHM_PerformanceLevelDesignation_Activity,
0266     PHM_PerformanceLevelDesignation_PowerContainment
0267 };
0268
0269 typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
0270
0271 struct PHM_PerformanceLevel {
0272     uint32_t    coreClock;
0273     uint32_t    memory_clock;
0274     uint32_t  vddc;
0275     uint32_t  vddci;
0276     uint32_t    nonLocalMemoryFreq;
0277     uint32_t nonLocalMemoryWidth;
0278 };
0279
0280 typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
0281
0282 /* Function for setting a platform cap */
0283 static inline void phm_cap_set(uint32_t *caps,
0284             enum phm_platform_caps c)
0285 {
0286     caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
0287                  (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
0288 }
0289
0290 static inline void phm_cap_unset(uint32_t *caps,
0291             enum phm_platform_caps c)
0292 {
0293     caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
0294 }
0295
0296 static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
0297 {
0298     return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
0299           (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
0300 }
0301
0302 #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
0303
0304 #define PP_PCIEGenInvalid  0xffff
0305 enum PP_PCIEGen {
0306     PP_PCIEGen1 = 0,                /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
0307     PP_PCIEGen2,                    /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
0308     PP_PCIEGen3                     /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
0309 };
0310
0311 typedef enum PP_PCIEGen PP_PCIEGen;
0312
0313 #define PP_Min_PCIEGen     PP_PCIEGen1
0314 #define PP_Max_PCIEGen     PP_PCIEGen3
0315 #define PP_Min_PCIELane    1
0316 #define PP_Max_PCIELane    16
0317
0318 enum phm_clock_Type {
0319     PHM_DispClock = 1,
0320     PHM_SClock,
0321     PHM_MemClock
0322 };
0323
0324 #define MAX_NUM_CLOCKS 16
0325
0326 struct PP_Clocks {
0327     uint32_t engineClock;
0328     uint32_t memoryClock;
0329     uint32_t BusBandwidth;
0330     uint32_t engineClockInSR;
0331     uint32_t dcefClock;
0332     uint32_t dcefClockInSR;
0333 };
0334
0335 struct pp_clock_info {
0336     uint32_t min_mem_clk;
0337     uint32_t max_mem_clk;
0338     uint32_t min_eng_clk;
0339     uint32_t max_eng_clk;
0340     uint32_t min_bus_bandwidth;
0341     uint32_t max_bus_bandwidth;
0342 };
0343
0344 struct phm_platform_descriptor {
0345     uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
0346     uint32_t vbiosInterruptId;
0347     struct PP_Clocks overdriveLimit;
0348     struct PP_Clocks clockStep;
0349     uint32_t hardwareActivityPerformanceLevels;
0350     uint32_t minimumClocksReductionPercentage;
0351     uint32_t minOverdriveVDDC;
0352     uint32_t maxOverdriveVDDC;
0353     uint32_t overdriveVDDCStep;
0354     uint32_t hardwarePerformanceLevels;
0355     uint16_t powerBudget;
0356     uint32_t TDPLimit;
0357     uint32_t nearTDPLimit;
0358     uint32_t nearTDPLimitAdjusted;
0359     uint32_t SQRampingThreshold;
0360     uint32_t CACLeakage;
0361     uint16_t TDPODLimit;
0362     uint32_t TDPAdjustment;
0363     bool TDPAdjustmentPolarity;
0364     uint16_t LoadLineSlope;
0365     uint32_t  VidMinLimit;
0366     uint32_t  VidMaxLimit;
0367     uint32_t  VidStep;
0368     uint32_t  VidAdjustment;
0369     bool VidAdjustmentPolarity;
0370 };
0371
0372 struct phm_clocks {
0373     uint32_t num_of_entries;
0374     uint32_t clock[MAX_NUM_CLOCKS];
0375 };
0376
0377 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
0378 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
0379 #define DPMTABLE_UPDATE_SCLK        0x00000004
0380 #define DPMTABLE_UPDATE_MCLK        0x00000008
0381 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
0382 #define DPMTABLE_UPDATE_SOCCLK      0x00000020
0383
0384 struct phm_odn_performance_level {
0385     uint32_t clock;
0386     uint32_t vddc;
0387     bool enabled;
0388 };
0389
0390 struct phm_odn_clock_levels {
0391     uint32_t size;
0392     uint32_t options;
0393     uint32_t flags;
0394     uint32_t num_of_pl;
0395     /* variable-sized array, specify by num_of_pl. */
0396     struct phm_odn_performance_level entries[8];
0397 };
0398
0399 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
0400 extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
0401 extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
0402 extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
0403 extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
0404 extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
0405 extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
0406 extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
0407             const struct pp_hw_power_state *pcurrent_state,
0408          const struct pp_hw_power_state *pnew_power_state);
0409
0410 extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
0411                    struct pp_power_state *adjusted_ps,
0412                  const struct pp_power_state *current_ps);
0413
0414 extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
0415
0416 extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
0417 extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
0418 extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
0419 extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
0420 extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
0421 extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
0422 extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
0423 extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
0424
0425 extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
0426                  const struct pp_hw_power_state *pstate1,
0427                  const struct pp_hw_power_state *pstate2,
0428                  bool *equal);
0429
0430 extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
0431         const struct amd_pp_display_configuration *display_config);
0432
0433 extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
0434         struct amd_pp_simple_clock_info *info);
0435
0436 extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
0437
0438 extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
0439
0440 extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
0441                 PHM_PerformanceLevelDesignation designation, uint32_t index,
0442                 PHM_PerformanceLevel *level);
0443
0444 extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
0445             struct pp_clock_info *pclock_info,
0446             PHM_PerformanceLevelDesignation designation);
0447
0448 extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
0449
0450 extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
0451
0452 extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
0453         enum amd_pp_clock_type type,
0454         struct pp_clock_levels_with_latency *clocks);
0455 extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
0456         enum amd_pp_clock_type type,
0457         struct pp_clock_levels_with_voltage *clocks);
0458 extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
0459                         void *clock_ranges);
0460 extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
0461         struct pp_display_clock_request *clock);
0462
0463 extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
0464 extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
0465
0466 extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);
0467
0468 #endif /* _HARDWARE_MANAGER_H_ */
0469