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0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef _VEGA20_HWMGR_H_
0025 #define _VEGA20_HWMGR_H_
0026 
0027 #include "hwmgr.h"
0028 #include "smu11_driver_if.h"
0029 #include "ppatomfwctrl.h"
0030 
0031 #define VEGA20_MAX_HARDWARE_POWERLEVELS 2
0032 
0033 #define WaterMarksExist  1
0034 #define WaterMarksLoaded 2
0035 
0036 #define VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS   8
0037 #define VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
0038 #define VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
0039 #define VG20_PSUEDO_NUM_UCLK_DPM_LEVELS     4
0040 
0041 //OverDriver8 macro defs
0042 #define AVFS_CURVE 0
0043 #define OD8_HOTCURVE_TEMPERATURE 85
0044 
0045 #define VG20_CLOCK_MAX_DEFAULT 0xFFFF
0046 
0047 typedef uint32_t PP_Clock;
0048 
0049 enum {
0050     GNLD_DPM_PREFETCHER = 0,
0051     GNLD_DPM_GFXCLK,
0052     GNLD_DPM_UCLK,
0053     GNLD_DPM_SOCCLK,
0054     GNLD_DPM_UVD,
0055     GNLD_DPM_VCE,
0056     GNLD_ULV,
0057     GNLD_DPM_MP0CLK,
0058     GNLD_DPM_LINK,
0059     GNLD_DPM_DCEFCLK,
0060     GNLD_DS_GFXCLK,
0061     GNLD_DS_SOCCLK,
0062     GNLD_DS_LCLK,
0063     GNLD_PPT,
0064     GNLD_TDC,
0065     GNLD_THERMAL,
0066     GNLD_GFX_PER_CU_CG,
0067     GNLD_RM,
0068     GNLD_DS_DCEFCLK,
0069     GNLD_ACDC,
0070     GNLD_VR0HOT,
0071     GNLD_VR1HOT,
0072     GNLD_FW_CTF,
0073     GNLD_LED_DISPLAY,
0074     GNLD_FAN_CONTROL,
0075     GNLD_DIDT,
0076     GNLD_GFXOFF,
0077     GNLD_CG,
0078     GNLD_DPM_FCLK,
0079     GNLD_DS_FCLK,
0080     GNLD_DS_MP1CLK,
0081     GNLD_DS_MP0CLK,
0082     GNLD_XGMI,
0083     GNLD_ECC,
0084 
0085     GNLD_FEATURES_MAX
0086 };
0087 
0088 
0089 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
0090 
0091 #define SMC_DPM_FEATURES    0x30F
0092 
0093 struct smu_features {
0094     bool supported;
0095     bool enabled;
0096     bool allowed;
0097     uint32_t smu_feature_id;
0098     uint64_t smu_feature_bitmap;
0099 };
0100 
0101 struct vega20_performance_level {
0102     uint32_t  soc_clock;
0103     uint32_t  gfx_clock;
0104     uint32_t  mem_clock;
0105 };
0106 
0107 struct vega20_bacos {
0108     uint32_t                       baco_flags;
0109     /* struct vega20_performance_level  performance_level; */
0110 };
0111 
0112 struct vega20_uvd_clocks {
0113     uint32_t  vclk;
0114     uint32_t  dclk;
0115 };
0116 
0117 struct vega20_vce_clocks {
0118     uint32_t  evclk;
0119     uint32_t  ecclk;
0120 };
0121 
0122 struct vega20_power_state {
0123     uint32_t                  magic;
0124     struct vega20_uvd_clocks    uvd_clks;
0125     struct vega20_vce_clocks    vce_clks;
0126     uint16_t                  performance_level_count;
0127     bool                      dc_compatible;
0128     uint32_t                  sclk_threshold;
0129     struct vega20_performance_level  performance_levels[VEGA20_MAX_HARDWARE_POWERLEVELS];
0130 };
0131 
0132 struct vega20_dpm_level {
0133     bool        enabled;
0134     uint32_t    value;
0135     uint32_t    param1;
0136 };
0137 
0138 #define VEGA20_MAX_DEEPSLEEP_DIVIDER_ID 5
0139 #define MAX_REGULAR_DPM_NUMBER 16
0140 #define MAX_PCIE_CONF 2
0141 #define VEGA20_MINIMUM_ENGINE_CLOCK 2500
0142 
0143 struct vega20_max_sustainable_clocks {
0144     PP_Clock display_clock;
0145     PP_Clock phy_clock;
0146     PP_Clock pixel_clock;
0147     PP_Clock uclock;
0148     PP_Clock dcef_clock;
0149     PP_Clock soc_clock;
0150 };
0151 
0152 struct vega20_dpm_state {
0153     uint32_t  soft_min_level;
0154     uint32_t  soft_max_level;
0155     uint32_t  hard_min_level;
0156     uint32_t  hard_max_level;
0157 };
0158 
0159 struct vega20_single_dpm_table {
0160     uint32_t        count;
0161     struct vega20_dpm_state dpm_state;
0162     struct vega20_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
0163 };
0164 
0165 struct vega20_odn_dpm_control {
0166     uint32_t    count;
0167     uint32_t    entries[MAX_REGULAR_DPM_NUMBER];
0168 };
0169 
0170 struct vega20_pcie_table {
0171     uint16_t count;
0172     uint8_t  pcie_gen[MAX_PCIE_CONF];
0173     uint8_t  pcie_lane[MAX_PCIE_CONF];
0174     uint32_t lclk[MAX_PCIE_CONF];
0175 };
0176 
0177 struct vega20_dpm_table {
0178     struct vega20_single_dpm_table  soc_table;
0179     struct vega20_single_dpm_table  gfx_table;
0180     struct vega20_single_dpm_table  mem_table;
0181     struct vega20_single_dpm_table  eclk_table;
0182     struct vega20_single_dpm_table  vclk_table;
0183     struct vega20_single_dpm_table  dclk_table;
0184     struct vega20_single_dpm_table  dcef_table;
0185     struct vega20_single_dpm_table  pixel_table;
0186     struct vega20_single_dpm_table  display_table;
0187     struct vega20_single_dpm_table  phy_table;
0188     struct vega20_single_dpm_table  fclk_table;
0189     struct vega20_pcie_table        pcie_table;
0190 };
0191 
0192 #define VEGA20_MAX_LEAKAGE_COUNT  8
0193 struct vega20_leakage_voltage {
0194     uint16_t  count;
0195     uint16_t  leakage_id[VEGA20_MAX_LEAKAGE_COUNT];
0196     uint16_t  actual_voltage[VEGA20_MAX_LEAKAGE_COUNT];
0197 };
0198 
0199 struct vega20_display_timing {
0200     uint32_t  min_clock_in_sr;
0201     uint32_t  num_existing_displays;
0202 };
0203 
0204 struct vega20_dpmlevel_enable_mask {
0205     uint32_t  uvd_dpm_enable_mask;
0206     uint32_t  vce_dpm_enable_mask;
0207     uint32_t  samu_dpm_enable_mask;
0208     uint32_t  sclk_dpm_enable_mask;
0209     uint32_t  mclk_dpm_enable_mask;
0210 };
0211 
0212 struct vega20_vbios_boot_state {
0213     uint8_t     uc_cooling_id;
0214     uint16_t    vddc;
0215     uint16_t    vddci;
0216     uint16_t    mvddc;
0217     uint16_t    vdd_gfx;
0218     uint32_t    gfx_clock;
0219     uint32_t    mem_clock;
0220     uint32_t    soc_clock;
0221     uint32_t    dcef_clock;
0222     uint32_t    eclock;
0223     uint32_t    dclock;
0224     uint32_t    vclock;
0225     uint32_t    fclock;
0226 };
0227 
0228 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
0229 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
0230 #define DPMTABLE_UPDATE_SCLK        0x00000004
0231 #define DPMTABLE_UPDATE_MCLK        0x00000008
0232 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
0233 #define DPMTABLE_OD_UPDATE_SCLK_MASK     0x00000020
0234 #define DPMTABLE_OD_UPDATE_MCLK_MASK     0x00000040
0235 
0236 // To determine if sclk and mclk are in overdrive state
0237 #define SCLK_MASK_OVERDRIVE_ENABLED      0x00000008
0238 #define MCLK_MASK_OVERDRIVE_ENABLED      0x00000010
0239 #define SOCCLK_OVERDRIVE_ENABLED         0x00000020
0240 
0241 struct vega20_smc_state_table {
0242     uint32_t        soc_boot_level;
0243     uint32_t        gfx_boot_level;
0244     uint32_t        dcef_boot_level;
0245     uint32_t        mem_boot_level;
0246     uint32_t        uvd_boot_level;
0247     uint32_t        vce_boot_level;
0248     uint32_t        gfx_max_level;
0249     uint32_t        mem_max_level;
0250     uint8_t         vr_hot_gpio;
0251     uint8_t         ac_dc_gpio;
0252     uint8_t         therm_out_gpio;
0253     uint8_t         therm_out_polarity;
0254     uint8_t         therm_out_mode;
0255     PPTable_t       pp_table;
0256     Watermarks_t    water_marks_table;
0257     AvfsDebugTable_t avfs_debug_table;
0258     AvfsFuseOverride_t avfs_fuse_override_table;
0259     SmuMetrics_t    smu_metrics;
0260     DriverSmuConfig_t driver_smu_config;
0261     DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
0262     OverDriveTable_t overdrive_table;
0263 };
0264 
0265 struct vega20_mclk_latency_entries {
0266     uint32_t  frequency;
0267     uint32_t  latency;
0268 };
0269 
0270 struct vega20_mclk_latency_table {
0271     uint32_t  count;
0272     struct vega20_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
0273 };
0274 
0275 struct vega20_registry_data {
0276     uint64_t  disallowed_features;
0277     uint8_t   ac_dc_switch_gpio_support;
0278     uint8_t   acg_loop_support;
0279     uint8_t   clock_stretcher_support;
0280     uint8_t   db_ramping_support;
0281     uint8_t   didt_mode;
0282     uint8_t   didt_support;
0283     uint8_t   edc_didt_support;
0284     uint8_t   force_dpm_high;
0285     uint8_t   fuzzy_fan_control_support;
0286     uint8_t   mclk_dpm_key_disabled;
0287     uint8_t   od_state_in_dc_support;
0288     uint8_t   pcie_lane_override;
0289     uint8_t   pcie_speed_override;
0290     uint32_t  pcie_clock_override;
0291     uint8_t   pcie_dpm_key_disabled;
0292     uint8_t   dcefclk_dpm_key_disabled;
0293     uint8_t   prefetcher_dpm_key_disabled;
0294     uint8_t   quick_transition_support;
0295     uint8_t   regulator_hot_gpio_support;
0296     uint8_t   master_deep_sleep_support;
0297     uint8_t   gfx_clk_deep_sleep_support;
0298     uint8_t   sclk_deep_sleep_support;
0299     uint8_t   lclk_deep_sleep_support;
0300     uint8_t   dce_fclk_deep_sleep_support;
0301     uint8_t   sclk_dpm_key_disabled;
0302     uint8_t   sclk_throttle_low_notification;
0303     uint8_t   skip_baco_hardware;
0304     uint8_t   socclk_dpm_key_disabled;
0305     uint8_t   sq_ramping_support;
0306     uint8_t   tcp_ramping_support;
0307     uint8_t   td_ramping_support;
0308     uint8_t   dbr_ramping_support;
0309     uint8_t   gc_didt_support;
0310     uint8_t   psm_didt_support;
0311     uint8_t   thermal_support;
0312     uint8_t   fw_ctf_enabled;
0313     uint8_t   led_dpm_enabled;
0314     uint8_t   fan_control_support;
0315     uint8_t   ulv_support;
0316     uint8_t   od8_feature_enable;
0317     uint8_t   disable_water_mark;
0318     uint8_t   disable_workload_policy;
0319     uint32_t  force_workload_policy_mask;
0320     uint8_t   disable_3d_fs_detection;
0321     uint8_t   disable_pp_tuning;
0322     uint8_t   disable_xlpp_tuning;
0323     uint32_t  perf_ui_tuning_profile_turbo;
0324     uint32_t  perf_ui_tuning_profile_powerSave;
0325     uint32_t  perf_ui_tuning_profile_xl;
0326     uint16_t  zrpm_stop_temp;
0327     uint16_t  zrpm_start_temp;
0328     uint32_t  stable_pstate_sclk_dpm_percentage;
0329     uint8_t   fps_support;
0330     uint8_t   vr0hot;
0331     uint8_t   vr1hot;
0332     uint8_t   disable_auto_wattman;
0333     uint32_t  auto_wattman_debug;
0334     uint32_t  auto_wattman_sample_period;
0335     uint32_t  fclk_gfxclk_ratio;
0336     uint8_t   auto_wattman_threshold;
0337     uint8_t   log_avfs_param;
0338     uint8_t   enable_enginess;
0339     uint8_t   custom_fan_support;
0340     uint8_t   disable_pcc_limit_control;
0341     uint8_t   gfxoff_controlled_by_driver;
0342 };
0343 
0344 struct vega20_odn_clock_voltage_dependency_table {
0345     uint32_t count;
0346     struct phm_ppt_v1_clock_voltage_dependency_record
0347         entries[MAX_REGULAR_DPM_NUMBER];
0348 };
0349 
0350 struct vega20_odn_dpm_table {
0351     struct vega20_odn_dpm_control       control_gfxclk_state;
0352     struct vega20_odn_dpm_control       control_memclk_state;
0353     struct phm_odn_clock_levels     odn_core_clock_dpm_levels;
0354     struct phm_odn_clock_levels     odn_memory_clock_dpm_levels;
0355     struct vega20_odn_clock_voltage_dependency_table        vdd_dependency_on_sclk;
0356     struct vega20_odn_clock_voltage_dependency_table        vdd_dependency_on_mclk;
0357     struct vega20_odn_clock_voltage_dependency_table        vdd_dependency_on_socclk;
0358     uint32_t                odn_mclk_min_limit;
0359 };
0360 
0361 struct vega20_odn_fan_table {
0362     uint32_t    target_fan_speed;
0363     uint32_t    target_temperature;
0364     uint32_t    min_performance_clock;
0365     uint32_t    min_fan_limit;
0366     bool        force_fan_pwm;
0367 };
0368 
0369 struct vega20_odn_temp_table {
0370     uint16_t    target_operating_temp;
0371     uint16_t    default_target_operating_temp;
0372     uint16_t    operating_temp_min_limit;
0373     uint16_t    operating_temp_max_limit;
0374     uint16_t    operating_temp_step;
0375 };
0376 
0377 struct vega20_odn_data {
0378     uint32_t    apply_overdrive_next_settings_mask;
0379     uint32_t    overdrive_next_state;
0380     uint32_t    overdrive_next_capabilities;
0381     uint32_t    odn_sclk_dpm_enable_mask;
0382     uint32_t    odn_mclk_dpm_enable_mask;
0383     struct vega20_odn_dpm_table odn_dpm_table;
0384     struct vega20_odn_fan_table odn_fan_table;
0385     struct vega20_odn_temp_table    odn_temp_table;
0386 };
0387 
0388 enum OD8_FEATURE_ID
0389 {
0390     OD8_GFXCLK_LIMITS               = 1 << 0,
0391     OD8_GFXCLK_CURVE                = 1 << 1,
0392     OD8_UCLK_MAX                    = 1 << 2,
0393     OD8_POWER_LIMIT                 = 1 << 3,
0394     OD8_ACOUSTIC_LIMIT_SCLK         = 1 << 4,   //FanMaximumRpm
0395     OD8_FAN_SPEED_MIN               = 1 << 5,   //FanMinimumPwm
0396     OD8_TEMPERATURE_FAN             = 1 << 6,   //FanTargetTemperature
0397     OD8_TEMPERATURE_SYSTEM          = 1 << 7,   //MaxOpTemp
0398     OD8_MEMORY_TIMING_TUNE          = 1 << 8,
0399     OD8_FAN_ZERO_RPM_CONTROL        = 1 << 9
0400 };
0401 
0402 enum OD8_SETTING_ID
0403 {
0404     OD8_SETTING_GFXCLK_FMIN = 0,
0405     OD8_SETTING_GFXCLK_FMAX,
0406     OD8_SETTING_GFXCLK_FREQ1,
0407     OD8_SETTING_GFXCLK_VOLTAGE1,
0408     OD8_SETTING_GFXCLK_FREQ2,
0409     OD8_SETTING_GFXCLK_VOLTAGE2,
0410     OD8_SETTING_GFXCLK_FREQ3,
0411     OD8_SETTING_GFXCLK_VOLTAGE3,
0412     OD8_SETTING_UCLK_FMAX,
0413     OD8_SETTING_POWER_PERCENTAGE,
0414     OD8_SETTING_FAN_ACOUSTIC_LIMIT,
0415     OD8_SETTING_FAN_MIN_SPEED,
0416     OD8_SETTING_FAN_TARGET_TEMP,
0417     OD8_SETTING_OPERATING_TEMP_MAX,
0418     OD8_SETTING_AC_TIMING,
0419     OD8_SETTING_FAN_ZERO_RPM_CONTROL,
0420     OD8_SETTING_COUNT
0421 };
0422 
0423 struct vega20_od8_single_setting {
0424     uint32_t    feature_id;
0425     int32_t     min_value;
0426     int32_t     max_value;
0427     int32_t     current_value;
0428     int32_t     default_value;
0429 };
0430 
0431 struct vega20_od8_settings {
0432     uint32_t    overdrive8_capabilities;
0433     struct vega20_od8_single_setting    od8_settings_array[OD8_SETTING_COUNT];
0434 };
0435 
0436 struct vega20_hwmgr {
0437     struct vega20_dpm_table          dpm_table;
0438     struct vega20_dpm_table          golden_dpm_table;
0439     struct vega20_registry_data      registry_data;
0440     struct vega20_vbios_boot_state   vbios_boot_state;
0441     struct vega20_mclk_latency_table mclk_latency_table;
0442 
0443     struct vega20_max_sustainable_clocks max_sustainable_clocks;
0444 
0445     struct vega20_leakage_voltage    vddc_leakage;
0446 
0447     uint32_t                           vddc_control;
0448     struct pp_atomfwctrl_voltage_table vddc_voltage_table;
0449     uint32_t                           mvdd_control;
0450     struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
0451     uint32_t                           vddci_control;
0452     struct pp_atomfwctrl_voltage_table vddci_voltage_table;
0453 
0454     uint32_t                           active_auto_throttle_sources;
0455     struct vega20_bacos                bacos;
0456 
0457     /* ---- General data ---- */
0458     uint8_t                           need_update_dpm_table;
0459 
0460     bool                           cac_enabled;
0461     bool                           battery_state;
0462     bool                           is_tlu_enabled;
0463     bool                           avfs_exist;
0464 
0465     uint32_t                       low_sclk_interrupt_threshold;
0466 
0467     uint32_t                       total_active_cus;
0468 
0469     uint32_t                       water_marks_bitmap;
0470 
0471     struct vega20_display_timing display_timing;
0472 
0473     /* ---- Vega20 Dyn Register Settings ---- */
0474 
0475     uint32_t                       debug_settings;
0476     uint32_t                       lowest_uclk_reserved_for_ulv;
0477     uint32_t                       gfxclk_average_alpha;
0478     uint32_t                       socclk_average_alpha;
0479     uint32_t                       uclk_average_alpha;
0480     uint32_t                       gfx_activity_average_alpha;
0481     uint32_t                       display_voltage_mode;
0482     uint32_t                       dcef_clk_quad_eqn_a;
0483     uint32_t                       dcef_clk_quad_eqn_b;
0484     uint32_t                       dcef_clk_quad_eqn_c;
0485     uint32_t                       disp_clk_quad_eqn_a;
0486     uint32_t                       disp_clk_quad_eqn_b;
0487     uint32_t                       disp_clk_quad_eqn_c;
0488     uint32_t                       pixel_clk_quad_eqn_a;
0489     uint32_t                       pixel_clk_quad_eqn_b;
0490     uint32_t                       pixel_clk_quad_eqn_c;
0491     uint32_t                       phy_clk_quad_eqn_a;
0492     uint32_t                       phy_clk_quad_eqn_b;
0493     uint32_t                       phy_clk_quad_eqn_c;
0494 
0495     /* ---- Thermal Temperature Setting ---- */
0496     struct vega20_dpmlevel_enable_mask     dpm_level_enable_mask;
0497 
0498     /* ---- Power Gating States ---- */
0499     bool                           uvd_power_gated;
0500     bool                           vce_power_gated;
0501     bool                           samu_power_gated;
0502     bool                           need_long_memory_training;
0503 
0504     /* Internal settings to apply the application power optimization parameters */
0505     bool                           apply_optimized_settings;
0506     uint32_t                       disable_dpm_mask;
0507 
0508     /* ---- Overdrive next setting ---- */
0509     struct vega20_odn_data         odn_data;
0510     bool                           gfxclk_overdrive;
0511     bool                           memclk_overdrive;
0512 
0513     /* ---- Overdrive8 Setting ---- */
0514     struct vega20_od8_settings     od8_settings;
0515 
0516     /* ---- Workload Mask ---- */
0517     uint32_t                       workload_mask;
0518 
0519     /* ---- SMU9 ---- */
0520     uint32_t                       smu_version;
0521     struct smu_features            smu_features[GNLD_FEATURES_MAX];
0522     struct vega20_smc_state_table  smc_state_table;
0523 
0524     /* ---- Gfxoff ---- */
0525     bool                           gfxoff_allowed;
0526     uint32_t                       counter_gfxoff;
0527 
0528     unsigned long                  metrics_time;
0529     SmuMetrics_t                   metrics_table;
0530     struct gpu_metrics_v1_0        gpu_metrics_table;
0531 
0532     bool                           pcie_parameters_override;
0533     uint32_t                       pcie_gen_level1;
0534     uint32_t                       pcie_width_level1;
0535 
0536     bool                           is_custom_profile_set;
0537 };
0538 
0539 #define VEGA20_DPM2_NEAR_TDP_DEC                      10
0540 #define VEGA20_DPM2_ABOVE_SAFE_INC                    5
0541 #define VEGA20_DPM2_BELOW_SAFE_INC                    20
0542 
0543 #define VEGA20_DPM2_LTA_WINDOW_SIZE                   7
0544 
0545 #define VEGA20_DPM2_LTS_TRUNCATE                      0
0546 
0547 #define VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT            80
0548 
0549 #define VEGA20_DPM2_MAXPS_PERCENT_M                   90
0550 #define VEGA20_DPM2_MAXPS_PERCENT_H                   90
0551 
0552 #define VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN         50
0553 
0554 #define VEGA20_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
0555 #define VEGA20_DPM2_SQ_RAMP_MIN_POWER                 0x12
0556 #define VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
0557 #define VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
0558 #define VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
0559 
0560 #define VEGA20_VOLTAGE_CONTROL_NONE                   0x0
0561 #define VEGA20_VOLTAGE_CONTROL_BY_GPIO                0x1
0562 #define VEGA20_VOLTAGE_CONTROL_BY_SVID2               0x2
0563 #define VEGA20_VOLTAGE_CONTROL_MERGED                 0x3
0564 /* To convert to Q8.8 format for firmware */
0565 #define VEGA20_Q88_FORMAT_CONVERSION_UNIT             256
0566 
0567 #define VEGA20_UNUSED_GPIO_PIN       0x7F
0568 
0569 #define VEGA20_THERM_OUT_MODE_DISABLE       0x0
0570 #define VEGA20_THERM_OUT_MODE_THERM_ONLY    0x1
0571 #define VEGA20_THERM_OUT_MODE_THERM_VRHOT   0x2
0572 
0573 #define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT   0xffffffff
0574 #define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT    0xffffffff
0575 
0576 #define PPVEGA20_VEGA20GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
0577 #define PPVEGA20_VEGA20SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
0578 #define PPVEGA20_VEGA20UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
0579 #define PPVEGA20_VEGA20GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
0580 #define PPVEGA20_VEGA20LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
0581 #define PPVEGA20_VEGA20DISPLAYVOLTAGEMODE_DFLT         0xffffffff
0582 #define PPREGKEY_VEGA20QUADRATICEQUATION_DFLT          0xffffffff
0583 
0584 #define VEGA20_UMD_PSTATE_GFXCLK_LEVEL         0x3
0585 #define VEGA20_UMD_PSTATE_SOCCLK_LEVEL         0x3
0586 #define VEGA20_UMD_PSTATE_MCLK_LEVEL           0x2
0587 #define VEGA20_UMD_PSTATE_UVDCLK_LEVEL         0x3
0588 #define VEGA20_UMD_PSTATE_VCEMCLK_LEVEL        0x3
0589 
0590 #endif /* _VEGA20_HWMGR_H_ */
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