powerplay/hwmgr/vega12_processpptables.c

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/module.h>
0024 #include <linux/slab.h>
0025 #include <linux/fb.h>
0026
0027 #include "vega12/smu9_driver_if.h"
0028 #include "vega12_processpptables.h"
0029 #include "ppatomfwctrl.h"
0030 #include "atomfirmware.h"
0031 #include "pp_debug.h"
0032 #include "cgs_common.h"
0033 #include "vega12_pptable.h"
0034
0035 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
0036         enum phm_platform_caps cap)
0037 {
0038     if (enable)
0039         phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
0040     else
0041         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
0042 }
0043
0044 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
0045 {
0046     int index = GetIndexIntoMasterDataTable(powerplayinfo);
0047
0048     u16 size;
0049     u8 frev, crev;
0050     const void *table_address = hwmgr->soft_pp_table;
0051
0052     if (!table_address) {
0053         table_address = (ATOM_Vega12_POWERPLAYTABLE *)
0054                 smu_atom_get_data_table(hwmgr->adev, index,
0055                         &size, &frev, &crev);
0056
0057         hwmgr->soft_pp_table = table_address;   /*Cache the result in RAM.*/
0058         hwmgr->soft_pp_table_size = size;
0059     }
0060
0061     return table_address;
0062 }
0063
0064 static int check_powerplay_tables(
0065         struct pp_hwmgr *hwmgr,
0066         const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
0067 {
0068     PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
0069         ATOM_VEGA12_TABLE_REVISION_VEGA12),
0070         "Unsupported PPTable format!", return -1);
0071     PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
0072         "Invalid PowerPlay Table!", return -1);
0073
0074     return 0;
0075 }
0076
0077 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
0078 {
0079     set_hw_cap(
0080             hwmgr,
0081             0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY),
0082             PHM_PlatformCaps_PowerPlaySupport);
0083
0084     set_hw_cap(
0085             hwmgr,
0086             0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
0087             PHM_PlatformCaps_BiosPowerSourceControl);
0088
0089     set_hw_cap(
0090             hwmgr,
0091             0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO),
0092             PHM_PlatformCaps_BACO);
0093
0094     set_hw_cap(
0095             hwmgr,
0096             0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO),
0097              PHM_PlatformCaps_BAMACO);
0098
0099     return 0;
0100 }
0101
0102 static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
0103 {
0104     struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table;
0105
0106     PP_ASSERT_WITH_CODE(
0107         pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0,
0108         "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!",
0109         return -1);
0110
0111     ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address;
0112     ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address;
0113     ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address;
0114     ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address;
0115
0116     ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl;
0117     ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda;
0118     ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl;
0119     ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda;
0120
0121     ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl;
0122     ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda;
0123     ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent;
0124     ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent;
0125
0126     ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx;
0127     ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc;
0128
0129     ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping;
0130     ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping;
0131     ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping;
0132     ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping;
0133
0134     ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask;
0135     ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask;
0136
0137     ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent;
0138     ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset;
0139     ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx;
0140
0141     ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent;
0142     ppsmc_pptable->SocOffset = smc_dpm_table.socoffset;
0143     ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc;
0144
0145     ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent;
0146     ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset;
0147     ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0;
0148
0149     ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent;
0150     ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset;
0151     ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1;
0152
0153     ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio;
0154     ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity;
0155     ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio;
0156     ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity;
0157
0158     ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio;
0159     ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity;
0160     ppsmc_pptable->Padding1 = smc_dpm_table.padding1;
0161     ppsmc_pptable->Padding2 = smc_dpm_table.padding2;
0162
0163     ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0;
0164     ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1;
0165     ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2;
0166
0167     ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled;
0168     ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent;
0169     ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq;
0170
0171     ppsmc_pptable->UclkSpreadEnabled = 0;
0172     ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent;
0173     ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq;
0174
0175     ppsmc_pptable->SocclkSpreadEnabled = 0;
0176     ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent;
0177     ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq;
0178
0179     ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled;
0180     ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent;
0181     ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq;
0182
0183     ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
0184
0185     ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address;
0186
0187     return 0;
0188 }
0189
0190 #define VEGA12_ENGINECLOCK_HARDMAX 198000
0191 static int init_powerplay_table_information(
0192         struct pp_hwmgr *hwmgr,
0193         const ATOM_Vega12_POWERPLAYTABLE *powerplay_table)
0194 {
0195     struct phm_ppt_v3_information *pptable_information =
0196         (struct phm_ppt_v3_information *)hwmgr->pptable;
0197     uint32_t disable_power_control = 0;
0198     int result;
0199
0200     hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
0201     pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType;
0202
0203     set_hw_cap(hwmgr,
0204         ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
0205         PHM_PlatformCaps_ThermalController);
0206
0207     phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
0208
0209     if (le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]) > VEGA12_ENGINECLOCK_HARDMAX)
0210         hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX;
0211     else
0212         hwmgr->platform_descriptor.overdriveLimit.engineClock =
0213             le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]);
0214     hwmgr->platform_descriptor.overdriveLimit.memoryClock =
0215         le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]);
0216
0217     phm_copy_overdrive_settings_limits_array(hwmgr,
0218                          &pptable_information->od_settings_max,
0219                          powerplay_table->ODSettingsMax,
0220                          ATOM_VEGA12_ODSETTING_COUNT);
0221     phm_copy_overdrive_settings_limits_array(hwmgr,
0222                          &pptable_information->od_settings_min,
0223                          powerplay_table->ODSettingsMin,
0224                          ATOM_VEGA12_ODSETTING_COUNT);
0225
0226     /* hwmgr->platformDescriptor.minOverdriveVDDC = 0;
0227     hwmgr->platformDescriptor.maxOverdriveVDDC = 0;
0228     hwmgr->platformDescriptor.overdriveVDDCStep = 0; */
0229
0230     if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
0231         && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
0232         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
0233
0234     pptable_information->us_small_power_limit1 = le16_to_cpu(powerplay_table->usSmallPowerLimit1);
0235     pptable_information->us_small_power_limit2 = le16_to_cpu(powerplay_table->usSmallPowerLimit2);
0236     pptable_information->us_boost_power_limit = le16_to_cpu(powerplay_table->usBoostPowerLimit);
0237     pptable_information->us_od_turbo_power_limit = le16_to_cpu(powerplay_table->usODTurboPowerLimit);
0238     pptable_information->us_od_powersave_power_limit = le16_to_cpu(powerplay_table->usODPowerSavePowerLimit);
0239
0240     pptable_information->us_software_shutdown_temp = le16_to_cpu(powerplay_table->usSoftwareShutdownTemp);
0241
0242     hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]);
0243
0244     disable_power_control = 0;
0245     if (!disable_power_control) {
0246         /* enable TDP overdrive (PowerControl) feature as well if supported */
0247         if (hwmgr->platform_descriptor.TDPODLimit)
0248             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0249                 PHM_PlatformCaps_PowerControl);
0250     }
0251
0252     phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax, ATOM_VEGA12_PPCLOCK_COUNT);
0253     phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin, ATOM_VEGA12_PPCLOCK_COUNT);
0254
0255     pptable_information->smc_pptable = kmemdup(&(powerplay_table->smcPPTable),
0256                            sizeof(PPTable_t), GFP_KERNEL);
0257     if (pptable_information->smc_pptable == NULL)
0258         return -ENOMEM;
0259
0260     result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
0261
0262     return result;
0263 }
0264
0265 static int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
0266 {
0267     int result = 0;
0268     const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;
0269
0270     hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
0271     PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
0272         "Failed to allocate hwmgr->pptable!", return -ENOMEM);
0273
0274     powerplay_table = get_powerplay_table(hwmgr);
0275     PP_ASSERT_WITH_CODE((powerplay_table != NULL),
0276         "Missing PowerPlay Table!", return -1);
0277
0278     result = check_powerplay_tables(hwmgr, powerplay_table);
0279     PP_ASSERT_WITH_CODE((result == 0),
0280         "check_powerplay_tables failed", return result);
0281
0282     result = set_platform_caps(hwmgr,
0283             le32_to_cpu(powerplay_table->ulPlatformCaps));
0284     PP_ASSERT_WITH_CODE((result == 0),
0285         "set_platform_caps failed", return result);
0286
0287     result = init_powerplay_table_information(hwmgr, powerplay_table);
0288     PP_ASSERT_WITH_CODE((result == 0),
0289         "init_powerplay_table_information failed", return result);
0290
0291     return result;
0292 }
0293
0294 static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
0295 {
0296     struct phm_ppt_v3_information *pp_table_info =
0297             (struct phm_ppt_v3_information *)(hwmgr->pptable);
0298
0299     kfree(pp_table_info->power_saving_clock_max);
0300     pp_table_info->power_saving_clock_max = NULL;
0301
0302     kfree(pp_table_info->power_saving_clock_min);
0303     pp_table_info->power_saving_clock_min = NULL;
0304
0305     kfree(pp_table_info->od_settings_max);
0306     pp_table_info->od_settings_max = NULL;
0307
0308     kfree(pp_table_info->od_settings_min);
0309     pp_table_info->od_settings_min = NULL;
0310
0311     kfree(pp_table_info->smc_pptable);
0312     pp_table_info->smc_pptable = NULL;
0313
0314     kfree(hwmgr->pptable);
0315     hwmgr->pptable = NULL;
0316
0317     return 0;
0318 }
0319
0320 const struct pp_table_func vega12_pptable_funcs = {
0321     .pptable_init = vega12_pp_tables_initialize,
0322     .pptable_fini = vega12_pp_tables_uninitialize,
0323 };
0324
0325 #if 0
0326 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
0327         uint16_t classification, uint16_t classification2)
0328 {
0329     uint32_t result = 0;
0330
0331     if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
0332         result |= PP_StateClassificationFlag_Boot;
0333
0334     if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
0335         result |= PP_StateClassificationFlag_Thermal;
0336
0337     if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
0338         result |= PP_StateClassificationFlag_LimitedPowerSource;
0339
0340     if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
0341         result |= PP_StateClassificationFlag_Rest;
0342
0343     if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
0344         result |= PP_StateClassificationFlag_Forced;
0345
0346     if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
0347         result |= PP_StateClassificationFlag_ACPI;
0348
0349     if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
0350         result |= PP_StateClassificationFlag_LimitedPowerSource_2;
0351
0352     return result;
0353 }
0354
0355 int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
0356         uint32_t entry_index, struct pp_power_state *power_state,
0357         int (*call_back_func)(struct pp_hwmgr *, void *,
0358                 struct pp_power_state *, void *, uint32_t))
0359 {
0360     int result = 0;
0361     const ATOM_Vega12_State_Array *state_arrays;
0362     const ATOM_Vega12_State *state_entry;
0363     const ATOM_Vega12_POWERPLAYTABLE *pp_table =
0364             get_powerplay_table(hwmgr);
0365
0366     PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
0367             return -1;);
0368     power_state->classification.bios_index = entry_index;
0369
0370     if (pp_table->sHeader.format_revision >=
0371             ATOM_Vega12_TABLE_REVISION_VEGA12) {
0372         state_arrays = (ATOM_Vega12_State_Array *)
0373                 (((unsigned long)pp_table) +
0374                 le16_to_cpu(pp_table->usStateArrayOffset));
0375
0376         PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
0377                 "Invalid PowerPlay Table State Array Offset.",
0378                 return -1);
0379         PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
0380                 "Invalid PowerPlay Table State Array.",
0381                 return -1);
0382         PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
0383                 "Invalid PowerPlay Table State Array Entry.",
0384                 return -1);
0385
0386         state_entry = &(state_arrays->states[entry_index]);
0387
0388         result = call_back_func(hwmgr, (void *)state_entry, power_state,
0389                 (void *)pp_table,
0390                 make_classification_flags(hwmgr,
0391                     le16_to_cpu(state_entry->usClassification),
0392                     le16_to_cpu(state_entry->usClassification2)));
0393     }
0394
0395     if (!result && (power_state->classification.flags &
0396             PP_StateClassificationFlag_Boot))
0397         result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
0398
0399     return result;
0400 }
0401 #endif