powerplay/hwmgr/vega12_hwmgr.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _VEGA12_HWMGR_H_
0025 #define _VEGA12_HWMGR_H_
0026
0027 #include "hwmgr.h"
0028 #include "vega12/smu9_driver_if.h"
0029 #include "ppatomfwctrl.h"
0030
0031 #define VEGA12_MAX_HARDWARE_POWERLEVELS 2
0032
0033 #define WaterMarksExist  1
0034 #define WaterMarksLoaded 2
0035
0036 #define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS   16
0037 #define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS   8
0038 #define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS  8
0039 #define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS     4
0040
0041 enum
0042 {
0043     GNLD_DPM_PREFETCHER = 0,
0044     GNLD_DPM_GFXCLK,
0045     GNLD_DPM_UCLK,
0046     GNLD_DPM_SOCCLK,
0047     GNLD_DPM_UVD,
0048     GNLD_DPM_VCE,
0049     GNLD_ULV,
0050     GNLD_DPM_MP0CLK,
0051     GNLD_DPM_LINK,
0052     GNLD_DPM_DCEFCLK,
0053     GNLD_DS_GFXCLK,
0054     GNLD_DS_SOCCLK,
0055     GNLD_DS_LCLK,
0056     GNLD_PPT,
0057     GNLD_TDC,
0058     GNLD_THERMAL,
0059     GNLD_GFX_PER_CU_CG,
0060     GNLD_RM,
0061     GNLD_DS_DCEFCLK,
0062     GNLD_ACDC,
0063     GNLD_VR0HOT,
0064     GNLD_VR1HOT,
0065     GNLD_FW_CTF,
0066     GNLD_LED_DISPLAY,
0067     GNLD_FAN_CONTROL,
0068     GNLD_DIDT,
0069     GNLD_GFXOFF,
0070     GNLD_CG,
0071     GNLD_ACG,
0072
0073     GNLD_FEATURES_MAX
0074 };
0075
0076
0077 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
0078
0079 #define SMC_DPM_FEATURES    0x30F
0080
0081 struct smu_features {
0082     bool supported;
0083     bool enabled;
0084     bool allowed;
0085     uint32_t smu_feature_id;
0086     uint64_t smu_feature_bitmap;
0087 };
0088
0089 struct vega12_dpm_level {
0090     bool        enabled;
0091     uint32_t    value;
0092     uint32_t    param1;
0093 };
0094
0095 #define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
0096 #define MAX_REGULAR_DPM_NUMBER 16
0097 #define MAX_PCIE_CONF 2
0098 #define VEGA12_MINIMUM_ENGINE_CLOCK 2500
0099
0100 struct vega12_dpm_state {
0101     uint32_t  soft_min_level;
0102     uint32_t  soft_max_level;
0103     uint32_t  hard_min_level;
0104     uint32_t  hard_max_level;
0105 };
0106
0107 struct vega12_single_dpm_table {
0108     uint32_t        count;
0109     struct vega12_dpm_state dpm_state;
0110     struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
0111 };
0112
0113 struct vega12_odn_dpm_control {
0114     uint32_t    count;
0115     uint32_t    entries[MAX_REGULAR_DPM_NUMBER];
0116 };
0117
0118 struct vega12_pcie_table {
0119     uint16_t count;
0120     uint8_t  pcie_gen[MAX_PCIE_CONF];
0121     uint8_t  pcie_lane[MAX_PCIE_CONF];
0122     uint32_t lclk[MAX_PCIE_CONF];
0123 };
0124
0125 struct vega12_dpm_table {
0126     struct vega12_single_dpm_table  soc_table;
0127     struct vega12_single_dpm_table  gfx_table;
0128     struct vega12_single_dpm_table  mem_table;
0129     struct vega12_single_dpm_table  eclk_table;
0130     struct vega12_single_dpm_table  vclk_table;
0131     struct vega12_single_dpm_table  dclk_table;
0132     struct vega12_single_dpm_table  dcef_table;
0133     struct vega12_single_dpm_table  pixel_table;
0134     struct vega12_single_dpm_table  display_table;
0135     struct vega12_single_dpm_table  phy_table;
0136     struct vega12_pcie_table        pcie_table;
0137 };
0138
0139 #define VEGA12_MAX_LEAKAGE_COUNT  8
0140 struct vega12_leakage_voltage {
0141     uint16_t  count;
0142     uint16_t  leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
0143     uint16_t  actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
0144 };
0145
0146 struct vega12_display_timing {
0147     uint32_t  min_clock_in_sr;
0148     uint32_t  num_existing_displays;
0149 };
0150
0151 struct vega12_dpmlevel_enable_mask {
0152     uint32_t  uvd_dpm_enable_mask;
0153     uint32_t  vce_dpm_enable_mask;
0154     uint32_t  samu_dpm_enable_mask;
0155     uint32_t  sclk_dpm_enable_mask;
0156     uint32_t  mclk_dpm_enable_mask;
0157 };
0158
0159 struct vega12_vbios_boot_state {
0160     bool        bsoc_vddc_lock;
0161     uint8_t     uc_cooling_id;
0162     uint16_t    vddc;
0163     uint16_t    vddci;
0164     uint16_t    mvddc;
0165     uint16_t    vdd_gfx;
0166     uint32_t    gfx_clock;
0167     uint32_t    mem_clock;
0168     uint32_t    soc_clock;
0169     uint32_t    dcef_clock;
0170     uint32_t    eclock;
0171     uint32_t    dclock;
0172     uint32_t    vclock;
0173 };
0174
0175 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
0176 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
0177 #define DPMTABLE_UPDATE_SCLK        0x00000004
0178 #define DPMTABLE_UPDATE_MCLK        0x00000008
0179 #define DPMTABLE_OD_UPDATE_VDDC     0x00000010
0180
0181 struct vega12_smc_state_table {
0182     uint32_t        soc_boot_level;
0183     uint32_t        gfx_boot_level;
0184     uint32_t        dcef_boot_level;
0185     uint32_t        mem_boot_level;
0186     uint32_t        uvd_boot_level;
0187     uint32_t        vce_boot_level;
0188     uint32_t        gfx_max_level;
0189     uint32_t        mem_max_level;
0190     uint8_t         vr_hot_gpio;
0191     uint8_t         ac_dc_gpio;
0192     uint8_t         therm_out_gpio;
0193     uint8_t         therm_out_polarity;
0194     uint8_t         therm_out_mode;
0195     PPTable_t       pp_table;
0196     Watermarks_t    water_marks_table;
0197     AvfsDebugTable_t avfs_debug_table;
0198     AvfsFuseOverride_t avfs_fuse_override_table;
0199     SmuMetrics_t    smu_metrics;
0200     DriverSmuConfig_t driver_smu_config;
0201     DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
0202     OverDriveTable_t overdrive_table;
0203 };
0204
0205 struct vega12_mclk_latency_entries {
0206     uint32_t  frequency;
0207     uint32_t  latency;
0208 };
0209
0210 struct vega12_mclk_latency_table {
0211     uint32_t  count;
0212     struct vega12_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
0213 };
0214
0215 struct vega12_registry_data {
0216     uint64_t  disallowed_features;
0217     uint8_t   ac_dc_switch_gpio_support;
0218     uint8_t   acg_loop_support;
0219     uint8_t   clock_stretcher_support;
0220     uint8_t   db_ramping_support;
0221     uint8_t   didt_mode;
0222     uint8_t   didt_support;
0223     uint8_t   edc_didt_support;
0224     uint8_t   force_dpm_high;
0225     uint8_t   fuzzy_fan_control_support;
0226     uint8_t   mclk_dpm_key_disabled;
0227     uint8_t   od_state_in_dc_support;
0228     uint8_t   pcie_lane_override;
0229     uint8_t   pcie_speed_override;
0230     uint32_t  pcie_clock_override;
0231     uint8_t   pcie_dpm_key_disabled;
0232     uint8_t   dcefclk_dpm_key_disabled;
0233     uint8_t   prefetcher_dpm_key_disabled;
0234     uint8_t   quick_transition_support;
0235     uint8_t   regulator_hot_gpio_support;
0236     uint8_t   master_deep_sleep_support;
0237     uint8_t   gfx_clk_deep_sleep_support;
0238     uint8_t   sclk_deep_sleep_support;
0239     uint8_t   lclk_deep_sleep_support;
0240     uint8_t   dce_fclk_deep_sleep_support;
0241     uint8_t   sclk_dpm_key_disabled;
0242     uint8_t   sclk_throttle_low_notification;
0243     uint8_t   skip_baco_hardware;
0244     uint8_t   socclk_dpm_key_disabled;
0245     uint8_t   sq_ramping_support;
0246     uint8_t   tcp_ramping_support;
0247     uint8_t   td_ramping_support;
0248     uint8_t   dbr_ramping_support;
0249     uint8_t   gc_didt_support;
0250     uint8_t   psm_didt_support;
0251     uint8_t   thermal_support;
0252     uint8_t   fw_ctf_enabled;
0253     uint8_t   led_dpm_enabled;
0254     uint8_t   fan_control_support;
0255     uint8_t   ulv_support;
0256     uint8_t   odn_feature_enable;
0257     uint8_t   disable_water_mark;
0258     uint8_t   disable_workload_policy;
0259     uint32_t  force_workload_policy_mask;
0260     uint8_t   disable_3d_fs_detection;
0261     uint8_t   disable_pp_tuning;
0262     uint8_t   disable_xlpp_tuning;
0263     uint32_t  perf_ui_tuning_profile_turbo;
0264     uint32_t  perf_ui_tuning_profile_powerSave;
0265     uint32_t  perf_ui_tuning_profile_xl;
0266     uint16_t  zrpm_stop_temp;
0267     uint16_t  zrpm_start_temp;
0268     uint32_t  stable_pstate_sclk_dpm_percentage;
0269     uint8_t   fps_support;
0270     uint8_t   vr0hot;
0271     uint8_t   vr1hot;
0272     uint8_t   disable_auto_wattman;
0273     uint32_t  auto_wattman_debug;
0274     uint32_t  auto_wattman_sample_period;
0275     uint8_t   auto_wattman_threshold;
0276     uint8_t   log_avfs_param;
0277     uint8_t   enable_enginess;
0278     uint8_t   custom_fan_support;
0279     uint8_t   disable_pcc_limit_control;
0280 };
0281
0282 struct vega12_odn_clock_voltage_dependency_table {
0283     uint32_t count;
0284     struct phm_ppt_v1_clock_voltage_dependency_record
0285         entries[MAX_REGULAR_DPM_NUMBER];
0286 };
0287
0288 struct vega12_odn_dpm_table {
0289     struct vega12_odn_dpm_control       control_gfxclk_state;
0290     struct vega12_odn_dpm_control       control_memclk_state;
0291     struct phm_odn_clock_levels     odn_core_clock_dpm_levels;
0292     struct phm_odn_clock_levels     odn_memory_clock_dpm_levels;
0293     struct vega12_odn_clock_voltage_dependency_table        vdd_dependency_on_sclk;
0294     struct vega12_odn_clock_voltage_dependency_table        vdd_dependency_on_mclk;
0295     struct vega12_odn_clock_voltage_dependency_table        vdd_dependency_on_socclk;
0296     uint32_t                odn_mclk_min_limit;
0297 };
0298
0299 struct vega12_odn_fan_table {
0300     uint32_t    target_fan_speed;
0301     uint32_t    target_temperature;
0302     uint32_t    min_performance_clock;
0303     uint32_t    min_fan_limit;
0304     bool        force_fan_pwm;
0305 };
0306
0307 struct vega12_clock_range {
0308     uint32_t    ACMax;
0309     uint32_t    ACMin;
0310     uint32_t    DCMax;
0311 };
0312
0313 struct vega12_hwmgr {
0314     struct vega12_dpm_table          dpm_table;
0315     struct vega12_dpm_table          golden_dpm_table;
0316     struct vega12_registry_data      registry_data;
0317     struct vega12_vbios_boot_state   vbios_boot_state;
0318     struct vega12_mclk_latency_table mclk_latency_table;
0319
0320     struct vega12_leakage_voltage    vddc_leakage;
0321
0322     uint32_t                           vddc_control;
0323     struct pp_atomfwctrl_voltage_table vddc_voltage_table;
0324     uint32_t                           mvdd_control;
0325     struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
0326     uint32_t                           vddci_control;
0327     struct pp_atomfwctrl_voltage_table vddci_voltage_table;
0328
0329     uint32_t                           active_auto_throttle_sources;
0330     uint32_t                           water_marks_bitmap;
0331
0332     struct vega12_odn_dpm_table       odn_dpm_table;
0333     struct vega12_odn_fan_table       odn_fan_table;
0334
0335     /* ---- General data ---- */
0336     uint8_t                           need_update_dpm_table;
0337
0338     bool                           cac_enabled;
0339     bool                           battery_state;
0340     bool                           is_tlu_enabled;
0341     bool                           avfs_exist;
0342
0343     uint32_t                       low_sclk_interrupt_threshold;
0344
0345     uint32_t                       total_active_cus;
0346
0347     struct vega12_display_timing display_timing;
0348
0349     /* ---- Vega12 Dyn Register Settings ---- */
0350
0351     uint32_t                       debug_settings;
0352     uint32_t                       lowest_uclk_reserved_for_ulv;
0353     uint32_t                       gfxclk_average_alpha;
0354     uint32_t                       socclk_average_alpha;
0355     uint32_t                       uclk_average_alpha;
0356     uint32_t                       gfx_activity_average_alpha;
0357     uint32_t                       display_voltage_mode;
0358     uint32_t                       dcef_clk_quad_eqn_a;
0359     uint32_t                       dcef_clk_quad_eqn_b;
0360     uint32_t                       dcef_clk_quad_eqn_c;
0361     uint32_t                       disp_clk_quad_eqn_a;
0362     uint32_t                       disp_clk_quad_eqn_b;
0363     uint32_t                       disp_clk_quad_eqn_c;
0364     uint32_t                       pixel_clk_quad_eqn_a;
0365     uint32_t                       pixel_clk_quad_eqn_b;
0366     uint32_t                       pixel_clk_quad_eqn_c;
0367     uint32_t                       phy_clk_quad_eqn_a;
0368     uint32_t                       phy_clk_quad_eqn_b;
0369     uint32_t                       phy_clk_quad_eqn_c;
0370
0371     /* ---- Thermal Temperature Setting ---- */
0372     struct vega12_dpmlevel_enable_mask     dpm_level_enable_mask;
0373
0374     /* ---- Power Gating States ---- */
0375     bool                           uvd_power_gated;
0376     bool                           vce_power_gated;
0377     bool                           samu_power_gated;
0378     bool                           need_long_memory_training;
0379
0380     /* Internal settings to apply the application power optimization parameters */
0381     bool                           apply_optimized_settings;
0382     uint32_t                       disable_dpm_mask;
0383
0384     /* ---- Overdrive next setting ---- */
0385     uint32_t                       apply_overdrive_next_settings_mask;
0386
0387     /* ---- Workload Mask ---- */
0388     uint32_t                       workload_mask;
0389
0390     /* ---- SMU9 ---- */
0391     uint32_t                       smu_version;
0392     struct smu_features            smu_features[GNLD_FEATURES_MAX];
0393     struct vega12_smc_state_table  smc_state_table;
0394
0395     struct vega12_clock_range      clk_range[PPCLK_COUNT];
0396
0397     /* ---- Gfxoff ---- */
0398     bool                           gfxoff_controlled_by_driver;
0399
0400     unsigned long                  metrics_time;
0401     SmuMetrics_t                   metrics_table;
0402     struct gpu_metrics_v1_0        gpu_metrics_table;
0403 };
0404
0405 #define VEGA12_DPM2_NEAR_TDP_DEC                      10
0406 #define VEGA12_DPM2_ABOVE_SAFE_INC                    5
0407 #define VEGA12_DPM2_BELOW_SAFE_INC                    20
0408
0409 #define VEGA12_DPM2_LTA_WINDOW_SIZE                   7
0410
0411 #define VEGA12_DPM2_LTS_TRUNCATE                      0
0412
0413 #define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT            80
0414
0415 #define VEGA12_DPM2_MAXPS_PERCENT_M                   90
0416 #define VEGA12_DPM2_MAXPS_PERCENT_H                   90
0417
0418 #define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN         50
0419
0420 #define VEGA12_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
0421 #define VEGA12_DPM2_SQ_RAMP_MIN_POWER                 0x12
0422 #define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
0423 #define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
0424 #define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
0425
0426 #define VEGA12_VOLTAGE_CONTROL_NONE                   0x0
0427 #define VEGA12_VOLTAGE_CONTROL_BY_GPIO                0x1
0428 #define VEGA12_VOLTAGE_CONTROL_BY_SVID2               0x2
0429 #define VEGA12_VOLTAGE_CONTROL_MERGED                 0x3
0430 /* To convert to Q8.8 format for firmware */
0431 #define VEGA12_Q88_FORMAT_CONVERSION_UNIT             256
0432
0433 #define VEGA12_UNUSED_GPIO_PIN       0x7F
0434
0435 #define VEGA12_THERM_OUT_MODE_DISABLE       0x0
0436 #define VEGA12_THERM_OUT_MODE_THERM_ONLY    0x1
0437 #define VEGA12_THERM_OUT_MODE_THERM_VRHOT   0x2
0438
0439 #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT   0xffffffff
0440 #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT    0xffffffff
0441
0442 #define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
0443 #define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
0444 #define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
0445 #define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
0446 #define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT   0xffffffff
0447 #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT         0xffffffff
0448 #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT          0xffffffff
0449
0450 #define VEGA12_UMD_PSTATE_GFXCLK_LEVEL         0x3
0451 #define VEGA12_UMD_PSTATE_SOCCLK_LEVEL         0x3
0452 #define VEGA12_UMD_PSTATE_MCLK_LEVEL           0x2
0453 #define VEGA12_UMD_PSTATE_UVDCLK_LEVEL         0x3
0454 #define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL        0x3
0455
0456 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
0457
0458 #endif /* _VEGA12_HWMGR_H_ */