powerplay/hwmgr/vega12_hwmgr.c

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include <linux/delay.h>
0025 #include <linux/fb.h>
0026 #include <linux/module.h>
0027 #include <linux/slab.h>
0028
0029 #include "hwmgr.h"
0030 #include "amd_powerplay.h"
0031 #include "vega12_smumgr.h"
0032 #include "hardwaremanager.h"
0033 #include "ppatomfwctrl.h"
0034 #include "atomfirmware.h"
0035 #include "cgs_common.h"
0036 #include "vega12_inc.h"
0037 #include "pppcielanes.h"
0038 #include "vega12_hwmgr.h"
0039 #include "vega12_processpptables.h"
0040 #include "vega12_pptable.h"
0041 #include "vega12_thermal.h"
0042 #include "vega12_ppsmc.h"
0043 #include "pp_debug.h"
0044 #include "amd_pcie_helpers.h"
0045 #include "ppinterrupt.h"
0046 #include "pp_overdriver.h"
0047 #include "pp_thermal.h"
0048 #include "vega12_baco.h"
0049
0050 #define smnPCIE_LC_SPEED_CNTL           0x11140290
0051 #define smnPCIE_LC_LINK_WIDTH_CNTL      0x11140288
0052
0053 #define LINK_WIDTH_MAX              6
0054 #define LINK_SPEED_MAX              3
0055 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
0056 static const int link_speed[] = {25, 50, 80, 160};
0057
0058 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
0059         enum pp_clock_type type, uint32_t mask);
0060 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
0061         uint32_t *clock,
0062         PPCLK_e clock_select,
0063         bool max);
0064
0065 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
0066 {
0067     struct vega12_hwmgr *data =
0068             (struct vega12_hwmgr *)(hwmgr->backend);
0069
0070     data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
0071     data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
0072     data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
0073     data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
0074     data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
0075
0076     data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
0077     data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0078     data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0079     data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0080     data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0081     data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0082     data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0083     data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0084     data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0085     data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0086     data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0087     data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0088     data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
0089
0090     data->registry_data.disallowed_features = 0x0;
0091     data->registry_data.od_state_in_dc_support = 0;
0092     data->registry_data.thermal_support = 1;
0093     data->registry_data.skip_baco_hardware = 0;
0094
0095     data->registry_data.log_avfs_param = 0;
0096     data->registry_data.sclk_throttle_low_notification = 1;
0097     data->registry_data.force_dpm_high = 0;
0098     data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
0099
0100     data->registry_data.didt_support = 0;
0101     if (data->registry_data.didt_support) {
0102         data->registry_data.didt_mode = 6;
0103         data->registry_data.sq_ramping_support = 1;
0104         data->registry_data.db_ramping_support = 0;
0105         data->registry_data.td_ramping_support = 0;
0106         data->registry_data.tcp_ramping_support = 0;
0107         data->registry_data.dbr_ramping_support = 0;
0108         data->registry_data.edc_didt_support = 1;
0109         data->registry_data.gc_didt_support = 0;
0110         data->registry_data.psm_didt_support = 0;
0111     }
0112
0113     data->registry_data.pcie_lane_override = 0xff;
0114     data->registry_data.pcie_speed_override = 0xff;
0115     data->registry_data.pcie_clock_override = 0xffffffff;
0116     data->registry_data.regulator_hot_gpio_support = 1;
0117     data->registry_data.ac_dc_switch_gpio_support = 0;
0118     data->registry_data.quick_transition_support = 0;
0119     data->registry_data.zrpm_start_temp = 0xffff;
0120     data->registry_data.zrpm_stop_temp = 0xffff;
0121     data->registry_data.odn_feature_enable = 1;
0122     data->registry_data.disable_water_mark = 0;
0123     data->registry_data.disable_pp_tuning = 0;
0124     data->registry_data.disable_xlpp_tuning = 0;
0125     data->registry_data.disable_workload_policy = 0;
0126     data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
0127     data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
0128     data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
0129     data->registry_data.force_workload_policy_mask = 0;
0130     data->registry_data.disable_3d_fs_detection = 0;
0131     data->registry_data.fps_support = 1;
0132     data->registry_data.disable_auto_wattman = 1;
0133     data->registry_data.auto_wattman_debug = 0;
0134     data->registry_data.auto_wattman_sample_period = 100;
0135     data->registry_data.auto_wattman_threshold = 50;
0136     data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
0137 }
0138
0139 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
0140 {
0141     struct vega12_hwmgr *data =
0142             (struct vega12_hwmgr *)(hwmgr->backend);
0143     struct amdgpu_device *adev = hwmgr->adev;
0144
0145     if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
0146         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0147                 PHM_PlatformCaps_ControlVDDCI);
0148
0149     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0150             PHM_PlatformCaps_TablelessHardwareInterface);
0151
0152     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0153             PHM_PlatformCaps_EnableSMU7ThermalManagement);
0154
0155     if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
0156         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0157                 PHM_PlatformCaps_UVDPowerGating);
0158         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0159                 PHM_PlatformCaps_UVDDynamicPowerGating);
0160     }
0161
0162     if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
0163         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0164                 PHM_PlatformCaps_VCEPowerGating);
0165
0166     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0167             PHM_PlatformCaps_UnTabledHardwareInterface);
0168
0169     if (data->registry_data.odn_feature_enable)
0170         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0171                 PHM_PlatformCaps_ODNinACSupport);
0172     else {
0173         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0174                 PHM_PlatformCaps_OD6inACSupport);
0175         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0176                 PHM_PlatformCaps_OD6PlusinACSupport);
0177     }
0178
0179     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0180             PHM_PlatformCaps_ActivityReporting);
0181     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0182             PHM_PlatformCaps_FanSpeedInTableIsRPM);
0183
0184     if (data->registry_data.od_state_in_dc_support) {
0185         if (data->registry_data.odn_feature_enable)
0186             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0187                     PHM_PlatformCaps_ODNinDCSupport);
0188         else {
0189             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0190                     PHM_PlatformCaps_OD6inDCSupport);
0191             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0192                     PHM_PlatformCaps_OD6PlusinDCSupport);
0193         }
0194     }
0195
0196     if (data->registry_data.thermal_support
0197             && data->registry_data.fuzzy_fan_control_support
0198             && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
0199         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0200                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
0201
0202     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0203                 PHM_PlatformCaps_DynamicPowerManagement);
0204     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0205             PHM_PlatformCaps_SMC);
0206     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0207             PHM_PlatformCaps_ThermalPolicyDelay);
0208
0209     if (data->registry_data.force_dpm_high)
0210         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0211                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
0212
0213     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0214             PHM_PlatformCaps_DynamicUVDState);
0215
0216     if (data->registry_data.sclk_throttle_low_notification)
0217         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0218                 PHM_PlatformCaps_SclkThrottleLowNotification);
0219
0220     /* power tune caps */
0221     /* assume disabled */
0222     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0223             PHM_PlatformCaps_PowerContainment);
0224     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0225             PHM_PlatformCaps_DiDtSupport);
0226     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0227             PHM_PlatformCaps_SQRamping);
0228     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0229             PHM_PlatformCaps_DBRamping);
0230     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0231             PHM_PlatformCaps_TDRamping);
0232     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0233             PHM_PlatformCaps_TCPRamping);
0234     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0235             PHM_PlatformCaps_DBRRamping);
0236     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0237             PHM_PlatformCaps_DiDtEDCEnable);
0238     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0239             PHM_PlatformCaps_GCEDC);
0240     phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0241             PHM_PlatformCaps_PSM);
0242
0243     if (data->registry_data.didt_support) {
0244         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
0245         if (data->registry_data.sq_ramping_support)
0246             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
0247         if (data->registry_data.db_ramping_support)
0248             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
0249         if (data->registry_data.td_ramping_support)
0250             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
0251         if (data->registry_data.tcp_ramping_support)
0252             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
0253         if (data->registry_data.dbr_ramping_support)
0254             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
0255         if (data->registry_data.edc_didt_support)
0256             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
0257         if (data->registry_data.gc_didt_support)
0258             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
0259         if (data->registry_data.psm_didt_support)
0260             phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
0261     }
0262
0263     phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0264             PHM_PlatformCaps_RegulatorHot);
0265
0266     if (data->registry_data.ac_dc_switch_gpio_support) {
0267         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0268                 PHM_PlatformCaps_AutomaticDCTransition);
0269         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0270                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
0271     }
0272
0273     if (data->registry_data.quick_transition_support) {
0274         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0275                 PHM_PlatformCaps_AutomaticDCTransition);
0276         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0277                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
0278         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0279                 PHM_PlatformCaps_Falcon_QuickTransition);
0280     }
0281
0282     if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
0283         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
0284                 PHM_PlatformCaps_LowestUclkReservedForUlv);
0285         if (data->lowest_uclk_reserved_for_ulv == 1)
0286             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0287                     PHM_PlatformCaps_LowestUclkReservedForUlv);
0288     }
0289
0290     if (data->registry_data.custom_fan_support)
0291         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0292                 PHM_PlatformCaps_CustomFanControlSupport);
0293
0294     return 0;
0295 }
0296
0297 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
0298 {
0299     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
0300     struct amdgpu_device *adev = hwmgr->adev;
0301     uint32_t top32, bottom32;
0302     int i;
0303
0304     data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
0305             FEATURE_DPM_PREFETCHER_BIT;
0306     data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
0307             FEATURE_DPM_GFXCLK_BIT;
0308     data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
0309             FEATURE_DPM_UCLK_BIT;
0310     data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
0311             FEATURE_DPM_SOCCLK_BIT;
0312     data->smu_features[GNLD_DPM_UVD].smu_feature_id =
0313             FEATURE_DPM_UVD_BIT;
0314     data->smu_features[GNLD_DPM_VCE].smu_feature_id =
0315             FEATURE_DPM_VCE_BIT;
0316     data->smu_features[GNLD_ULV].smu_feature_id =
0317             FEATURE_ULV_BIT;
0318     data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
0319             FEATURE_DPM_MP0CLK_BIT;
0320     data->smu_features[GNLD_DPM_LINK].smu_feature_id =
0321             FEATURE_DPM_LINK_BIT;
0322     data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
0323             FEATURE_DPM_DCEFCLK_BIT;
0324     data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
0325             FEATURE_DS_GFXCLK_BIT;
0326     data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
0327             FEATURE_DS_SOCCLK_BIT;
0328     data->smu_features[GNLD_DS_LCLK].smu_feature_id =
0329             FEATURE_DS_LCLK_BIT;
0330     data->smu_features[GNLD_PPT].smu_feature_id =
0331             FEATURE_PPT_BIT;
0332     data->smu_features[GNLD_TDC].smu_feature_id =
0333             FEATURE_TDC_BIT;
0334     data->smu_features[GNLD_THERMAL].smu_feature_id =
0335             FEATURE_THERMAL_BIT;
0336     data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
0337             FEATURE_GFX_PER_CU_CG_BIT;
0338     data->smu_features[GNLD_RM].smu_feature_id =
0339             FEATURE_RM_BIT;
0340     data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
0341             FEATURE_DS_DCEFCLK_BIT;
0342     data->smu_features[GNLD_ACDC].smu_feature_id =
0343             FEATURE_ACDC_BIT;
0344     data->smu_features[GNLD_VR0HOT].smu_feature_id =
0345             FEATURE_VR0HOT_BIT;
0346     data->smu_features[GNLD_VR1HOT].smu_feature_id =
0347             FEATURE_VR1HOT_BIT;
0348     data->smu_features[GNLD_FW_CTF].smu_feature_id =
0349             FEATURE_FW_CTF_BIT;
0350     data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
0351             FEATURE_LED_DISPLAY_BIT;
0352     data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
0353             FEATURE_FAN_CONTROL_BIT;
0354     data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
0355     data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
0356     data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
0357     data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
0358
0359     for (i = 0; i < GNLD_FEATURES_MAX; i++) {
0360         data->smu_features[i].smu_feature_bitmap =
0361             (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
0362         data->smu_features[i].allowed =
0363             ((data->registry_data.disallowed_features >> i) & 1) ?
0364             false : true;
0365     }
0366
0367     /* Get the SN to turn into a Unique ID */
0368     smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
0369     smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
0370
0371     adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
0372 }
0373
0374 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
0375 {
0376     return 0;
0377 }
0378
0379 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
0380 {
0381     kfree(hwmgr->backend);
0382     hwmgr->backend = NULL;
0383
0384     return 0;
0385 }
0386
0387 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
0388 {
0389     int result = 0;
0390     struct vega12_hwmgr *data;
0391     struct amdgpu_device *adev = hwmgr->adev;
0392
0393     data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
0394     if (data == NULL)
0395         return -ENOMEM;
0396
0397     hwmgr->backend = data;
0398
0399     vega12_set_default_registry_data(hwmgr);
0400
0401     data->disable_dpm_mask = 0xff;
0402     data->workload_mask = 0xff;
0403
0404     /* need to set voltage control types before EVV patching */
0405     data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
0406     data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
0407     data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
0408
0409     data->water_marks_bitmap = 0;
0410     data->avfs_exist = false;
0411
0412     vega12_set_features_platform_caps(hwmgr);
0413
0414     vega12_init_dpm_defaults(hwmgr);
0415
0416     /* Parse pptable data read from VBIOS */
0417     vega12_set_private_data_based_on_pptable(hwmgr);
0418
0419     data->is_tlu_enabled = false;
0420
0421     hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
0422             VEGA12_MAX_HARDWARE_POWERLEVELS;
0423     hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
0424     hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
0425
0426     hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
0427     /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
0428     hwmgr->platform_descriptor.clockStep.engineClock = 500;
0429     hwmgr->platform_descriptor.clockStep.memoryClock = 500;
0430
0431     data->total_active_cus = adev->gfx.cu_info.number;
0432     /* Setup default Overdrive Fan control settings */
0433     data->odn_fan_table.target_fan_speed =
0434             hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
0435     data->odn_fan_table.target_temperature =
0436             hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
0437     data->odn_fan_table.min_performance_clock =
0438             hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
0439     data->odn_fan_table.min_fan_limit =
0440             hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
0441             hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
0442
0443     if (hwmgr->feature_mask & PP_GFXOFF_MASK)
0444         data->gfxoff_controlled_by_driver = true;
0445     else
0446         data->gfxoff_controlled_by_driver = false;
0447
0448     return result;
0449 }
0450
0451 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
0452 {
0453     struct vega12_hwmgr *data =
0454             (struct vega12_hwmgr *)(hwmgr->backend);
0455
0456     data->low_sclk_interrupt_threshold = 0;
0457
0458     return 0;
0459 }
0460
0461 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
0462 {
0463     PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
0464             "Failed to init sclk threshold!",
0465             return -EINVAL);
0466
0467     return 0;
0468 }
0469
0470 /*
0471  * @fn vega12_init_dpm_state
0472  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
0473  *
0474  * @param    dpm_state - the address of the DPM Table to initiailize.
0475  * @return   None.
0476  */
0477 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
0478 {
0479     dpm_state->soft_min_level = 0x0;
0480     dpm_state->soft_max_level = 0xffff;
0481     dpm_state->hard_min_level = 0x0;
0482     dpm_state->hard_max_level = 0xffff;
0483 }
0484
0485 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)
0486 {
0487     struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
0488     struct vega12_hwmgr *data =
0489             (struct vega12_hwmgr *)(hwmgr->backend);
0490     uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
0491     PPTable_t *pp_table = &(data->smc_state_table.pp_table);
0492     int i;
0493     int ret;
0494
0495     if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
0496         pcie_gen = 3;
0497     else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
0498         pcie_gen = 2;
0499     else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
0500         pcie_gen = 1;
0501     else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
0502         pcie_gen = 0;
0503
0504     if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
0505         pcie_width = 6;
0506     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
0507         pcie_width = 5;
0508     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
0509         pcie_width = 4;
0510     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
0511         pcie_width = 3;
0512     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
0513         pcie_width = 2;
0514     else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
0515         pcie_width = 1;
0516
0517     /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
0518      * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
0519      * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
0520      */
0521     for (i = 0; i < NUM_LINK_LEVELS; i++) {
0522         pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
0523             pp_table->PcieGenSpeed[i];
0524         pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
0525             pp_table->PcieLaneCount[i];
0526
0527         if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
0528             pp_table->PcieLaneCount[i]) {
0529             smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
0530             ret = smum_send_msg_to_smc_with_parameter(hwmgr,
0531                 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
0532                 NULL);
0533             PP_ASSERT_WITH_CODE(!ret,
0534                 "[OverridePcieParameters] Attempt to override pcie params failed!",
0535                 return ret);
0536         }
0537
0538         /* update the pptable */
0539         pp_table->PcieGenSpeed[i] = pcie_gen_arg;
0540         pp_table->PcieLaneCount[i] = pcie_width_arg;
0541     }
0542
0543     /* override to the highest if it's disabled from ppfeaturmask */
0544     if (data->registry_data.pcie_dpm_key_disabled) {
0545         for (i = 0; i < NUM_LINK_LEVELS; i++) {
0546             smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
0547             ret = smum_send_msg_to_smc_with_parameter(hwmgr,
0548                 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
0549                 NULL);
0550             PP_ASSERT_WITH_CODE(!ret,
0551                 "[OverridePcieParameters] Attempt to override pcie params failed!",
0552                 return ret);
0553
0554             pp_table->PcieGenSpeed[i] = pcie_gen;
0555             pp_table->PcieLaneCount[i] = pcie_width;
0556         }
0557         ret = vega12_enable_smc_features(hwmgr,
0558                 false,
0559                 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
0560         PP_ASSERT_WITH_CODE(!ret,
0561                 "Attempt to Disable DPM LINK Failed!",
0562                 return ret);
0563         data->smu_features[GNLD_DPM_LINK].enabled = false;
0564         data->smu_features[GNLD_DPM_LINK].supported = false;
0565     }
0566     return 0;
0567 }
0568
0569 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
0570         PPCLK_e clk_id, uint32_t *num_of_levels)
0571 {
0572     int ret = 0;
0573
0574     ret = smum_send_msg_to_smc_with_parameter(hwmgr,
0575             PPSMC_MSG_GetDpmFreqByIndex,
0576             (clk_id << 16 | 0xFF),
0577             num_of_levels);
0578     PP_ASSERT_WITH_CODE(!ret,
0579             "[GetNumOfDpmLevel] failed to get dpm levels!",
0580             return ret);
0581
0582     return ret;
0583 }
0584
0585 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
0586         PPCLK_e clkID, uint32_t index, uint32_t *clock)
0587 {
0588     /*
0589      *SMU expects the Clock ID to be in the top 16 bits.
0590      *Lower 16 bits specify the level
0591      */
0592     PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
0593         PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index),
0594         clock) == 0,
0595         "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
0596         return -EINVAL);
0597
0598     return 0;
0599 }
0600
0601 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
0602         struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
0603 {
0604     int ret = 0;
0605     uint32_t i, num_of_levels, clk;
0606
0607     ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
0608     PP_ASSERT_WITH_CODE(!ret,
0609             "[SetupSingleDpmTable] failed to get clk levels!",
0610             return ret);
0611
0612     dpm_table->count = num_of_levels;
0613
0614     for (i = 0; i < num_of_levels; i++) {
0615         ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
0616         PP_ASSERT_WITH_CODE(!ret,
0617             "[SetupSingleDpmTable] failed to get clk of specific level!",
0618             return ret);
0619         dpm_table->dpm_levels[i].value = clk;
0620         dpm_table->dpm_levels[i].enabled = true;
0621     }
0622
0623     return ret;
0624 }
0625
0626 /*
0627  * This function is to initialize all DPM state tables
0628  * for SMU based on the dependency table.
0629  * Dynamic state patching function will then trim these
0630  * state tables to the allowed range based
0631  * on the power policy or external client requests,
0632  * such as UVD request, etc.
0633  */
0634 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
0635 {
0636
0637     struct vega12_hwmgr *data =
0638             (struct vega12_hwmgr *)(hwmgr->backend);
0639     struct vega12_single_dpm_table *dpm_table;
0640     int ret = 0;
0641
0642     memset(&data->dpm_table, 0, sizeof(data->dpm_table));
0643
0644     /* socclk */
0645     dpm_table = &(data->dpm_table.soc_table);
0646     if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
0647         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
0648         PP_ASSERT_WITH_CODE(!ret,
0649                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
0650                 return ret);
0651     } else {
0652         dpm_table->count = 1;
0653         dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
0654     }
0655     vega12_init_dpm_state(&(dpm_table->dpm_state));
0656
0657     /* gfxclk */
0658     dpm_table = &(data->dpm_table.gfx_table);
0659     if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
0660         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
0661         PP_ASSERT_WITH_CODE(!ret,
0662                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
0663                 return ret);
0664     } else {
0665         dpm_table->count = 1;
0666         dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
0667     }
0668     vega12_init_dpm_state(&(dpm_table->dpm_state));
0669
0670     /* memclk */
0671     dpm_table = &(data->dpm_table.mem_table);
0672     if (data->smu_features[GNLD_DPM_UCLK].enabled) {
0673         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
0674         PP_ASSERT_WITH_CODE(!ret,
0675                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
0676                 return ret);
0677     } else {
0678         dpm_table->count = 1;
0679         dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
0680     }
0681     vega12_init_dpm_state(&(dpm_table->dpm_state));
0682
0683     /* eclk */
0684     dpm_table = &(data->dpm_table.eclk_table);
0685     if (data->smu_features[GNLD_DPM_VCE].enabled) {
0686         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
0687         PP_ASSERT_WITH_CODE(!ret,
0688                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
0689                 return ret);
0690     } else {
0691         dpm_table->count = 1;
0692         dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
0693     }
0694     vega12_init_dpm_state(&(dpm_table->dpm_state));
0695
0696     /* vclk */
0697     dpm_table = &(data->dpm_table.vclk_table);
0698     if (data->smu_features[GNLD_DPM_UVD].enabled) {
0699         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
0700         PP_ASSERT_WITH_CODE(!ret,
0701                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
0702                 return ret);
0703     } else {
0704         dpm_table->count = 1;
0705         dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
0706     }
0707     vega12_init_dpm_state(&(dpm_table->dpm_state));
0708
0709     /* dclk */
0710     dpm_table = &(data->dpm_table.dclk_table);
0711     if (data->smu_features[GNLD_DPM_UVD].enabled) {
0712         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
0713         PP_ASSERT_WITH_CODE(!ret,
0714                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
0715                 return ret);
0716     } else {
0717         dpm_table->count = 1;
0718         dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
0719     }
0720     vega12_init_dpm_state(&(dpm_table->dpm_state));
0721
0722     /* dcefclk */
0723     dpm_table = &(data->dpm_table.dcef_table);
0724     if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
0725         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
0726         PP_ASSERT_WITH_CODE(!ret,
0727                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
0728                 return ret);
0729     } else {
0730         dpm_table->count = 1;
0731         dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
0732     }
0733     vega12_init_dpm_state(&(dpm_table->dpm_state));
0734
0735     /* pixclk */
0736     dpm_table = &(data->dpm_table.pixel_table);
0737     if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
0738         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
0739         PP_ASSERT_WITH_CODE(!ret,
0740                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
0741                 return ret);
0742     } else
0743         dpm_table->count = 0;
0744     vega12_init_dpm_state(&(dpm_table->dpm_state));
0745
0746     /* dispclk */
0747     dpm_table = &(data->dpm_table.display_table);
0748     if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
0749         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
0750         PP_ASSERT_WITH_CODE(!ret,
0751                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
0752                 return ret);
0753     } else
0754         dpm_table->count = 0;
0755     vega12_init_dpm_state(&(dpm_table->dpm_state));
0756
0757     /* phyclk */
0758     dpm_table = &(data->dpm_table.phy_table);
0759     if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
0760         ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
0761         PP_ASSERT_WITH_CODE(!ret,
0762                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
0763                 return ret);
0764     } else
0765         dpm_table->count = 0;
0766     vega12_init_dpm_state(&(dpm_table->dpm_state));
0767
0768     /* save a copy of the default DPM table */
0769     memcpy(&(data->golden_dpm_table), &(data->dpm_table),
0770             sizeof(struct vega12_dpm_table));
0771
0772     return 0;
0773 }
0774
0775 #if 0
0776 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
0777 {
0778     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
0779     struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
0780     uint32_t min_level;
0781
0782     hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
0783     hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
0784
0785     /* Optimize compute power profile: Use only highest
0786      * 2 power levels (if more than 2 are available)
0787      */
0788     if (dpm_table->count > 2)
0789         min_level = dpm_table->count - 2;
0790     else if (dpm_table->count == 2)
0791         min_level = 1;
0792     else
0793         min_level = 0;
0794
0795     hwmgr->default_compute_power_profile.min_sclk =
0796             dpm_table->dpm_levels[min_level].value;
0797
0798     hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
0799     hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
0800
0801     return 0;
0802 }
0803 #endif
0804
0805 /**
0806  * vega12_init_smc_table - Initializes the SMC table and uploads it
0807  *
0808  * @hwmgr:  the address of the powerplay hardware manager.
0809  * return:  always 0
0810  */
0811 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
0812 {
0813     int result;
0814     struct vega12_hwmgr *data =
0815             (struct vega12_hwmgr *)(hwmgr->backend);
0816     PPTable_t *pp_table = &(data->smc_state_table.pp_table);
0817     struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
0818     struct phm_ppt_v3_information *pptable_information =
0819         (struct phm_ppt_v3_information *)hwmgr->pptable;
0820
0821     result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
0822     if (!result) {
0823         data->vbios_boot_state.vddc     = boot_up_values.usVddc;
0824         data->vbios_boot_state.vddci    = boot_up_values.usVddci;
0825         data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
0826         data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
0827         data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
0828         data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
0829         data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
0830         data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
0831         data->vbios_boot_state.eclock = boot_up_values.ulEClk;
0832         data->vbios_boot_state.dclock = boot_up_values.ulDClk;
0833         data->vbios_boot_state.vclock = boot_up_values.ulVClk;
0834         smum_send_msg_to_smc_with_parameter(hwmgr,
0835                 PPSMC_MSG_SetMinDeepSleepDcefclk,
0836             (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
0837                 NULL);
0838     }
0839
0840     memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
0841
0842     result = smum_smc_table_manager(hwmgr,
0843                     (uint8_t *)pp_table, TABLE_PPTABLE, false);
0844     PP_ASSERT_WITH_CODE(!result,
0845             "Failed to upload PPtable!", return result);
0846
0847     return 0;
0848 }
0849
0850 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
0851 {
0852     uint32_t result;
0853
0854     PP_ASSERT_WITH_CODE(
0855         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0,
0856         "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
0857         return -EINVAL);
0858
0859     PP_ASSERT_WITH_CODE(result == 1,
0860             "Failed to run ACG BTC!", return -EINVAL);
0861
0862     return 0;
0863 }
0864
0865 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
0866 {
0867     struct vega12_hwmgr *data =
0868             (struct vega12_hwmgr *)(hwmgr->backend);
0869     int i;
0870     uint32_t allowed_features_low = 0, allowed_features_high = 0;
0871
0872     for (i = 0; i < GNLD_FEATURES_MAX; i++)
0873         if (data->smu_features[i].allowed)
0874             data->smu_features[i].smu_feature_id > 31 ?
0875                 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
0876                 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
0877
0878     PP_ASSERT_WITH_CODE(
0879         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high,
0880             NULL) == 0,
0881         "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
0882         return -1);
0883
0884     PP_ASSERT_WITH_CODE(
0885         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low,
0886             NULL) == 0,
0887         "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
0888         return -1);
0889
0890     return 0;
0891 }
0892
0893 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
0894 {
0895     struct vega12_hwmgr *data =
0896             (struct vega12_hwmgr *)(hwmgr->backend);
0897
0898     data->uvd_power_gated = true;
0899     data->vce_power_gated = true;
0900
0901     if (data->smu_features[GNLD_DPM_UVD].enabled)
0902         data->uvd_power_gated = false;
0903
0904     if (data->smu_features[GNLD_DPM_VCE].enabled)
0905         data->vce_power_gated = false;
0906 }
0907
0908 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
0909 {
0910     struct vega12_hwmgr *data =
0911             (struct vega12_hwmgr *)(hwmgr->backend);
0912     uint64_t features_enabled;
0913     int i;
0914     bool enabled;
0915
0916     PP_ASSERT_WITH_CODE(
0917         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0,
0918         "[EnableAllSMUFeatures] Failed to enable all smu features!",
0919         return -1);
0920
0921     if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
0922         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
0923             enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
0924             data->smu_features[i].enabled = enabled;
0925             data->smu_features[i].supported = enabled;
0926         }
0927     }
0928
0929     vega12_init_powergate_state(hwmgr);
0930
0931     return 0;
0932 }
0933
0934 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
0935 {
0936     struct vega12_hwmgr *data =
0937             (struct vega12_hwmgr *)(hwmgr->backend);
0938     uint64_t features_enabled;
0939     int i;
0940     bool enabled;
0941
0942     PP_ASSERT_WITH_CODE(
0943         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0,
0944         "[DisableAllSMUFeatures] Failed to disable all smu features!",
0945         return -1);
0946
0947     if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
0948         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
0949             enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
0950             data->smu_features[i].enabled = enabled;
0951             data->smu_features[i].supported = enabled;
0952         }
0953     }
0954
0955     return 0;
0956 }
0957
0958 static int vega12_odn_initialize_default_settings(
0959         struct pp_hwmgr *hwmgr)
0960 {
0961     return 0;
0962 }
0963
0964 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
0965         uint32_t adjust_percent)
0966 {
0967     return smum_send_msg_to_smc_with_parameter(hwmgr,
0968             PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
0969             NULL);
0970 }
0971
0972 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
0973 {
0974     int adjust_percent, result = 0;
0975
0976     if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
0977         adjust_percent =
0978                 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
0979                 hwmgr->platform_descriptor.TDPAdjustment :
0980                 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
0981         result = vega12_set_overdrive_target_percentage(hwmgr,
0982                 (uint32_t)adjust_percent);
0983     }
0984     return result;
0985 }
0986
0987 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
0988         PPCLK_e clkid, struct vega12_clock_range *clock)
0989 {
0990     /* AC Max */
0991     PP_ASSERT_WITH_CODE(
0992         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16),
0993             &(clock->ACMax)) == 0,
0994         "[GetClockRanges] Failed to get max ac clock from SMC!",
0995         return -EINVAL);
0996
0997     /* AC Min */
0998     PP_ASSERT_WITH_CODE(
0999         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16),
1000             &(clock->ACMin)) == 0,
1001         "[GetClockRanges] Failed to get min ac clock from SMC!",
1002         return -EINVAL);
1003
1004     /* DC Max */
1005     PP_ASSERT_WITH_CODE(
1006         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16),
1007             &(clock->DCMax)) == 0,
1008         "[GetClockRanges] Failed to get max dc clock from SMC!",
1009         return -EINVAL);
1010
1011     return 0;
1012 }
1013
1014 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
1015 {
1016     struct vega12_hwmgr *data =
1017             (struct vega12_hwmgr *)(hwmgr->backend);
1018     uint32_t i;
1019
1020     for (i = 0; i < PPCLK_COUNT; i++)
1021         PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
1022                     i, &(data->clk_range[i])),
1023                 "Failed to get clk range from SMC!",
1024                 return -EINVAL);
1025
1026     return 0;
1027 }
1028
1029 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1030 {
1031     int tmp_result, result = 0;
1032
1033     smum_send_msg_to_smc_with_parameter(hwmgr,
1034             PPSMC_MSG_NumOfDisplays, 0, NULL);
1035
1036     result = vega12_set_allowed_featuresmask(hwmgr);
1037     PP_ASSERT_WITH_CODE(result == 0,
1038             "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1039             return result);
1040
1041     tmp_result = vega12_init_smc_table(hwmgr);
1042     PP_ASSERT_WITH_CODE(!tmp_result,
1043             "Failed to initialize SMC table!",
1044             result = tmp_result);
1045
1046     tmp_result = vega12_run_acg_btc(hwmgr);
1047     PP_ASSERT_WITH_CODE(!tmp_result,
1048             "Failed to run ACG BTC!",
1049             result = tmp_result);
1050
1051     result = vega12_enable_all_smu_features(hwmgr);
1052     PP_ASSERT_WITH_CODE(!result,
1053             "Failed to enable all smu features!",
1054             return result);
1055
1056     result = vega12_override_pcie_parameters(hwmgr);
1057     PP_ASSERT_WITH_CODE(!result,
1058             "[EnableDPMTasks] Failed to override pcie parameters!",
1059             return result);
1060
1061     tmp_result = vega12_power_control_set_level(hwmgr);
1062     PP_ASSERT_WITH_CODE(!tmp_result,
1063             "Failed to power control set level!",
1064             result = tmp_result);
1065
1066     result = vega12_get_all_clock_ranges(hwmgr);
1067     PP_ASSERT_WITH_CODE(!result,
1068             "Failed to get all clock ranges!",
1069             return result);
1070
1071     result = vega12_odn_initialize_default_settings(hwmgr);
1072     PP_ASSERT_WITH_CODE(!result,
1073             "Failed to power control set level!",
1074             return result);
1075
1076     result = vega12_setup_default_dpm_tables(hwmgr);
1077     PP_ASSERT_WITH_CODE(!result,
1078             "Failed to setup default DPM tables!",
1079             return result);
1080     return result;
1081 }
1082
1083 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
1084          struct pp_hw_power_state *hw_ps)
1085 {
1086     return 0;
1087 }
1088
1089 static uint32_t vega12_find_lowest_dpm_level(
1090         struct vega12_single_dpm_table *table)
1091 {
1092     uint32_t i;
1093
1094     for (i = 0; i < table->count; i++) {
1095         if (table->dpm_levels[i].enabled)
1096             break;
1097     }
1098
1099     if (i >= table->count) {
1100         i = 0;
1101         table->dpm_levels[i].enabled = true;
1102     }
1103
1104     return i;
1105 }
1106
1107 static uint32_t vega12_find_highest_dpm_level(
1108         struct vega12_single_dpm_table *table)
1109 {
1110     int32_t i = 0;
1111     PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1112             "[FindHighestDPMLevel] DPM Table has too many entries!",
1113             return MAX_REGULAR_DPM_NUMBER - 1);
1114
1115     for (i = table->count - 1; i >= 0; i--) {
1116         if (table->dpm_levels[i].enabled)
1117             break;
1118     }
1119
1120     if (i < 0) {
1121         i = 0;
1122         table->dpm_levels[i].enabled = true;
1123     }
1124
1125     return (uint32_t)i;
1126 }
1127
1128 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1129 {
1130     struct vega12_hwmgr *data = hwmgr->backend;
1131     uint32_t min_freq;
1132     int ret = 0;
1133
1134     if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1135         min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1136         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1137                     hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1138                     (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1139                     NULL)),
1140                     "Failed to set soft min gfxclk !",
1141                     return ret);
1142     }
1143
1144     if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1145         min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1146         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1147                     hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1148                     (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1149                     NULL)),
1150                     "Failed to set soft min memclk !",
1151                     return ret);
1152
1153         min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1154         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1155                     hwmgr, PPSMC_MSG_SetHardMinByFreq,
1156                     (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1157                     NULL)),
1158                     "Failed to set hard min memclk !",
1159                     return ret);
1160     }
1161
1162     if (data->smu_features[GNLD_DPM_UVD].enabled) {
1163         min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1164
1165         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1166                     hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1167                     (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1168                     NULL)),
1169                     "Failed to set soft min vclk!",
1170                     return ret);
1171
1172         min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1173
1174         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1175                     hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1176                     (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1177                     NULL)),
1178                     "Failed to set soft min dclk!",
1179                     return ret);
1180     }
1181
1182     if (data->smu_features[GNLD_DPM_VCE].enabled) {
1183         min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1184
1185         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1186                     hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1187                     (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1188                     NULL)),
1189                     "Failed to set soft min eclk!",
1190                     return ret);
1191     }
1192
1193     if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1194         min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1195
1196         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1197                     hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1198                     (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1199                     NULL)),
1200                     "Failed to set soft min socclk!",
1201                     return ret);
1202     }
1203
1204     if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1205         min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1206
1207         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1208                     hwmgr, PPSMC_MSG_SetHardMinByFreq,
1209                     (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1210                     NULL)),
1211                     "Failed to set hard min dcefclk!",
1212                     return ret);
1213     }
1214
1215     return ret;
1216
1217 }
1218
1219 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1220 {
1221     struct vega12_hwmgr *data = hwmgr->backend;
1222     uint32_t max_freq;
1223     int ret = 0;
1224
1225     if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1226         max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1227
1228         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1229                     hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1230                     (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1231                     NULL)),
1232                     "Failed to set soft max gfxclk!",
1233                     return ret);
1234     }
1235
1236     if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1237         max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1238
1239         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1240                     hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1241                     (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1242                     NULL)),
1243                     "Failed to set soft max memclk!",
1244                     return ret);
1245     }
1246
1247     if (data->smu_features[GNLD_DPM_UVD].enabled) {
1248         max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1249
1250         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1251                     hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1252                     (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1253                     NULL)),
1254                     "Failed to set soft max vclk!",
1255                     return ret);
1256
1257         max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1258         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1259                     hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1260                     (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1261                     NULL)),
1262                     "Failed to set soft max dclk!",
1263                     return ret);
1264     }
1265
1266     if (data->smu_features[GNLD_DPM_VCE].enabled) {
1267         max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1268
1269         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1270                     hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1271                     (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1272                     NULL)),
1273                     "Failed to set soft max eclk!",
1274                     return ret);
1275     }
1276
1277     if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1278         max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1279
1280         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1281                     hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1282                     (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1283                     NULL)),
1284                     "Failed to set soft max socclk!",
1285                     return ret);
1286     }
1287
1288     return ret;
1289 }
1290
1291 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1292 {
1293     struct vega12_hwmgr *data =
1294             (struct vega12_hwmgr *)(hwmgr->backend);
1295
1296     if (data->smu_features[GNLD_DPM_VCE].supported) {
1297         PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1298                 enable,
1299                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1300                 "Attempt to Enable/Disable DPM VCE Failed!",
1301                 return -1);
1302         data->smu_features[GNLD_DPM_VCE].enabled = enable;
1303     }
1304
1305     return 0;
1306 }
1307
1308 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1309 {
1310     struct vega12_hwmgr *data =
1311             (struct vega12_hwmgr *)(hwmgr->backend);
1312     uint32_t gfx_clk;
1313
1314     if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1315         return -1;
1316
1317     if (low)
1318         PP_ASSERT_WITH_CODE(
1319             vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1320             "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1321             return -1);
1322     else
1323         PP_ASSERT_WITH_CODE(
1324             vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1325             "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1326             return -1);
1327
1328     return (gfx_clk * 100);
1329 }
1330
1331 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1332 {
1333     struct vega12_hwmgr *data =
1334             (struct vega12_hwmgr *)(hwmgr->backend);
1335     uint32_t mem_clk;
1336
1337     if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1338         return -1;
1339
1340     if (low)
1341         PP_ASSERT_WITH_CODE(
1342             vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1343             "[GetMclks]: fail to get min PPCLK_UCLK\n",
1344             return -1);
1345     else
1346         PP_ASSERT_WITH_CODE(
1347             vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1348             "[GetMclks]: fail to get max PPCLK_UCLK\n",
1349             return -1);
1350
1351     return (mem_clk * 100);
1352 }
1353
1354 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr,
1355                     SmuMetrics_t *metrics_table,
1356                     bool bypass_cache)
1357 {
1358     struct vega12_hwmgr *data =
1359             (struct vega12_hwmgr *)(hwmgr->backend);
1360     int ret = 0;
1361
1362     if (bypass_cache ||
1363         !data->metrics_time ||
1364         time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
1365         ret = smum_smc_table_manager(hwmgr,
1366                          (uint8_t *)(&data->metrics_table),
1367                          TABLE_SMU_METRICS,
1368                          true);
1369         if (ret) {
1370             pr_info("Failed to export SMU metrics table!\n");
1371             return ret;
1372         }
1373         data->metrics_time = jiffies;
1374     }
1375
1376     if (metrics_table)
1377         memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
1378
1379     return ret;
1380 }
1381
1382 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1383 {
1384     SmuMetrics_t metrics_table;
1385     int ret = 0;
1386
1387     ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1388     if (ret)
1389         return ret;
1390
1391     *query = metrics_table.CurrSocketPower << 8;
1392
1393     return ret;
1394 }
1395
1396 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1397 {
1398     uint32_t gfx_clk = 0;
1399
1400     *gfx_freq = 0;
1401
1402     PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1403             PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16),
1404             &gfx_clk) == 0,
1405             "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1406             return -EINVAL);
1407
1408     *gfx_freq = gfx_clk * 100;
1409
1410     return 0;
1411 }
1412
1413 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1414 {
1415     uint32_t mem_clk = 0;
1416
1417     *mclk_freq = 0;
1418
1419     PP_ASSERT_WITH_CODE(
1420             smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),
1421                 &mem_clk) == 0,
1422             "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1423             return -EINVAL);
1424
1425     *mclk_freq = mem_clk * 100;
1426
1427     return 0;
1428 }
1429
1430 static int vega12_get_current_activity_percent(
1431         struct pp_hwmgr *hwmgr,
1432         int idx,
1433         uint32_t *activity_percent)
1434 {
1435     SmuMetrics_t metrics_table;
1436     int ret = 0;
1437
1438     ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1439     if (ret)
1440         return ret;
1441
1442     switch (idx) {
1443     case AMDGPU_PP_SENSOR_GPU_LOAD:
1444         *activity_percent = metrics_table.AverageGfxActivity;
1445         break;
1446     case AMDGPU_PP_SENSOR_MEM_LOAD:
1447         *activity_percent = metrics_table.AverageUclkActivity;
1448         break;
1449     default:
1450         pr_err("Invalid index for retrieving clock activity\n");
1451         return -EINVAL;
1452     }
1453
1454     return ret;
1455 }
1456
1457 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1458                   void *value, int *size)
1459 {
1460     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1461     SmuMetrics_t metrics_table;
1462     int ret = 0;
1463
1464     switch (idx) {
1465     case AMDGPU_PP_SENSOR_GFX_SCLK:
1466         ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1467         if (!ret)
1468             *size = 4;
1469         break;
1470     case AMDGPU_PP_SENSOR_GFX_MCLK:
1471         ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1472         if (!ret)
1473             *size = 4;
1474         break;
1475     case AMDGPU_PP_SENSOR_GPU_LOAD:
1476     case AMDGPU_PP_SENSOR_MEM_LOAD:
1477         ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
1478         if (!ret)
1479             *size = 4;
1480         break;
1481     case AMDGPU_PP_SENSOR_GPU_TEMP:
1482         *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1483         *size = 4;
1484         break;
1485     case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1486         ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1487         if (ret)
1488             return ret;
1489
1490         *((uint32_t *)value) = metrics_table.TemperatureHotspot *
1491             PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1492         *size = 4;
1493         break;
1494     case AMDGPU_PP_SENSOR_MEM_TEMP:
1495         ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1496         if (ret)
1497             return ret;
1498
1499         *((uint32_t *)value) = metrics_table.TemperatureHBM *
1500             PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1501         *size = 4;
1502         break;
1503     case AMDGPU_PP_SENSOR_UVD_POWER:
1504         *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1505         *size = 4;
1506         break;
1507     case AMDGPU_PP_SENSOR_VCE_POWER:
1508         *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1509         *size = 4;
1510         break;
1511     case AMDGPU_PP_SENSOR_GPU_POWER:
1512         ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1513         if (!ret)
1514             *size = 4;
1515         break;
1516     case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1517         ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1518         if (!ret)
1519             *size = 8;
1520         break;
1521     default:
1522         ret = -EOPNOTSUPP;
1523         break;
1524     }
1525     return ret;
1526 }
1527
1528 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1529         bool has_disp)
1530 {
1531     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1532
1533     if (data->smu_features[GNLD_DPM_UCLK].enabled)
1534         return smum_send_msg_to_smc_with_parameter(hwmgr,
1535             PPSMC_MSG_SetUclkFastSwitch,
1536             has_disp ? 1 : 0,
1537             NULL);
1538
1539     return 0;
1540 }
1541
1542 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1543         struct pp_display_clock_request *clock_req)
1544 {
1545     int result = 0;
1546     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1547     enum amd_pp_clock_type clk_type = clock_req->clock_type;
1548     uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1549     PPCLK_e clk_select = 0;
1550     uint32_t clk_request = 0;
1551
1552     if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1553         switch (clk_type) {
1554         case amd_pp_dcef_clock:
1555             clk_select = PPCLK_DCEFCLK;
1556             break;
1557         case amd_pp_disp_clock:
1558             clk_select = PPCLK_DISPCLK;
1559             break;
1560         case amd_pp_pixel_clock:
1561             clk_select = PPCLK_PIXCLK;
1562             break;
1563         case amd_pp_phy_clock:
1564             clk_select = PPCLK_PHYCLK;
1565             break;
1566         default:
1567             pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1568             result = -1;
1569             break;
1570         }
1571
1572         if (!result) {
1573             clk_request = (clk_select << 16) | clk_freq;
1574             result = smum_send_msg_to_smc_with_parameter(hwmgr,
1575                     PPSMC_MSG_SetHardMinByFreq,
1576                     clk_request,
1577                     NULL);
1578         }
1579     }
1580
1581     return result;
1582 }
1583
1584 static int vega12_notify_smc_display_config_after_ps_adjustment(
1585         struct pp_hwmgr *hwmgr)
1586 {
1587     struct vega12_hwmgr *data =
1588             (struct vega12_hwmgr *)(hwmgr->backend);
1589     struct PP_Clocks min_clocks = {0};
1590     struct pp_display_clock_request clock_req;
1591
1592     if ((hwmgr->display_config->num_display > 1) &&
1593          !hwmgr->display_config->multi_monitor_in_sync &&
1594          !hwmgr->display_config->nb_pstate_switch_disable)
1595         vega12_notify_smc_display_change(hwmgr, false);
1596     else
1597         vega12_notify_smc_display_change(hwmgr, true);
1598
1599     min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1600     min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1601     min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1602
1603     if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1604         clock_req.clock_type = amd_pp_dcef_clock;
1605         clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1606         if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1607             if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1608                 PP_ASSERT_WITH_CODE(
1609                     !smum_send_msg_to_smc_with_parameter(
1610                     hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1611                     min_clocks.dcefClockInSR /100,
1612                     NULL),
1613                     "Attempt to set divider for DCEFCLK Failed!",
1614                     return -1);
1615         } else {
1616             pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1617         }
1618     }
1619
1620     return 0;
1621 }
1622
1623 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1624 {
1625     struct vega12_hwmgr *data =
1626             (struct vega12_hwmgr *)(hwmgr->backend);
1627
1628     uint32_t soft_level;
1629
1630     soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1631
1632     data->dpm_table.gfx_table.dpm_state.soft_min_level =
1633         data->dpm_table.gfx_table.dpm_state.soft_max_level =
1634         data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1635
1636     soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1637
1638     data->dpm_table.mem_table.dpm_state.soft_min_level =
1639         data->dpm_table.mem_table.dpm_state.soft_max_level =
1640         data->dpm_table.mem_table.dpm_levels[soft_level].value;
1641
1642     PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1643             "Failed to upload boot level to highest!",
1644             return -1);
1645
1646     PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1647             "Failed to upload dpm max level to highest!",
1648             return -1);
1649
1650     return 0;
1651 }
1652
1653 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1654 {
1655     struct vega12_hwmgr *data =
1656             (struct vega12_hwmgr *)(hwmgr->backend);
1657     uint32_t soft_level;
1658
1659     soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1660
1661     data->dpm_table.gfx_table.dpm_state.soft_min_level =
1662         data->dpm_table.gfx_table.dpm_state.soft_max_level =
1663         data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1664
1665     soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1666
1667     data->dpm_table.mem_table.dpm_state.soft_min_level =
1668         data->dpm_table.mem_table.dpm_state.soft_max_level =
1669         data->dpm_table.mem_table.dpm_levels[soft_level].value;
1670
1671     PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1672             "Failed to upload boot level to highest!",
1673             return -1);
1674
1675     PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1676             "Failed to upload dpm max level to highest!",
1677             return -1);
1678
1679     return 0;
1680
1681 }
1682
1683 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1684 {
1685     PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1686             "Failed to upload DPM Bootup Levels!",
1687             return -1);
1688
1689     PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1690             "Failed to upload DPM Max Levels!",
1691             return -1);
1692
1693     return 0;
1694 }
1695
1696 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1697                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1698 {
1699     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1700     struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1701     struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1702     struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1703
1704     *sclk_mask = 0;
1705     *mclk_mask = 0;
1706     *soc_mask  = 0;
1707
1708     if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1709         mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1710         soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1711         *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1712         *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1713         *soc_mask  = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1714     }
1715
1716     if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1717         *sclk_mask = 0;
1718     } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1719         *mclk_mask = 0;
1720     } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1721         *sclk_mask = gfx_dpm_table->count - 1;
1722         *mclk_mask = mem_dpm_table->count - 1;
1723         *soc_mask  = soc_dpm_table->count - 1;
1724     }
1725
1726     return 0;
1727 }
1728
1729 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1730 {
1731     switch (mode) {
1732     case AMD_FAN_CTRL_NONE:
1733         break;
1734     case AMD_FAN_CTRL_MANUAL:
1735         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1736             vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1737         break;
1738     case AMD_FAN_CTRL_AUTO:
1739         if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1740             vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1741         break;
1742     default:
1743         break;
1744     }
1745 }
1746
1747 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1748                 enum amd_dpm_forced_level level)
1749 {
1750     int ret = 0;
1751     uint32_t sclk_mask = 0;
1752     uint32_t mclk_mask = 0;
1753     uint32_t soc_mask = 0;
1754
1755     switch (level) {
1756     case AMD_DPM_FORCED_LEVEL_HIGH:
1757         ret = vega12_force_dpm_highest(hwmgr);
1758         break;
1759     case AMD_DPM_FORCED_LEVEL_LOW:
1760         ret = vega12_force_dpm_lowest(hwmgr);
1761         break;
1762     case AMD_DPM_FORCED_LEVEL_AUTO:
1763         ret = vega12_unforce_dpm_levels(hwmgr);
1764         break;
1765     case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1766     case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1767     case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1768     case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1769         ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1770         if (ret)
1771             return ret;
1772         vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1773         vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1774         break;
1775     case AMD_DPM_FORCED_LEVEL_MANUAL:
1776     case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1777     default:
1778         break;
1779     }
1780
1781     return ret;
1782 }
1783
1784 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1785 {
1786     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1787
1788     if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1789         return AMD_FAN_CTRL_MANUAL;
1790     else
1791         return AMD_FAN_CTRL_AUTO;
1792 }
1793
1794 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1795         struct amd_pp_simple_clock_info *info)
1796 {
1797 #if 0
1798     struct phm_ppt_v2_information *table_info =
1799             (struct phm_ppt_v2_information *)hwmgr->pptable;
1800     struct phm_clock_and_voltage_limits *max_limits =
1801             &table_info->max_clock_voltage_on_ac;
1802
1803     info->engine_max_clock = max_limits->sclk;
1804     info->memory_max_clock = max_limits->mclk;
1805 #endif
1806     return 0;
1807 }
1808
1809 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1810         uint32_t *clock,
1811         PPCLK_e clock_select,
1812         bool max)
1813 {
1814     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1815
1816     if (max)
1817         *clock = data->clk_range[clock_select].ACMax;
1818     else
1819         *clock = data->clk_range[clock_select].ACMin;
1820
1821     return 0;
1822 }
1823
1824 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1825         struct pp_clock_levels_with_latency *clocks)
1826 {
1827     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1828     uint32_t ucount;
1829     int i;
1830     struct vega12_single_dpm_table *dpm_table;
1831
1832     if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1833         return -1;
1834
1835     dpm_table = &(data->dpm_table.gfx_table);
1836     ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1837         MAX_NUM_CLOCKS : dpm_table->count;
1838
1839     for (i = 0; i < ucount; i++) {
1840         clocks->data[i].clocks_in_khz =
1841             dpm_table->dpm_levels[i].value * 1000;
1842
1843         clocks->data[i].latency_in_us = 0;
1844     }
1845
1846     clocks->num_levels = ucount;
1847
1848     return 0;
1849 }
1850
1851 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1852         uint32_t clock)
1853 {
1854     return 25;
1855 }
1856
1857 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1858         struct pp_clock_levels_with_latency *clocks)
1859 {
1860     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1861     uint32_t ucount;
1862     int i;
1863     struct vega12_single_dpm_table *dpm_table;
1864     if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1865         return -1;
1866
1867     dpm_table = &(data->dpm_table.mem_table);
1868     ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1869         MAX_NUM_CLOCKS : dpm_table->count;
1870
1871     for (i = 0; i < ucount; i++) {
1872         clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1873         data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1874         clocks->data[i].latency_in_us =
1875             data->mclk_latency_table.entries[i].latency =
1876             vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1877     }
1878
1879     clocks->num_levels = data->mclk_latency_table.count = ucount;
1880
1881     return 0;
1882 }
1883
1884 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1885         struct pp_clock_levels_with_latency *clocks)
1886 {
1887     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1888     uint32_t ucount;
1889     int i;
1890     struct vega12_single_dpm_table *dpm_table;
1891
1892     if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1893         return -1;
1894
1895
1896     dpm_table = &(data->dpm_table.dcef_table);
1897     ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1898         MAX_NUM_CLOCKS : dpm_table->count;
1899
1900     for (i = 0; i < ucount; i++) {
1901         clocks->data[i].clocks_in_khz =
1902             dpm_table->dpm_levels[i].value * 1000;
1903
1904         clocks->data[i].latency_in_us = 0;
1905     }
1906
1907     clocks->num_levels = ucount;
1908
1909     return 0;
1910 }
1911
1912 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1913         struct pp_clock_levels_with_latency *clocks)
1914 {
1915     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1916     uint32_t ucount;
1917     int i;
1918     struct vega12_single_dpm_table *dpm_table;
1919
1920     if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1921         return -1;
1922
1923
1924     dpm_table = &(data->dpm_table.soc_table);
1925     ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1926         MAX_NUM_CLOCKS : dpm_table->count;
1927
1928     for (i = 0; i < ucount; i++) {
1929         clocks->data[i].clocks_in_khz =
1930             dpm_table->dpm_levels[i].value * 1000;
1931
1932         clocks->data[i].latency_in_us = 0;
1933     }
1934
1935     clocks->num_levels = ucount;
1936
1937     return 0;
1938
1939 }
1940
1941 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1942         enum amd_pp_clock_type type,
1943         struct pp_clock_levels_with_latency *clocks)
1944 {
1945     int ret;
1946
1947     switch (type) {
1948     case amd_pp_sys_clock:
1949         ret = vega12_get_sclks(hwmgr, clocks);
1950         break;
1951     case amd_pp_mem_clock:
1952         ret = vega12_get_memclocks(hwmgr, clocks);
1953         break;
1954     case amd_pp_dcef_clock:
1955         ret = vega12_get_dcefclocks(hwmgr, clocks);
1956         break;
1957     case amd_pp_soc_clock:
1958         ret = vega12_get_socclocks(hwmgr, clocks);
1959         break;
1960     default:
1961         return -EINVAL;
1962     }
1963
1964     return ret;
1965 }
1966
1967 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1968         enum amd_pp_clock_type type,
1969         struct pp_clock_levels_with_voltage *clocks)
1970 {
1971     clocks->num_levels = 0;
1972
1973     return 0;
1974 }
1975
1976 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1977                             void *clock_ranges)
1978 {
1979     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1980     Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1981     struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1982
1983     if (!data->registry_data.disable_water_mark &&
1984             data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1985             data->smu_features[GNLD_DPM_SOCCLK].supported) {
1986         smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1987         data->water_marks_bitmap |= WaterMarksExist;
1988         data->water_marks_bitmap &= ~WaterMarksLoaded;
1989     }
1990
1991     return 0;
1992 }
1993
1994 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1995         enum pp_clock_type type, uint32_t mask)
1996 {
1997     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1998     uint32_t soft_min_level, soft_max_level, hard_min_level;
1999     int ret = 0;
2000
2001     switch (type) {
2002     case PP_SCLK:
2003         soft_min_level = mask ? (ffs(mask) - 1) : 0;
2004         soft_max_level = mask ? (fls(mask) - 1) : 0;
2005
2006         data->dpm_table.gfx_table.dpm_state.soft_min_level =
2007             data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2008         data->dpm_table.gfx_table.dpm_state.soft_max_level =
2009             data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2010
2011         ret = vega12_upload_dpm_min_level(hwmgr);
2012         PP_ASSERT_WITH_CODE(!ret,
2013             "Failed to upload boot level to lowest!",
2014             return ret);
2015
2016         ret = vega12_upload_dpm_max_level(hwmgr);
2017         PP_ASSERT_WITH_CODE(!ret,
2018             "Failed to upload dpm max level to highest!",
2019             return ret);
2020         break;
2021
2022     case PP_MCLK:
2023         soft_min_level = mask ? (ffs(mask) - 1) : 0;
2024         soft_max_level = mask ? (fls(mask) - 1) : 0;
2025
2026         data->dpm_table.mem_table.dpm_state.soft_min_level =
2027             data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2028         data->dpm_table.mem_table.dpm_state.soft_max_level =
2029             data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2030
2031         ret = vega12_upload_dpm_min_level(hwmgr);
2032         PP_ASSERT_WITH_CODE(!ret,
2033             "Failed to upload boot level to lowest!",
2034             return ret);
2035
2036         ret = vega12_upload_dpm_max_level(hwmgr);
2037         PP_ASSERT_WITH_CODE(!ret,
2038             "Failed to upload dpm max level to highest!",
2039             return ret);
2040
2041         break;
2042
2043     case PP_SOCCLK:
2044         soft_min_level = mask ? (ffs(mask) - 1) : 0;
2045         soft_max_level = mask ? (fls(mask) - 1) : 0;
2046
2047         if (soft_max_level >= data->dpm_table.soc_table.count) {
2048             pr_err("Clock level specified %d is over max allowed %d\n",
2049                     soft_max_level,
2050                     data->dpm_table.soc_table.count - 1);
2051             return -EINVAL;
2052         }
2053
2054         data->dpm_table.soc_table.dpm_state.soft_min_level =
2055             data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2056         data->dpm_table.soc_table.dpm_state.soft_max_level =
2057             data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2058
2059         ret = vega12_upload_dpm_min_level(hwmgr);
2060         PP_ASSERT_WITH_CODE(!ret,
2061             "Failed to upload boot level to lowest!",
2062             return ret);
2063
2064         ret = vega12_upload_dpm_max_level(hwmgr);
2065         PP_ASSERT_WITH_CODE(!ret,
2066             "Failed to upload dpm max level to highest!",
2067             return ret);
2068
2069         break;
2070
2071     case PP_DCEFCLK:
2072         hard_min_level = mask ? (ffs(mask) - 1) : 0;
2073
2074         if (hard_min_level >= data->dpm_table.dcef_table.count) {
2075             pr_err("Clock level specified %d is over max allowed %d\n",
2076                     hard_min_level,
2077                     data->dpm_table.dcef_table.count - 1);
2078             return -EINVAL;
2079         }
2080
2081         data->dpm_table.dcef_table.dpm_state.hard_min_level =
2082             data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2083
2084         ret = vega12_upload_dpm_min_level(hwmgr);
2085         PP_ASSERT_WITH_CODE(!ret,
2086             "Failed to upload boot level to lowest!",
2087             return ret);
2088
2089         //TODO: Setting DCEFCLK max dpm level is not supported
2090
2091         break;
2092
2093     case PP_PCIE:
2094         break;
2095
2096     default:
2097         break;
2098     }
2099
2100     return 0;
2101 }
2102
2103 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2104 {
2105     static const char *ppfeature_name[] = {
2106             "DPM_PREFETCHER",
2107             "GFXCLK_DPM",
2108             "UCLK_DPM",
2109             "SOCCLK_DPM",
2110             "UVD_DPM",
2111             "VCE_DPM",
2112             "ULV",
2113             "MP0CLK_DPM",
2114             "LINK_DPM",
2115             "DCEFCLK_DPM",
2116             "GFXCLK_DS",
2117             "SOCCLK_DS",
2118             "LCLK_DS",
2119             "PPT",
2120             "TDC",
2121             "THERMAL",
2122             "GFX_PER_CU_CG",
2123             "RM",
2124             "DCEFCLK_DS",
2125             "ACDC",
2126             "VR0HOT",
2127             "VR1HOT",
2128             "FW_CTF",
2129             "LED_DISPLAY",
2130             "FAN_CONTROL",
2131             "DIDT",
2132             "GFXOFF",
2133             "CG",
2134             "ACG"};
2135     static const char *output_title[] = {
2136             "FEATURES",
2137             "BITMASK",
2138             "ENABLEMENT"};
2139     uint64_t features_enabled;
2140     int i;
2141     int ret = 0;
2142     int size = 0;
2143
2144     phm_get_sysfs_buf(&buf, &size);
2145
2146     ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2147     PP_ASSERT_WITH_CODE(!ret,
2148         "[EnableAllSmuFeatures] Failed to get enabled smc features!",
2149         return ret);
2150
2151     size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2152     size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
2153                 output_title[0],
2154                 output_title[1],
2155                 output_title[2]);
2156     for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2157         size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
2158                 ppfeature_name[i],
2159                 1ULL << i,
2160                 (features_enabled & (1ULL << i)) ? "Y" : "N");
2161     }
2162
2163     return size;
2164 }
2165
2166 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
2167 {
2168     uint64_t features_enabled;
2169     uint64_t features_to_enable;
2170     uint64_t features_to_disable;
2171     int ret = 0;
2172
2173     if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2174         return -EINVAL;
2175
2176     ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2177     if (ret)
2178         return ret;
2179
2180     features_to_disable =
2181         features_enabled & ~new_ppfeature_masks;
2182     features_to_enable =
2183         ~features_enabled & new_ppfeature_masks;
2184
2185     pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2186     pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2187
2188     if (features_to_disable) {
2189         ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
2190         if (ret)
2191             return ret;
2192     }
2193
2194     if (features_to_enable) {
2195         ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
2196         if (ret)
2197             return ret;
2198     }
2199
2200     return 0;
2201 }
2202
2203 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
2204 {
2205     struct amdgpu_device *adev = hwmgr->adev;
2206
2207     return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2208         PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2209         >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2210 }
2211
2212 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
2213 {
2214     uint32_t width_level;
2215
2216     width_level = vega12_get_current_pcie_link_width_level(hwmgr);
2217     if (width_level > LINK_WIDTH_MAX)
2218         width_level = 0;
2219
2220     return link_width[width_level];
2221 }
2222
2223 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
2224 {
2225     struct amdgpu_device *adev = hwmgr->adev;
2226
2227     return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2228         PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2229         >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2230 }
2231
2232 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
2233 {
2234     uint32_t speed_level;
2235
2236     speed_level = vega12_get_current_pcie_link_speed_level(hwmgr);
2237     if (speed_level > LINK_SPEED_MAX)
2238         speed_level = 0;
2239
2240     return link_speed[speed_level];
2241 }
2242
2243 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
2244         enum pp_clock_type type, char *buf)
2245 {
2246     int i, now, size = 0;
2247     struct pp_clock_levels_with_latency clocks;
2248
2249     switch (type) {
2250     case PP_SCLK:
2251         PP_ASSERT_WITH_CODE(
2252                 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
2253                 "Attempt to get current gfx clk Failed!",
2254                 return -1);
2255
2256         PP_ASSERT_WITH_CODE(
2257                 vega12_get_sclks(hwmgr, &clocks) == 0,
2258                 "Attempt to get gfx clk levels Failed!",
2259                 return -1);
2260         for (i = 0; i < clocks.num_levels; i++)
2261             size += sprintf(buf + size, "%d: %uMhz %s\n",
2262                 i, clocks.data[i].clocks_in_khz / 1000,
2263                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2264         break;
2265
2266     case PP_MCLK:
2267         PP_ASSERT_WITH_CODE(
2268                 vega12_get_current_mclk_freq(hwmgr, &now) == 0,
2269                 "Attempt to get current mclk freq Failed!",
2270                 return -1);
2271
2272         PP_ASSERT_WITH_CODE(
2273                 vega12_get_memclocks(hwmgr, &clocks) == 0,
2274                 "Attempt to get memory clk levels Failed!",
2275                 return -1);
2276         for (i = 0; i < clocks.num_levels; i++)
2277             size += sprintf(buf + size, "%d: %uMhz %s\n",
2278                 i, clocks.data[i].clocks_in_khz / 1000,
2279                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2280         break;
2281
2282     case PP_SOCCLK:
2283         PP_ASSERT_WITH_CODE(
2284                 smum_send_msg_to_smc_with_parameter(hwmgr,
2285                     PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16),
2286                     &now) == 0,
2287                 "Attempt to get Current SOCCLK Frequency Failed!",
2288                 return -EINVAL);
2289
2290         PP_ASSERT_WITH_CODE(
2291                 vega12_get_socclocks(hwmgr, &clocks) == 0,
2292                 "Attempt to get soc clk levels Failed!",
2293                 return -1);
2294         for (i = 0; i < clocks.num_levels; i++)
2295             size += sprintf(buf + size, "%d: %uMhz %s\n",
2296                 i, clocks.data[i].clocks_in_khz / 1000,
2297                 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2298         break;
2299
2300     case PP_DCEFCLK:
2301         PP_ASSERT_WITH_CODE(
2302                 smum_send_msg_to_smc_with_parameter(hwmgr,
2303                     PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16),
2304                     &now) == 0,
2305                 "Attempt to get Current DCEFCLK Frequency Failed!",
2306                 return -EINVAL);
2307
2308         PP_ASSERT_WITH_CODE(
2309                 vega12_get_dcefclocks(hwmgr, &clocks) == 0,
2310                 "Attempt to get dcef clk levels Failed!",
2311                 return -1);
2312         for (i = 0; i < clocks.num_levels; i++)
2313             size += sprintf(buf + size, "%d: %uMhz %s\n",
2314                 i, clocks.data[i].clocks_in_khz / 1000,
2315                 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2316         break;
2317
2318     case PP_PCIE:
2319         break;
2320
2321     default:
2322         break;
2323     }
2324     return size;
2325 }
2326
2327 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2328 {
2329     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2330     struct vega12_single_dpm_table *dpm_table;
2331     bool vblank_too_short = false;
2332     bool disable_mclk_switching;
2333     uint32_t i, latency;
2334
2335     disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2336                       !hwmgr->display_config->multi_monitor_in_sync) ||
2337                       vblank_too_short;
2338     latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2339
2340     /* gfxclk */
2341     dpm_table = &(data->dpm_table.gfx_table);
2342     dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2343     dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2344     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2345     dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2346
2347     if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2348         if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2349             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2350             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2351         }
2352
2353         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2354             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2355             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2356         }
2357
2358         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2359             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2360             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2361         }
2362     }
2363
2364     /* memclk */
2365     dpm_table = &(data->dpm_table.mem_table);
2366     dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2367     dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2368     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2369     dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2370
2371     if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2372         if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2373             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2374             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2375         }
2376
2377         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2378             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2379             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2380         }
2381
2382         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2383             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2384             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2385         }
2386     }
2387
2388     /* honour DAL's UCLK Hardmin */
2389     if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2390         dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2391
2392     /* Hardmin is dependent on displayconfig */
2393     if (disable_mclk_switching) {
2394         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2395         for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
2396             if (data->mclk_latency_table.entries[i].latency <= latency) {
2397                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
2398                     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2399                     break;
2400                 }
2401             }
2402         }
2403     }
2404
2405     if (hwmgr->display_config->nb_pstate_switch_disable)
2406         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2407
2408     /* vclk */
2409     dpm_table = &(data->dpm_table.vclk_table);
2410     dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2411     dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2412     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2413     dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2414
2415     if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2416         if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2417             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2418             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2419         }
2420
2421         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2422             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2423             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2424         }
2425     }
2426
2427     /* dclk */
2428     dpm_table = &(data->dpm_table.dclk_table);
2429     dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2430     dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2431     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2432     dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2433
2434     if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2435         if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2436             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2437             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2438         }
2439
2440         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2441             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2442             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2443         }
2444     }
2445
2446     /* socclk */
2447     dpm_table = &(data->dpm_table.soc_table);
2448     dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2449     dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2450     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2451     dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2452
2453     if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2454         if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2455             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2456             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2457         }
2458
2459         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2460             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2461             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2462         }
2463     }
2464
2465     /* eclk */
2466     dpm_table = &(data->dpm_table.eclk_table);
2467     dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2468     dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2469     dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2470     dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2471
2472     if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2473         if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2474             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2475             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2476         }
2477
2478         if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2479             dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2480             dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2481         }
2482     }
2483
2484     return 0;
2485 }
2486
2487 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2488         struct vega12_single_dpm_table *dpm_table)
2489 {
2490     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2491     int ret = 0;
2492
2493     if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2494         PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2495                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2496                 return -EINVAL);
2497         PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2498                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2499                 return -EINVAL);
2500
2501         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2502         PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2503                 PPSMC_MSG_SetHardMinByFreq,
2504                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
2505                 NULL)),
2506                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2507                 return ret);
2508     }
2509
2510     return ret;
2511 }
2512
2513 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2514 {
2515     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2516     int ret = 0;
2517
2518     smum_send_msg_to_smc_with_parameter(hwmgr,
2519             PPSMC_MSG_NumOfDisplays, 0,
2520             NULL);
2521
2522     ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2523             &data->dpm_table.mem_table);
2524
2525     return ret;
2526 }
2527
2528 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2529 {
2530     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2531     int result = 0;
2532     Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2533
2534     if ((data->water_marks_bitmap & WaterMarksExist) &&
2535             !(data->water_marks_bitmap & WaterMarksLoaded)) {
2536         result = smum_smc_table_manager(hwmgr,
2537                         (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2538         PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
2539         data->water_marks_bitmap |= WaterMarksLoaded;
2540     }
2541
2542     if ((data->water_marks_bitmap & WaterMarksExist) &&
2543         data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2544         data->smu_features[GNLD_DPM_SOCCLK].supported)
2545         smum_send_msg_to_smc_with_parameter(hwmgr,
2546             PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
2547             NULL);
2548
2549     return result;
2550 }
2551
2552 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2553 {
2554     struct vega12_hwmgr *data =
2555             (struct vega12_hwmgr *)(hwmgr->backend);
2556
2557     if (data->smu_features[GNLD_DPM_UVD].supported) {
2558         PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2559                 enable,
2560                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2561                 "Attempt to Enable/Disable DPM UVD Failed!",
2562                 return -1);
2563         data->smu_features[GNLD_DPM_UVD].enabled = enable;
2564     }
2565
2566     return 0;
2567 }
2568
2569 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2570 {
2571     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2572
2573     if (data->vce_power_gated == bgate)
2574         return;
2575
2576     data->vce_power_gated = bgate;
2577     vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2578 }
2579
2580 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2581 {
2582     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2583
2584     if (data->uvd_power_gated == bgate)
2585         return;
2586
2587     data->uvd_power_gated = bgate;
2588     vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2589 }
2590
2591 static bool
2592 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2593 {
2594     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2595     bool is_update_required = false;
2596
2597     if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2598         is_update_required = true;
2599
2600     if (data->registry_data.gfx_clk_deep_sleep_support) {
2601         if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2602             is_update_required = true;
2603     }
2604
2605     return is_update_required;
2606 }
2607
2608 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2609 {
2610     int tmp_result, result = 0;
2611
2612     tmp_result = vega12_disable_all_smu_features(hwmgr);
2613     PP_ASSERT_WITH_CODE((tmp_result == 0),
2614             "Failed to disable all smu features!", result = tmp_result);
2615
2616     return result;
2617 }
2618
2619 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2620 {
2621     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2622     int result;
2623
2624     result = vega12_disable_dpm_tasks(hwmgr);
2625     PP_ASSERT_WITH_CODE((0 == result),
2626             "[disable_dpm_tasks] Failed to disable DPM!",
2627             );
2628     data->water_marks_bitmap &= ~(WaterMarksLoaded);
2629
2630     return result;
2631 }
2632
2633 #if 0
2634 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2635         uint32_t *sclk_idx, uint32_t *mclk_idx,
2636         uint32_t min_sclk, uint32_t min_mclk)
2637 {
2638     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2639     struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2640     uint32_t i;
2641
2642     for (i = 0; i < dpm_table->gfx_table.count; i++) {
2643         if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2644             dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2645             *sclk_idx = i;
2646             break;
2647         }
2648     }
2649
2650     for (i = 0; i < dpm_table->mem_table.count; i++) {
2651         if (dpm_table->mem_table.dpm_levels[i].enabled &&
2652             dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2653             *mclk_idx = i;
2654             break;
2655         }
2656     }
2657 }
2658 #endif
2659
2660 #if 0
2661 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2662         struct amd_pp_profile *request)
2663 {
2664     return 0;
2665 }
2666
2667 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2668 {
2669     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2670     struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2671     struct vega12_single_dpm_table *golden_sclk_table =
2672             &(data->golden_dpm_table.gfx_table);
2673     int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2674     int golden_value = golden_sclk_table->dpm_levels
2675             [golden_sclk_table->count - 1].value;
2676
2677     value -= golden_value;
2678     value = DIV_ROUND_UP(value * 100, golden_value);
2679
2680     return value;
2681 }
2682
2683 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2684 {
2685     return 0;
2686 }
2687
2688 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2689 {
2690     struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2691     struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2692     struct vega12_single_dpm_table *golden_mclk_table =
2693             &(data->golden_dpm_table.mem_table);
2694     int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2695     int golden_value = golden_mclk_table->dpm_levels
2696             [golden_mclk_table->count - 1].value;
2697
2698     value -= golden_value;
2699     value = DIV_ROUND_UP(value * 100, golden_value);
2700
2701     return value;
2702 }
2703
2704 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2705 {
2706     return 0;
2707 }
2708 #endif
2709
2710 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2711                     uint32_t virtual_addr_low,
2712                     uint32_t virtual_addr_hi,
2713                     uint32_t mc_addr_low,
2714                     uint32_t mc_addr_hi,
2715                     uint32_t size)
2716 {
2717     smum_send_msg_to_smc_with_parameter(hwmgr,
2718                     PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2719                     virtual_addr_hi,
2720                     NULL);
2721     smum_send_msg_to_smc_with_parameter(hwmgr,
2722                     PPSMC_MSG_SetSystemVirtualDramAddrLow,
2723                     virtual_addr_low,
2724                     NULL);
2725     smum_send_msg_to_smc_with_parameter(hwmgr,
2726                     PPSMC_MSG_DramLogSetDramAddrHigh,
2727                     mc_addr_hi,
2728                     NULL);
2729
2730     smum_send_msg_to_smc_with_parameter(hwmgr,
2731                     PPSMC_MSG_DramLogSetDramAddrLow,
2732                     mc_addr_low,
2733                     NULL);
2734
2735     smum_send_msg_to_smc_with_parameter(hwmgr,
2736                     PPSMC_MSG_DramLogSetDramSize,
2737                     size,
2738                     NULL);
2739     return 0;
2740 }
2741
2742 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2743         struct PP_TemperatureRange *thermal_data)
2744 {
2745     struct vega12_hwmgr *data =
2746             (struct vega12_hwmgr *)(hwmgr->backend);
2747     PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2748
2749     memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2750
2751     thermal_data->max = pp_table->TedgeLimit *
2752         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2753     thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
2754         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2755     thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
2756         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2757     thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2758         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2759     thermal_data->mem_crit_max = pp_table->ThbmLimit *
2760         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2761     thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
2762         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2763
2764     return 0;
2765 }
2766
2767 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2768 {
2769     struct vega12_hwmgr *data =
2770             (struct vega12_hwmgr *)(hwmgr->backend);
2771     int ret = 0;
2772
2773     if (data->gfxoff_controlled_by_driver)
2774         ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL);
2775
2776     return ret;
2777 }
2778
2779 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2780 {
2781     struct vega12_hwmgr *data =
2782             (struct vega12_hwmgr *)(hwmgr->backend);
2783     int ret = 0;
2784
2785     if (data->gfxoff_controlled_by_driver)
2786         ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL);
2787
2788     return ret;
2789 }
2790
2791 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2792 {
2793     if (enable)
2794         return vega12_enable_gfx_off(hwmgr);
2795     else
2796         return vega12_disable_gfx_off(hwmgr);
2797 }
2798
2799 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2800                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2801                 PHM_PerformanceLevel *level)
2802 {
2803     return 0;
2804 }
2805
2806 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
2807                 enum pp_mp1_state mp1_state)
2808 {
2809     uint16_t msg;
2810     int ret;
2811
2812     switch (mp1_state) {
2813     case PP_MP1_STATE_UNLOAD:
2814         msg = PPSMC_MSG_PrepareMp1ForUnload;
2815         break;
2816     case PP_MP1_STATE_SHUTDOWN:
2817     case PP_MP1_STATE_RESET:
2818     case PP_MP1_STATE_NONE:
2819     default:
2820         return 0;
2821     }
2822
2823     PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
2824                 "[PrepareMp1] Failed!",
2825                 return ret);
2826
2827     return 0;
2828 }
2829
2830 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2831 {
2832     memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2833
2834     gpu_metrics->common_header.structure_size =
2835                 sizeof(struct gpu_metrics_v1_0);
2836     gpu_metrics->common_header.format_revision = 1;
2837     gpu_metrics->common_header.content_revision = 0;
2838
2839     gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2840 }
2841
2842 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr,
2843                       void **table)
2844 {
2845     struct vega12_hwmgr *data =
2846             (struct vega12_hwmgr *)(hwmgr->backend);
2847     struct gpu_metrics_v1_0 *gpu_metrics =
2848             &data->gpu_metrics_table;
2849     SmuMetrics_t metrics;
2850     uint32_t fan_speed_rpm;
2851     int ret;
2852
2853     ret = vega12_get_metrics_table(hwmgr, &metrics, true);
2854     if (ret)
2855         return ret;
2856
2857     vega12_init_gpu_metrics_v1_0(gpu_metrics);
2858
2859     gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2860     gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2861     gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2862     gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2863     gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2864
2865     gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2866     gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2867
2868     gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2869     gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2870     gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2871
2872     gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2873     gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2874     gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2875     gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2876     gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2877
2878     gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2879
2880     vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
2881     gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
2882
2883     gpu_metrics->pcie_link_width =
2884             vega12_get_current_pcie_link_width(hwmgr);
2885     gpu_metrics->pcie_link_speed =
2886             vega12_get_current_pcie_link_speed(hwmgr);
2887
2888     *table = (void *)gpu_metrics;
2889
2890     return sizeof(struct gpu_metrics_v1_0);
2891 }
2892
2893 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2894     .backend_init = vega12_hwmgr_backend_init,
2895     .backend_fini = vega12_hwmgr_backend_fini,
2896     .asic_setup = vega12_setup_asic_task,
2897     .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2898     .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2899     .patch_boot_state = vega12_patch_boot_state,
2900     .get_sclk = vega12_dpm_get_sclk,
2901     .get_mclk = vega12_dpm_get_mclk,
2902     .notify_smc_display_config_after_ps_adjustment =
2903             vega12_notify_smc_display_config_after_ps_adjustment,
2904     .force_dpm_level = vega12_dpm_force_dpm_level,
2905     .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2906     .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2907     .reset_fan_speed_to_default =
2908             vega12_fan_ctrl_reset_fan_speed_to_default,
2909     .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2910     .set_fan_control_mode = vega12_set_fan_control_mode,
2911     .get_fan_control_mode = vega12_get_fan_control_mode,
2912     .read_sensor = vega12_read_sensor,
2913     .get_dal_power_level = vega12_get_dal_power_level,
2914     .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2915     .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2916     .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2917     .display_clock_voltage_request = vega12_display_clock_voltage_request,
2918     .force_clock_level = vega12_force_clock_level,
2919     .print_clock_levels = vega12_print_clock_levels,
2920     .apply_clocks_adjust_rules =
2921         vega12_apply_clocks_adjust_rules,
2922     .pre_display_config_changed =
2923         vega12_pre_display_configuration_changed_task,
2924     .display_config_changed = vega12_display_configuration_changed_task,
2925     .powergate_uvd = vega12_power_gate_uvd,
2926     .powergate_vce = vega12_power_gate_vce,
2927     .check_smc_update_required_for_display_configuration =
2928             vega12_check_smc_update_required_for_display_configuration,
2929     .power_off_asic = vega12_power_off_asic,
2930     .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2931 #if 0
2932     .set_power_profile_state = vega12_set_power_profile_state,
2933     .get_sclk_od = vega12_get_sclk_od,
2934     .set_sclk_od = vega12_set_sclk_od,
2935     .get_mclk_od = vega12_get_mclk_od,
2936     .set_mclk_od = vega12_set_mclk_od,
2937 #endif
2938     .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2939     .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2940     .register_irq_handlers = smu9_register_irq_handlers,
2941     .start_thermal_controller = vega12_start_thermal_controller,
2942     .powergate_gfx = vega12_gfx_off_control,
2943     .get_performance_level = vega12_get_performance_level,
2944     .get_asic_baco_capability = smu9_baco_get_capability,
2945     .get_asic_baco_state = smu9_baco_get_state,
2946     .set_asic_baco_state = vega12_baco_set_state,
2947     .get_ppfeature_status = vega12_get_ppfeature_status,
2948     .set_ppfeature_status = vega12_set_ppfeature_status,
2949     .set_mp1_state = vega12_set_mp1_state,
2950     .get_gpu_metrics = vega12_get_gpu_metrics,
2951 };
2952
2953 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2954 {
2955     hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2956     hwmgr->pptable_func = &vega12_pptable_funcs;
2957
2958     return 0;
2959 }