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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/module.h>
0024 #include <linux/pci.h>
0025 #include <linux/slab.h>
0026 #include <linux/fb.h>
0027 
0028 #include "vega10_processpptables.h"
0029 #include "ppatomfwctrl.h"
0030 #include "atomfirmware.h"
0031 #include "pp_debug.h"
0032 #include "cgs_common.h"
0033 #include "vega10_pptable.h"
0034 
0035 #define NUM_DSPCLK_LEVELS 8
0036 #define VEGA10_ENGINECLOCK_HARDMAX 198000
0037 
0038 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
0039         enum phm_platform_caps cap)
0040 {
0041     if (enable)
0042         phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
0043     else
0044         phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
0045 }
0046 
0047 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
0048 {
0049     int index = GetIndexIntoMasterDataTable(powerplayinfo);
0050 
0051     u16 size;
0052     u8 frev, crev;
0053     const void *table_address = hwmgr->soft_pp_table;
0054 
0055     if (!table_address) {
0056         table_address = (ATOM_Vega10_POWERPLAYTABLE *)
0057                 smu_atom_get_data_table(hwmgr->adev, index,
0058                         &size, &frev, &crev);
0059 
0060         hwmgr->soft_pp_table = table_address;   /*Cache the result in RAM.*/
0061         hwmgr->soft_pp_table_size = size;
0062     }
0063 
0064     return table_address;
0065 }
0066 
0067 static int check_powerplay_tables(
0068         struct pp_hwmgr *hwmgr,
0069         const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
0070 {
0071     const ATOM_Vega10_State_Array *state_arrays;
0072 
0073     state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)powerplay_table) +
0074         le16_to_cpu(powerplay_table->usStateArrayOffset));
0075 
0076     PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
0077             ATOM_Vega10_TABLE_REVISION_VEGA10),
0078         "Unsupported PPTable format!", return -1);
0079     PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
0080         "State table is not set!", return -1);
0081     PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
0082         "Invalid PowerPlay Table!", return -1);
0083     PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
0084         "Invalid PowerPlay Table!", return -1);
0085 
0086     return 0;
0087 }
0088 
0089 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
0090 {
0091     set_hw_cap(
0092             hwmgr,
0093             0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_POWERPLAY),
0094             PHM_PlatformCaps_PowerPlaySupport);
0095 
0096     set_hw_cap(
0097             hwmgr,
0098             0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_SBIOSPOWERSOURCE),
0099             PHM_PlatformCaps_BiosPowerSourceControl);
0100 
0101     set_hw_cap(
0102             hwmgr,
0103             0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_HARDWAREDC),
0104             PHM_PlatformCaps_AutomaticDCTransition);
0105 
0106     set_hw_cap(
0107             hwmgr,
0108             0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
0109             PHM_PlatformCaps_BACO);
0110 
0111     set_hw_cap(
0112             hwmgr,
0113             0 != (powerplay_caps & ATOM_VEGA10_PP_PLATFORM_COMBINE_PCC_WITH_THERMAL_SIGNAL),
0114             PHM_PlatformCaps_CombinePCCWithThermalSignal);
0115 
0116     return 0;
0117 }
0118 
0119 static int init_thermal_controller(
0120         struct pp_hwmgr *hwmgr,
0121         const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
0122 {
0123     const ATOM_Vega10_Thermal_Controller *thermal_controller;
0124     const Vega10_PPTable_Generic_SubTable_Header *header;
0125     const ATOM_Vega10_Fan_Table *fan_table_v1;
0126     const ATOM_Vega10_Fan_Table_V2 *fan_table_v2;
0127     const ATOM_Vega10_Fan_Table_V3 *fan_table_v3;
0128 
0129     thermal_controller = (ATOM_Vega10_Thermal_Controller *)
0130             (((unsigned long)powerplay_table) +
0131             le16_to_cpu(powerplay_table->usThermalControllerOffset));
0132 
0133     PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
0134             "Thermal controller table not set!", return -EINVAL);
0135 
0136     hwmgr->thermal_controller.ucType = thermal_controller->ucType;
0137     hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
0138     hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
0139 
0140     hwmgr->thermal_controller.fanInfo.bNoFan =
0141             (0 != (thermal_controller->ucFanParameters &
0142             ATOM_VEGA10_PP_FANPARAMETERS_NOFAN));
0143 
0144     hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
0145             thermal_controller->ucFanParameters &
0146             ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
0147 
0148     hwmgr->thermal_controller.fanInfo.ulMinRPM =
0149             thermal_controller->ucFanMinRPM * 100UL;
0150     hwmgr->thermal_controller.fanInfo.ulMaxRPM =
0151             thermal_controller->ucFanMaxRPM * 100UL;
0152 
0153     hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
0154             = 100000;
0155 
0156     set_hw_cap(
0157             hwmgr,
0158             ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
0159             PHM_PlatformCaps_ThermalController);
0160 
0161     if (!powerplay_table->usFanTableOffset)
0162         return 0;
0163 
0164     header = (const Vega10_PPTable_Generic_SubTable_Header *)
0165             (((unsigned long)powerplay_table) +
0166             le16_to_cpu(powerplay_table->usFanTableOffset));
0167 
0168     if (header->ucRevId == 10) {
0169         fan_table_v1 = (ATOM_Vega10_Fan_Table *)header;
0170 
0171         PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
0172                 "Invalid Input Fan Table!", return -EINVAL);
0173 
0174         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0175                 PHM_PlatformCaps_MicrocodeFanControl);
0176 
0177         hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
0178                 le16_to_cpu(fan_table_v1->usFanOutputSensitivity);
0179         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
0180                 le16_to_cpu(fan_table_v1->usFanRPMMax);
0181         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
0182                 le16_to_cpu(fan_table_v1->usThrottlingRPM);
0183         hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
0184                 le16_to_cpu(fan_table_v1->usFanAcousticLimit);
0185         hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
0186                 le16_to_cpu(fan_table_v1->usTargetTemperature);
0187         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
0188                 le16_to_cpu(fan_table_v1->usMinimumPWMLimit);
0189         hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
0190                 le16_to_cpu(fan_table_v1->usTargetGfxClk);
0191         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
0192                 le16_to_cpu(fan_table_v1->usFanGainEdge);
0193         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
0194                 le16_to_cpu(fan_table_v1->usFanGainHotspot);
0195         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
0196                 le16_to_cpu(fan_table_v1->usFanGainLiquid);
0197         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
0198                 le16_to_cpu(fan_table_v1->usFanGainVrVddc);
0199         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
0200                 le16_to_cpu(fan_table_v1->usFanGainVrMvdd);
0201         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
0202                 le16_to_cpu(fan_table_v1->usFanGainPlx);
0203         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
0204                 le16_to_cpu(fan_table_v1->usFanGainHbm);
0205 
0206         hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
0207                 fan_table_v1->ucEnableZeroRPM;
0208         hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
0209                 le16_to_cpu(fan_table_v1->usFanStopTemperature);
0210         hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
0211                 le16_to_cpu(fan_table_v1->usFanStartTemperature);
0212     } else if (header->ucRevId == 0xb) {
0213         fan_table_v2 = (ATOM_Vega10_Fan_Table_V2 *)header;
0214 
0215         hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
0216                 fan_table_v2->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
0217         hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
0218         hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
0219         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0220                 PHM_PlatformCaps_MicrocodeFanControl);
0221         hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
0222                 le16_to_cpu(fan_table_v2->usFanOutputSensitivity);
0223         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
0224                 fan_table_v2->ucFanMaxRPM * 100UL;
0225         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
0226                 le16_to_cpu(fan_table_v2->usThrottlingRPM);
0227         hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
0228                 le16_to_cpu(fan_table_v2->usFanAcousticLimitRpm);
0229         hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
0230                 le16_to_cpu(fan_table_v2->usTargetTemperature);
0231         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
0232                 le16_to_cpu(fan_table_v2->usMinimumPWMLimit);
0233         hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
0234                 le16_to_cpu(fan_table_v2->usTargetGfxClk);
0235         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
0236                 le16_to_cpu(fan_table_v2->usFanGainEdge);
0237         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
0238                 le16_to_cpu(fan_table_v2->usFanGainHotspot);
0239         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
0240                 le16_to_cpu(fan_table_v2->usFanGainLiquid);
0241         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
0242                 le16_to_cpu(fan_table_v2->usFanGainVrVddc);
0243         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
0244                 le16_to_cpu(fan_table_v2->usFanGainVrMvdd);
0245         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
0246                 le16_to_cpu(fan_table_v2->usFanGainPlx);
0247         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
0248                 le16_to_cpu(fan_table_v2->usFanGainHbm);
0249 
0250         hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
0251                 fan_table_v2->ucEnableZeroRPM;
0252         hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
0253                 le16_to_cpu(fan_table_v2->usFanStopTemperature);
0254         hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
0255                 le16_to_cpu(fan_table_v2->usFanStartTemperature);
0256     } else if (header->ucRevId > 0xb) {
0257         fan_table_v3 = (ATOM_Vega10_Fan_Table_V3 *)header;
0258 
0259         hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
0260                 fan_table_v3->ucFanParameters & ATOM_VEGA10_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
0261         hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v3->ucFanMinRPM * 100UL;
0262         hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v3->ucFanMaxRPM * 100UL;
0263         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
0264                 PHM_PlatformCaps_MicrocodeFanControl);
0265         hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
0266                 le16_to_cpu(fan_table_v3->usFanOutputSensitivity);
0267         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
0268                 fan_table_v3->ucFanMaxRPM * 100UL;
0269         hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
0270                 le16_to_cpu(fan_table_v3->usThrottlingRPM);
0271         hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
0272                 le16_to_cpu(fan_table_v3->usFanAcousticLimitRpm);
0273         hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
0274                 le16_to_cpu(fan_table_v3->usTargetTemperature);
0275         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
0276                 le16_to_cpu(fan_table_v3->usMinimumPWMLimit);
0277         hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
0278                 le16_to_cpu(fan_table_v3->usTargetGfxClk);
0279         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
0280                 le16_to_cpu(fan_table_v3->usFanGainEdge);
0281         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
0282                 le16_to_cpu(fan_table_v3->usFanGainHotspot);
0283         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
0284                 le16_to_cpu(fan_table_v3->usFanGainLiquid);
0285         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
0286                 le16_to_cpu(fan_table_v3->usFanGainVrVddc);
0287         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
0288                 le16_to_cpu(fan_table_v3->usFanGainVrMvdd);
0289         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
0290                 le16_to_cpu(fan_table_v3->usFanGainPlx);
0291         hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
0292                 le16_to_cpu(fan_table_v3->usFanGainHbm);
0293 
0294         hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
0295                 fan_table_v3->ucEnableZeroRPM;
0296         hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
0297                 le16_to_cpu(fan_table_v3->usFanStopTemperature);
0298         hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
0299                 le16_to_cpu(fan_table_v3->usFanStartTemperature);
0300         hwmgr->thermal_controller.advanceFanControlParameters.usMGpuThrottlingRPMLimit =
0301                 le16_to_cpu(fan_table_v3->usMGpuThrottlingRPM);
0302     }
0303 
0304     return 0;
0305 }
0306 
0307 static int init_over_drive_limits(
0308         struct pp_hwmgr *hwmgr,
0309         const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
0310 {
0311     const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
0312             (const ATOM_Vega10_GFXCLK_Dependency_Table *)
0313             (((unsigned long) powerplay_table) +
0314             le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
0315     bool is_acg_enabled = false;
0316     ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
0317 
0318     if (gfxclk_dep_table->ucRevId == 1) {
0319         patom_record_v2 =
0320             (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)gfxclk_dep_table->entries;
0321         is_acg_enabled =
0322             (bool)patom_record_v2[gfxclk_dep_table->ucNumEntries-1].ucACGEnable;
0323     }
0324 
0325     if (powerplay_table->ulMaxODEngineClock > VEGA10_ENGINECLOCK_HARDMAX &&
0326         !is_acg_enabled)
0327         hwmgr->platform_descriptor.overdriveLimit.engineClock =
0328             VEGA10_ENGINECLOCK_HARDMAX;
0329     else
0330         hwmgr->platform_descriptor.overdriveLimit.engineClock =
0331             le32_to_cpu(powerplay_table->ulMaxODEngineClock);
0332     hwmgr->platform_descriptor.overdriveLimit.memoryClock =
0333             le32_to_cpu(powerplay_table->ulMaxODMemoryClock);
0334 
0335     hwmgr->platform_descriptor.minOverdriveVDDC = 0;
0336     hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
0337     hwmgr->platform_descriptor.overdriveVDDCStep = 0;
0338 
0339     return 0;
0340 }
0341 
0342 static int get_mm_clock_voltage_table(
0343         struct pp_hwmgr *hwmgr,
0344         phm_ppt_v1_mm_clock_voltage_dependency_table **vega10_mm_table,
0345         const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table)
0346 {
0347     uint32_t i;
0348     const ATOM_Vega10_MM_Dependency_Record *mm_dependency_record;
0349     phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table;
0350 
0351     PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
0352             "Invalid PowerPlay Table!", return -1);
0353 
0354     mm_table = kzalloc(struct_size(mm_table, entries, mm_dependency_table->ucNumEntries),
0355                GFP_KERNEL);
0356     if (!mm_table)
0357         return -ENOMEM;
0358 
0359     mm_table->count = mm_dependency_table->ucNumEntries;
0360 
0361     for (i = 0; i < mm_dependency_table->ucNumEntries; i++) {
0362         mm_dependency_record = &mm_dependency_table->entries[i];
0363         mm_table->entries[i].vddcInd = mm_dependency_record->ucVddcInd;
0364         mm_table->entries[i].samclock =
0365                 le32_to_cpu(mm_dependency_record->ulPSPClk);
0366         mm_table->entries[i].eclk = le32_to_cpu(mm_dependency_record->ulEClk);
0367         mm_table->entries[i].vclk = le32_to_cpu(mm_dependency_record->ulVClk);
0368         mm_table->entries[i].dclk = le32_to_cpu(mm_dependency_record->ulDClk);
0369     }
0370 
0371     *vega10_mm_table = mm_table;
0372 
0373     return 0;
0374 }
0375 
0376 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t* sda)
0377 {
0378     switch(line){
0379     case Vega10_I2CLineID_DDC1:
0380         *scl = Vega10_I2C_DDC1CLK;
0381         *sda = Vega10_I2C_DDC1DATA;
0382         break;
0383     case Vega10_I2CLineID_DDC2:
0384         *scl = Vega10_I2C_DDC2CLK;
0385         *sda = Vega10_I2C_DDC2DATA;
0386         break;
0387     case Vega10_I2CLineID_DDC3:
0388         *scl = Vega10_I2C_DDC3CLK;
0389         *sda = Vega10_I2C_DDC3DATA;
0390         break;
0391     case Vega10_I2CLineID_DDC4:
0392         *scl = Vega10_I2C_DDC4CLK;
0393         *sda = Vega10_I2C_DDC4DATA;
0394         break;
0395     case Vega10_I2CLineID_DDC5:
0396         *scl = Vega10_I2C_DDC5CLK;
0397         *sda = Vega10_I2C_DDC5DATA;
0398         break;
0399     case Vega10_I2CLineID_DDC6:
0400         *scl = Vega10_I2C_DDC6CLK;
0401         *sda = Vega10_I2C_DDC6DATA;
0402         break;
0403     case Vega10_I2CLineID_SCLSDA:
0404         *scl = Vega10_I2C_SCL;
0405         *sda = Vega10_I2C_SDA;
0406         break;
0407     case Vega10_I2CLineID_DDCVGA:
0408         *scl = Vega10_I2C_DDCVGACLK;
0409         *sda = Vega10_I2C_DDCVGADATA;
0410         break;
0411     default:
0412         *scl = 0;
0413         *sda = 0;
0414         break;
0415     }
0416 }
0417 
0418 static int get_tdp_table(
0419         struct pp_hwmgr *hwmgr,
0420         struct phm_tdp_table **info_tdp_table,
0421         const Vega10_PPTable_Generic_SubTable_Header *table)
0422 {
0423     uint32_t table_size;
0424     struct phm_tdp_table *tdp_table;
0425     uint8_t scl;
0426     uint8_t sda;
0427     const ATOM_Vega10_PowerTune_Table *power_tune_table;
0428     const ATOM_Vega10_PowerTune_Table_V2 *power_tune_table_v2;
0429     const ATOM_Vega10_PowerTune_Table_V3 *power_tune_table_v3;
0430 
0431     table_size = sizeof(uint32_t) + sizeof(struct phm_tdp_table);
0432 
0433     tdp_table = kzalloc(table_size, GFP_KERNEL);
0434 
0435     if (!tdp_table)
0436         return -ENOMEM;
0437 
0438     if (table->ucRevId == 5) {
0439         power_tune_table = (ATOM_Vega10_PowerTune_Table *)table;
0440         tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table->usSocketPowerLimit);
0441         tdp_table->usTDC = le16_to_cpu(power_tune_table->usTdcLimit);
0442         tdp_table->usEDCLimit = le16_to_cpu(power_tune_table->usEdcLimit);
0443         tdp_table->usSoftwareShutdownTemp =
0444                 le16_to_cpu(power_tune_table->usSoftwareShutdownTemp);
0445         tdp_table->usTemperatureLimitTedge =
0446                 le16_to_cpu(power_tune_table->usTemperatureLimitTedge);
0447         tdp_table->usTemperatureLimitHotspot =
0448                 le16_to_cpu(power_tune_table->usTemperatureLimitHotSpot);
0449         tdp_table->usTemperatureLimitLiquid1 =
0450                 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid1);
0451         tdp_table->usTemperatureLimitLiquid2 =
0452                 le16_to_cpu(power_tune_table->usTemperatureLimitLiquid2);
0453         tdp_table->usTemperatureLimitHBM =
0454                 le16_to_cpu(power_tune_table->usTemperatureLimitHBM);
0455         tdp_table->usTemperatureLimitVrVddc =
0456                 le16_to_cpu(power_tune_table->usTemperatureLimitVrSoc);
0457         tdp_table->usTemperatureLimitVrMvdd =
0458                 le16_to_cpu(power_tune_table->usTemperatureLimitVrMem);
0459         tdp_table->usTemperatureLimitPlx =
0460                 le16_to_cpu(power_tune_table->usTemperatureLimitPlx);
0461         tdp_table->ucLiquid1_I2C_address = power_tune_table->ucLiquid1_I2C_address;
0462         tdp_table->ucLiquid2_I2C_address = power_tune_table->ucLiquid2_I2C_address;
0463         tdp_table->ucLiquid_I2C_Line = power_tune_table->ucLiquid_I2C_LineSCL;
0464         tdp_table->ucLiquid_I2C_LineSDA = power_tune_table->ucLiquid_I2C_LineSDA;
0465         tdp_table->ucVr_I2C_address = power_tune_table->ucVr_I2C_address;
0466         tdp_table->ucVr_I2C_Line = power_tune_table->ucVr_I2C_LineSCL;
0467         tdp_table->ucVr_I2C_LineSDA = power_tune_table->ucVr_I2C_LineSDA;
0468         tdp_table->ucPlx_I2C_address = power_tune_table->ucPlx_I2C_address;
0469         tdp_table->ucPlx_I2C_Line = power_tune_table->ucPlx_I2C_LineSCL;
0470         tdp_table->ucPlx_I2C_LineSDA = power_tune_table->ucPlx_I2C_LineSDA;
0471         hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
0472     } else if (table->ucRevId == 6) {
0473         power_tune_table_v2 = (ATOM_Vega10_PowerTune_Table_V2 *)table;
0474         tdp_table->usMaximumPowerDeliveryLimit = le16_to_cpu(power_tune_table_v2->usSocketPowerLimit);
0475         tdp_table->usTDC = le16_to_cpu(power_tune_table_v2->usTdcLimit);
0476         tdp_table->usEDCLimit = le16_to_cpu(power_tune_table_v2->usEdcLimit);
0477         tdp_table->usSoftwareShutdownTemp =
0478                 le16_to_cpu(power_tune_table_v2->usSoftwareShutdownTemp);
0479         tdp_table->usTemperatureLimitTedge =
0480                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitTedge);
0481         tdp_table->usTemperatureLimitHotspot =
0482                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHotSpot);
0483         tdp_table->usTemperatureLimitLiquid1 =
0484                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid1);
0485         tdp_table->usTemperatureLimitLiquid2 =
0486                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitLiquid2);
0487         tdp_table->usTemperatureLimitHBM =
0488                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitHBM);
0489         tdp_table->usTemperatureLimitVrVddc =
0490                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrSoc);
0491         tdp_table->usTemperatureLimitVrMvdd =
0492                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitVrMem);
0493         tdp_table->usTemperatureLimitPlx =
0494                 le16_to_cpu(power_tune_table_v2->usTemperatureLimitPlx);
0495         tdp_table->ucLiquid1_I2C_address = power_tune_table_v2->ucLiquid1_I2C_address;
0496         tdp_table->ucLiquid2_I2C_address = power_tune_table_v2->ucLiquid2_I2C_address;
0497 
0498         get_scl_sda_value(power_tune_table_v2->ucLiquid_I2C_Line, &scl, &sda);
0499 
0500         tdp_table->ucLiquid_I2C_Line = scl;
0501         tdp_table->ucLiquid_I2C_LineSDA = sda;
0502 
0503         tdp_table->ucVr_I2C_address = power_tune_table_v2->ucVr_I2C_address;
0504 
0505         get_scl_sda_value(power_tune_table_v2->ucVr_I2C_Line, &scl, &sda);
0506 
0507         tdp_table->ucVr_I2C_Line = scl;
0508         tdp_table->ucVr_I2C_LineSDA = sda;
0509         tdp_table->ucPlx_I2C_address = power_tune_table_v2->ucPlx_I2C_address;
0510 
0511         get_scl_sda_value(power_tune_table_v2->ucPlx_I2C_Line, &scl, &sda);
0512 
0513         tdp_table->ucPlx_I2C_Line = scl;
0514         tdp_table->ucPlx_I2C_LineSDA = sda;
0515 
0516         hwmgr->platform_descriptor.LoadLineSlope =
0517                     le16_to_cpu(power_tune_table_v2->usLoadLineResistance);
0518     } else {
0519         power_tune_table_v3 = (ATOM_Vega10_PowerTune_Table_V3 *)table;
0520         tdp_table->usMaximumPowerDeliveryLimit   = le16_to_cpu(power_tune_table_v3->usSocketPowerLimit);
0521         tdp_table->usTDC                         = le16_to_cpu(power_tune_table_v3->usTdcLimit);
0522         tdp_table->usEDCLimit                    = le16_to_cpu(power_tune_table_v3->usEdcLimit);
0523         tdp_table->usSoftwareShutdownTemp        = le16_to_cpu(power_tune_table_v3->usSoftwareShutdownTemp);
0524         tdp_table->usTemperatureLimitTedge       = le16_to_cpu(power_tune_table_v3->usTemperatureLimitTedge);
0525         tdp_table->usTemperatureLimitHotspot     = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHotSpot);
0526         tdp_table->usTemperatureLimitLiquid1     = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid1);
0527         tdp_table->usTemperatureLimitLiquid2     = le16_to_cpu(power_tune_table_v3->usTemperatureLimitLiquid2);
0528         tdp_table->usTemperatureLimitHBM         = le16_to_cpu(power_tune_table_v3->usTemperatureLimitHBM);
0529         tdp_table->usTemperatureLimitVrVddc      = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrSoc);
0530         tdp_table->usTemperatureLimitVrMvdd      = le16_to_cpu(power_tune_table_v3->usTemperatureLimitVrMem);
0531         tdp_table->usTemperatureLimitPlx         = le16_to_cpu(power_tune_table_v3->usTemperatureLimitPlx);
0532         tdp_table->ucLiquid1_I2C_address         = power_tune_table_v3->ucLiquid1_I2C_address;
0533         tdp_table->ucLiquid2_I2C_address         = power_tune_table_v3->ucLiquid2_I2C_address;
0534         tdp_table->usBoostStartTemperature       = le16_to_cpu(power_tune_table_v3->usBoostStartTemperature);
0535         tdp_table->usBoostStopTemperature        = le16_to_cpu(power_tune_table_v3->usBoostStopTemperature);
0536         tdp_table->ulBoostClock                  = le32_to_cpu(power_tune_table_v3->ulBoostClock);
0537 
0538         get_scl_sda_value(power_tune_table_v3->ucLiquid_I2C_Line, &scl, &sda);
0539 
0540         tdp_table->ucLiquid_I2C_Line             = scl;
0541         tdp_table->ucLiquid_I2C_LineSDA          = sda;
0542 
0543         tdp_table->ucVr_I2C_address              = power_tune_table_v3->ucVr_I2C_address;
0544 
0545         get_scl_sda_value(power_tune_table_v3->ucVr_I2C_Line, &scl, &sda);
0546 
0547         tdp_table->ucVr_I2C_Line                 = scl;
0548         tdp_table->ucVr_I2C_LineSDA              = sda;
0549 
0550         tdp_table->ucPlx_I2C_address             = power_tune_table_v3->ucPlx_I2C_address;
0551 
0552         get_scl_sda_value(power_tune_table_v3->ucPlx_I2C_Line, &scl, &sda);
0553 
0554         tdp_table->ucPlx_I2C_Line                = scl;
0555         tdp_table->ucPlx_I2C_LineSDA             = sda;
0556 
0557         hwmgr->platform_descriptor.LoadLineSlope =
0558                     le16_to_cpu(power_tune_table_v3->usLoadLineResistance);
0559     }
0560 
0561     *info_tdp_table = tdp_table;
0562 
0563     return 0;
0564 }
0565 
0566 static int get_socclk_voltage_dependency_table(
0567         struct pp_hwmgr *hwmgr,
0568         phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_clk_dep_table,
0569         const ATOM_Vega10_SOCCLK_Dependency_Table *clk_dep_table)
0570 {
0571     uint32_t i;
0572     phm_ppt_v1_clock_voltage_dependency_table *clk_table;
0573 
0574     PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
0575         "Invalid PowerPlay Table!", return -1);
0576 
0577     clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
0578                 GFP_KERNEL);
0579     if (!clk_table)
0580         return -ENOMEM;
0581 
0582     clk_table->count = (uint32_t)clk_dep_table->ucNumEntries;
0583 
0584     for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
0585         clk_table->entries[i].vddInd =
0586                 clk_dep_table->entries[i].ucVddInd;
0587         clk_table->entries[i].clk =
0588                 le32_to_cpu(clk_dep_table->entries[i].ulClk);
0589     }
0590 
0591     *pp_vega10_clk_dep_table = clk_table;
0592 
0593     return 0;
0594 }
0595 
0596 static int get_mclk_voltage_dependency_table(
0597         struct pp_hwmgr *hwmgr,
0598         phm_ppt_v1_clock_voltage_dependency_table **pp_vega10_mclk_dep_table,
0599         const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table)
0600 {
0601     uint32_t i;
0602     phm_ppt_v1_clock_voltage_dependency_table *mclk_table;
0603 
0604     PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
0605         "Invalid PowerPlay Table!", return -1);
0606 
0607     mclk_table = kzalloc(struct_size(mclk_table, entries, mclk_dep_table->ucNumEntries),
0608                 GFP_KERNEL);
0609     if (!mclk_table)
0610         return -ENOMEM;
0611 
0612     mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries;
0613 
0614     for (i = 0; i < mclk_dep_table->ucNumEntries; i++) {
0615         mclk_table->entries[i].vddInd =
0616                 mclk_dep_table->entries[i].ucVddInd;
0617         mclk_table->entries[i].vddciInd =
0618                 mclk_dep_table->entries[i].ucVddciInd;
0619         mclk_table->entries[i].mvddInd =
0620                 mclk_dep_table->entries[i].ucVddMemInd;
0621         mclk_table->entries[i].clk =
0622                 le32_to_cpu(mclk_dep_table->entries[i].ulMemClk);
0623     }
0624 
0625     *pp_vega10_mclk_dep_table = mclk_table;
0626 
0627     return 0;
0628 }
0629 
0630 static int get_gfxclk_voltage_dependency_table(
0631         struct pp_hwmgr *hwmgr,
0632         struct phm_ppt_v1_clock_voltage_dependency_table
0633             **pp_vega10_clk_dep_table,
0634         const ATOM_Vega10_GFXCLK_Dependency_Table *clk_dep_table)
0635 {
0636     uint32_t i;
0637     struct phm_ppt_v1_clock_voltage_dependency_table
0638                 *clk_table;
0639     ATOM_Vega10_GFXCLK_Dependency_Record_V2 *patom_record_v2;
0640 
0641     PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
0642             "Invalid PowerPlay Table!", return -1);
0643 
0644     clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
0645                 GFP_KERNEL);
0646     if (!clk_table)
0647         return -ENOMEM;
0648 
0649     clk_table->count = clk_dep_table->ucNumEntries;
0650 
0651     if (clk_dep_table->ucRevId == 0) {
0652         for (i = 0; i < clk_table->count; i++) {
0653             clk_table->entries[i].vddInd =
0654                 clk_dep_table->entries[i].ucVddInd;
0655             clk_table->entries[i].clk =
0656                 le32_to_cpu(clk_dep_table->entries[i].ulClk);
0657             clk_table->entries[i].cks_enable =
0658                 (((le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x8000)
0659                         >> 15) == 0) ? 1 : 0;
0660             clk_table->entries[i].cks_voffset =
0661                 le16_to_cpu(clk_dep_table->entries[i].usCKSVOffsetandDisable) & 0x7F;
0662             clk_table->entries[i].sclk_offset =
0663                 le16_to_cpu(clk_dep_table->entries[i].usAVFSOffset);
0664         }
0665     } else if (clk_dep_table->ucRevId == 1) {
0666         patom_record_v2 = (ATOM_Vega10_GFXCLK_Dependency_Record_V2 *)clk_dep_table->entries;
0667         for (i = 0; i < clk_table->count; i++) {
0668             clk_table->entries[i].vddInd =
0669                     patom_record_v2->ucVddInd;
0670             clk_table->entries[i].clk =
0671                     le32_to_cpu(patom_record_v2->ulClk);
0672             clk_table->entries[i].cks_enable =
0673                     (((le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x8000)
0674                             >> 15) == 0) ? 1 : 0;
0675             clk_table->entries[i].cks_voffset =
0676                     le16_to_cpu(patom_record_v2->usCKSVOffsetandDisable) & 0x7F;
0677             clk_table->entries[i].sclk_offset =
0678                     le16_to_cpu(patom_record_v2->usAVFSOffset);
0679             patom_record_v2++;
0680         }
0681     } else {
0682         kfree(clk_table);
0683         PP_ASSERT_WITH_CODE(false,
0684             "Unsupported GFXClockDependencyTable Revision!",
0685             return -EINVAL);
0686     }
0687 
0688     *pp_vega10_clk_dep_table = clk_table;
0689 
0690     return 0;
0691 }
0692 
0693 static int get_pix_clk_voltage_dependency_table(
0694         struct pp_hwmgr *hwmgr,
0695         struct phm_ppt_v1_clock_voltage_dependency_table
0696             **pp_vega10_clk_dep_table,
0697         const  ATOM_Vega10_PIXCLK_Dependency_Table *clk_dep_table)
0698 {
0699     uint32_t i;
0700     struct phm_ppt_v1_clock_voltage_dependency_table
0701                 *clk_table;
0702 
0703     PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
0704             "Invalid PowerPlay Table!", return -1);
0705 
0706     clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries),
0707                 GFP_KERNEL);
0708     if (!clk_table)
0709         return -ENOMEM;
0710 
0711     clk_table->count = clk_dep_table->ucNumEntries;
0712 
0713     for (i = 0; i < clk_table->count; i++) {
0714         clk_table->entries[i].vddInd =
0715                 clk_dep_table->entries[i].ucVddInd;
0716         clk_table->entries[i].clk =
0717                 le32_to_cpu(clk_dep_table->entries[i].ulClk);
0718     }
0719 
0720     *pp_vega10_clk_dep_table = clk_table;
0721 
0722     return 0;
0723 }
0724 
0725 static int get_dcefclk_voltage_dependency_table(
0726         struct pp_hwmgr *hwmgr,
0727         struct phm_ppt_v1_clock_voltage_dependency_table
0728             **pp_vega10_clk_dep_table,
0729         const ATOM_Vega10_DCEFCLK_Dependency_Table *clk_dep_table)
0730 {
0731     uint32_t i;
0732     uint8_t num_entries;
0733     struct phm_ppt_v1_clock_voltage_dependency_table
0734                 *clk_table;
0735     uint32_t dev_id;
0736     uint32_t rev_id;
0737     struct amdgpu_device *adev = hwmgr->adev;
0738 
0739     PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0),
0740             "Invalid PowerPlay Table!", return -1);
0741 
0742 /*
0743  * workaround needed to add another DPM level for pioneer cards
0744  * as VBIOS is locked down.
0745  * This DPM level was added to support 3DPM monitors @ 4K120Hz
0746  *
0747  */
0748     dev_id = adev->pdev->device;
0749     rev_id = adev->pdev->revision;
0750 
0751     if (dev_id == 0x6863 && rev_id == 0 &&
0752         clk_dep_table->entries[clk_dep_table->ucNumEntries - 1].ulClk < 90000)
0753         num_entries = clk_dep_table->ucNumEntries + 1 > NUM_DSPCLK_LEVELS ?
0754                 NUM_DSPCLK_LEVELS : clk_dep_table->ucNumEntries + 1;
0755     else
0756         num_entries = clk_dep_table->ucNumEntries;
0757 
0758 
0759     clk_table = kzalloc(struct_size(clk_table, entries, num_entries),
0760                 GFP_KERNEL);
0761     if (!clk_table)
0762         return -ENOMEM;
0763 
0764     clk_table->count = (uint32_t)num_entries;
0765 
0766     for (i = 0; i < clk_dep_table->ucNumEntries; i++) {
0767         clk_table->entries[i].vddInd =
0768                 clk_dep_table->entries[i].ucVddInd;
0769         clk_table->entries[i].clk =
0770                 le32_to_cpu(clk_dep_table->entries[i].ulClk);
0771     }
0772 
0773     if (i < num_entries) {
0774         clk_table->entries[i].vddInd = clk_dep_table->entries[i-1].ucVddInd;
0775         clk_table->entries[i].clk = 90000;
0776     }
0777 
0778     *pp_vega10_clk_dep_table = clk_table;
0779 
0780     return 0;
0781 }
0782 
0783 static int get_pcie_table(struct pp_hwmgr *hwmgr,
0784         struct phm_ppt_v1_pcie_table **vega10_pcie_table,
0785         const Vega10_PPTable_Generic_SubTable_Header *table)
0786 {
0787     uint32_t i, pcie_count;
0788     struct phm_ppt_v1_pcie_table *pcie_table;
0789     struct phm_ppt_v2_information *table_info =
0790             (struct phm_ppt_v2_information *)(hwmgr->pptable);
0791     const ATOM_Vega10_PCIE_Table *atom_pcie_table =
0792             (ATOM_Vega10_PCIE_Table *)table;
0793 
0794     PP_ASSERT_WITH_CODE(atom_pcie_table->ucNumEntries,
0795             "Invalid PowerPlay Table!",
0796             return 0);
0797 
0798     pcie_table = kzalloc(struct_size(pcie_table, entries, atom_pcie_table->ucNumEntries),
0799                  GFP_KERNEL);
0800     if (!pcie_table)
0801         return -ENOMEM;
0802 
0803     pcie_count = table_info->vdd_dep_on_sclk->count;
0804     if (atom_pcie_table->ucNumEntries <= pcie_count)
0805         pcie_count = atom_pcie_table->ucNumEntries;
0806     else
0807         pr_info("Number of Pcie Entries exceed the number of"
0808                 " GFXCLK Dpm Levels!"
0809                 " Disregarding the excess entries...\n");
0810 
0811     pcie_table->count = pcie_count;
0812 
0813     for (i = 0; i < pcie_count; i++) {
0814         pcie_table->entries[i].gen_speed =
0815                 atom_pcie_table->entries[i].ucPCIEGenSpeed;
0816         pcie_table->entries[i].lane_width =
0817                 atom_pcie_table->entries[i].ucPCIELaneWidth;
0818         pcie_table->entries[i].pcie_sclk =
0819                 atom_pcie_table->entries[i].ulLCLK;
0820     }
0821 
0822     *vega10_pcie_table = pcie_table;
0823 
0824     return 0;
0825 }
0826 
0827 static int get_hard_limits(
0828         struct pp_hwmgr *hwmgr,
0829         struct phm_clock_and_voltage_limits *limits,
0830         const ATOM_Vega10_Hard_Limit_Table *limit_table)
0831 {
0832     PP_ASSERT_WITH_CODE(limit_table->ucNumEntries,
0833             "Invalid PowerPlay Table!", return -1);
0834 
0835     /* currently we always take entries[0] parameters */
0836     limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);
0837     limits->mclk = le32_to_cpu(limit_table->entries[0].ulMCLKLimit);
0838     limits->gfxclk = le32_to_cpu(limit_table->entries[0].ulGFXCLKLimit);
0839     limits->vddc = le16_to_cpu(limit_table->entries[0].usVddcLimit);
0840     limits->vddci = le16_to_cpu(limit_table->entries[0].usVddciLimit);
0841     limits->vddmem = le16_to_cpu(limit_table->entries[0].usVddMemLimit);
0842 
0843     return 0;
0844 }
0845 
0846 static int get_valid_clk(
0847         struct pp_hwmgr *hwmgr,
0848         struct phm_clock_array **clk_table,
0849         const phm_ppt_v1_clock_voltage_dependency_table *clk_volt_pp_table)
0850 {
0851     uint32_t i;
0852     struct phm_clock_array *table;
0853 
0854     PP_ASSERT_WITH_CODE(clk_volt_pp_table->count,
0855             "Invalid PowerPlay Table!", return -1);
0856 
0857     table = kzalloc(struct_size(table, values, clk_volt_pp_table->count),
0858             GFP_KERNEL);
0859     if (!table)
0860         return -ENOMEM;
0861 
0862     table->count = (uint32_t)clk_volt_pp_table->count;
0863 
0864     for (i = 0; i < table->count; i++)
0865         table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk;
0866 
0867     *clk_table = table;
0868 
0869     return 0;
0870 }
0871 
0872 static int init_powerplay_extended_tables(
0873         struct pp_hwmgr *hwmgr,
0874         const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
0875 {
0876     int result = 0;
0877     struct phm_ppt_v2_information *pp_table_info =
0878         (struct phm_ppt_v2_information *)(hwmgr->pptable);
0879 
0880     const ATOM_Vega10_MM_Dependency_Table *mm_dependency_table =
0881             (const ATOM_Vega10_MM_Dependency_Table *)
0882             (((unsigned long) powerplay_table) +
0883             le16_to_cpu(powerplay_table->usMMDependencyTableOffset));
0884     const Vega10_PPTable_Generic_SubTable_Header *power_tune_table =
0885             (const Vega10_PPTable_Generic_SubTable_Header *)
0886             (((unsigned long) powerplay_table) +
0887             le16_to_cpu(powerplay_table->usPowerTuneTableOffset));
0888     const ATOM_Vega10_SOCCLK_Dependency_Table *socclk_dep_table =
0889             (const ATOM_Vega10_SOCCLK_Dependency_Table *)
0890             (((unsigned long) powerplay_table) +
0891             le16_to_cpu(powerplay_table->usSocclkDependencyTableOffset));
0892     const ATOM_Vega10_GFXCLK_Dependency_Table *gfxclk_dep_table =
0893             (const ATOM_Vega10_GFXCLK_Dependency_Table *)
0894             (((unsigned long) powerplay_table) +
0895             le16_to_cpu(powerplay_table->usGfxclkDependencyTableOffset));
0896     const ATOM_Vega10_DCEFCLK_Dependency_Table *dcefclk_dep_table =
0897             (const ATOM_Vega10_DCEFCLK_Dependency_Table *)
0898             (((unsigned long) powerplay_table) +
0899             le16_to_cpu(powerplay_table->usDcefclkDependencyTableOffset));
0900     const ATOM_Vega10_MCLK_Dependency_Table *mclk_dep_table =
0901             (const ATOM_Vega10_MCLK_Dependency_Table *)
0902             (((unsigned long) powerplay_table) +
0903             le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
0904     const ATOM_Vega10_Hard_Limit_Table *hard_limits =
0905             (const ATOM_Vega10_Hard_Limit_Table *)
0906             (((unsigned long) powerplay_table) +
0907             le16_to_cpu(powerplay_table->usHardLimitTableOffset));
0908     const Vega10_PPTable_Generic_SubTable_Header *pcie_table =
0909             (const Vega10_PPTable_Generic_SubTable_Header *)
0910             (((unsigned long) powerplay_table) +
0911             le16_to_cpu(powerplay_table->usPCIETableOffset));
0912     const ATOM_Vega10_PIXCLK_Dependency_Table *pixclk_dep_table =
0913             (const ATOM_Vega10_PIXCLK_Dependency_Table *)
0914             (((unsigned long) powerplay_table) +
0915             le16_to_cpu(powerplay_table->usPixclkDependencyTableOffset));
0916     const ATOM_Vega10_PHYCLK_Dependency_Table *phyclk_dep_table =
0917             (const ATOM_Vega10_PHYCLK_Dependency_Table *)
0918             (((unsigned long) powerplay_table) +
0919             le16_to_cpu(powerplay_table->usPhyClkDependencyTableOffset));
0920     const ATOM_Vega10_DISPCLK_Dependency_Table *dispclk_dep_table =
0921             (const ATOM_Vega10_DISPCLK_Dependency_Table *)
0922             (((unsigned long) powerplay_table) +
0923             le16_to_cpu(powerplay_table->usDispClkDependencyTableOffset));
0924 
0925     pp_table_info->vdd_dep_on_socclk = NULL;
0926     pp_table_info->vdd_dep_on_sclk = NULL;
0927     pp_table_info->vdd_dep_on_mclk = NULL;
0928     pp_table_info->vdd_dep_on_dcefclk = NULL;
0929     pp_table_info->mm_dep_table = NULL;
0930     pp_table_info->tdp_table = NULL;
0931     pp_table_info->vdd_dep_on_pixclk = NULL;
0932     pp_table_info->vdd_dep_on_phyclk = NULL;
0933     pp_table_info->vdd_dep_on_dispclk = NULL;
0934 
0935     if (powerplay_table->usMMDependencyTableOffset)
0936         result = get_mm_clock_voltage_table(hwmgr,
0937                 &pp_table_info->mm_dep_table,
0938                 mm_dependency_table);
0939 
0940     if (!result && powerplay_table->usPowerTuneTableOffset)
0941         result = get_tdp_table(hwmgr,
0942                 &pp_table_info->tdp_table,
0943                 power_tune_table);
0944 
0945     if (!result && powerplay_table->usSocclkDependencyTableOffset)
0946         result = get_socclk_voltage_dependency_table(hwmgr,
0947                 &pp_table_info->vdd_dep_on_socclk,
0948                 socclk_dep_table);
0949 
0950     if (!result && powerplay_table->usGfxclkDependencyTableOffset)
0951         result = get_gfxclk_voltage_dependency_table(hwmgr,
0952                 &pp_table_info->vdd_dep_on_sclk,
0953                 gfxclk_dep_table);
0954 
0955     if (!result && powerplay_table->usPixclkDependencyTableOffset)
0956         result = get_pix_clk_voltage_dependency_table(hwmgr,
0957                 &pp_table_info->vdd_dep_on_pixclk,
0958                 (const ATOM_Vega10_PIXCLK_Dependency_Table*)
0959                 pixclk_dep_table);
0960 
0961     if (!result && powerplay_table->usPhyClkDependencyTableOffset)
0962         result = get_pix_clk_voltage_dependency_table(hwmgr,
0963                 &pp_table_info->vdd_dep_on_phyclk,
0964                 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
0965                 phyclk_dep_table);
0966 
0967     if (!result && powerplay_table->usDispClkDependencyTableOffset)
0968         result = get_pix_clk_voltage_dependency_table(hwmgr,
0969                 &pp_table_info->vdd_dep_on_dispclk,
0970                 (const ATOM_Vega10_PIXCLK_Dependency_Table *)
0971                 dispclk_dep_table);
0972 
0973     if (!result && powerplay_table->usDcefclkDependencyTableOffset)
0974         result = get_dcefclk_voltage_dependency_table(hwmgr,
0975                 &pp_table_info->vdd_dep_on_dcefclk,
0976                 dcefclk_dep_table);
0977 
0978     if (!result && powerplay_table->usMclkDependencyTableOffset)
0979         result = get_mclk_voltage_dependency_table(hwmgr,
0980                 &pp_table_info->vdd_dep_on_mclk,
0981                 mclk_dep_table);
0982 
0983     if (!result && powerplay_table->usPCIETableOffset)
0984         result = get_pcie_table(hwmgr,
0985                 &pp_table_info->pcie_table,
0986                 pcie_table);
0987 
0988     if (!result && powerplay_table->usHardLimitTableOffset)
0989         result = get_hard_limits(hwmgr,
0990                 &pp_table_info->max_clock_voltage_on_dc,
0991                 hard_limits);
0992 
0993     hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
0994             pp_table_info->max_clock_voltage_on_dc.sclk;
0995     hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
0996             pp_table_info->max_clock_voltage_on_dc.mclk;
0997     hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
0998             pp_table_info->max_clock_voltage_on_dc.vddc;
0999     hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
1000             pp_table_info->max_clock_voltage_on_dc.vddci;
1001 
1002     if (!result &&
1003         pp_table_info->vdd_dep_on_socclk &&
1004         pp_table_info->vdd_dep_on_socclk->count)
1005         result = get_valid_clk(hwmgr,
1006                 &pp_table_info->valid_socclk_values,
1007                 pp_table_info->vdd_dep_on_socclk);
1008 
1009     if (!result &&
1010         pp_table_info->vdd_dep_on_sclk &&
1011         pp_table_info->vdd_dep_on_sclk->count)
1012         result = get_valid_clk(hwmgr,
1013                 &pp_table_info->valid_sclk_values,
1014                 pp_table_info->vdd_dep_on_sclk);
1015 
1016     if (!result &&
1017         pp_table_info->vdd_dep_on_dcefclk &&
1018         pp_table_info->vdd_dep_on_dcefclk->count)
1019         result = get_valid_clk(hwmgr,
1020                 &pp_table_info->valid_dcefclk_values,
1021                 pp_table_info->vdd_dep_on_dcefclk);
1022 
1023     if (!result &&
1024         pp_table_info->vdd_dep_on_mclk &&
1025         pp_table_info->vdd_dep_on_mclk->count)
1026         result = get_valid_clk(hwmgr,
1027                 &pp_table_info->valid_mclk_values,
1028                 pp_table_info->vdd_dep_on_mclk);
1029 
1030     return result;
1031 }
1032 
1033 static int get_vddc_lookup_table(
1034         struct pp_hwmgr *hwmgr,
1035         phm_ppt_v1_voltage_lookup_table **lookup_table,
1036         const ATOM_Vega10_Voltage_Lookup_Table *vddc_lookup_pp_tables,
1037         uint32_t max_levels)
1038 {
1039     uint32_t i;
1040     phm_ppt_v1_voltage_lookup_table *table;
1041 
1042     PP_ASSERT_WITH_CODE((vddc_lookup_pp_tables->ucNumEntries != 0),
1043             "Invalid SOC_VDDD Lookup Table!", return 1);
1044 
1045     table = kzalloc(struct_size(table, entries, max_levels), GFP_KERNEL);
1046     if (!table)
1047         return -ENOMEM;
1048 
1049     table->count = vddc_lookup_pp_tables->ucNumEntries;
1050 
1051     for (i = 0; i < vddc_lookup_pp_tables->ucNumEntries; i++)
1052         table->entries[i].us_vdd =
1053                 le16_to_cpu(vddc_lookup_pp_tables->entries[i].usVdd);
1054 
1055     *lookup_table = table;
1056 
1057     return 0;
1058 }
1059 
1060 static int init_dpm_2_parameters(
1061         struct pp_hwmgr *hwmgr,
1062         const ATOM_Vega10_POWERPLAYTABLE *powerplay_table)
1063 {
1064     int result = 0;
1065     struct phm_ppt_v2_information *pp_table_info =
1066             (struct phm_ppt_v2_information *)(hwmgr->pptable);
1067     uint32_t disable_power_control = 0;
1068 
1069     pp_table_info->us_ulv_voltage_offset =
1070         le16_to_cpu(powerplay_table->usUlvVoltageOffset);
1071 
1072     pp_table_info->us_ulv_smnclk_did =
1073             le16_to_cpu(powerplay_table->usUlvSmnclkDid);
1074     pp_table_info->us_ulv_mp1clk_did =
1075             le16_to_cpu(powerplay_table->usUlvMp1clkDid);
1076     pp_table_info->us_ulv_gfxclk_bypass =
1077             le16_to_cpu(powerplay_table->usUlvGfxclkBypass);
1078     pp_table_info->us_gfxclk_slew_rate =
1079             le16_to_cpu(powerplay_table->usGfxclkSlewRate);
1080     pp_table_info->uc_gfx_dpm_voltage_mode  =
1081             le16_to_cpu(powerplay_table->ucGfxVoltageMode);
1082     pp_table_info->uc_soc_dpm_voltage_mode  =
1083             le16_to_cpu(powerplay_table->ucSocVoltageMode);
1084     pp_table_info->uc_uclk_dpm_voltage_mode =
1085             le16_to_cpu(powerplay_table->ucUclkVoltageMode);
1086     pp_table_info->uc_uvd_dpm_voltage_mode  =
1087             le16_to_cpu(powerplay_table->ucUvdVoltageMode);
1088     pp_table_info->uc_vce_dpm_voltage_mode  =
1089             le16_to_cpu(powerplay_table->ucVceVoltageMode);
1090     pp_table_info->uc_mp0_dpm_voltage_mode  =
1091             le16_to_cpu(powerplay_table->ucMp0VoltageMode);
1092     pp_table_info->uc_dcef_dpm_voltage_mode =
1093             le16_to_cpu(powerplay_table->ucDcefVoltageMode);
1094 
1095     pp_table_info->ppm_parameter_table = NULL;
1096     pp_table_info->vddc_lookup_table = NULL;
1097     pp_table_info->vddmem_lookup_table = NULL;
1098     pp_table_info->vddci_lookup_table = NULL;
1099 
1100     /* TDP limits */
1101     hwmgr->platform_descriptor.TDPODLimit =
1102         le16_to_cpu(powerplay_table->usPowerControlLimit);
1103     hwmgr->platform_descriptor.TDPAdjustment = 0;
1104     hwmgr->platform_descriptor.VidAdjustment = 0;
1105     hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
1106     hwmgr->platform_descriptor.VidMinLimit = 0;
1107     hwmgr->platform_descriptor.VidMaxLimit = 1500000;
1108     hwmgr->platform_descriptor.VidStep = 6250;
1109 
1110     disable_power_control = 0;
1111     if (!disable_power_control) {
1112         /* enable TDP overdrive (PowerControl) feature as well if supported */
1113         if (hwmgr->platform_descriptor.TDPODLimit)
1114             phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1115             PHM_PlatformCaps_PowerControl);
1116     }
1117 
1118     if (powerplay_table->usVddcLookupTableOffset) {
1119         const ATOM_Vega10_Voltage_Lookup_Table *vddc_table =
1120                 (ATOM_Vega10_Voltage_Lookup_Table *)
1121                 (((unsigned long)powerplay_table) +
1122                 le16_to_cpu(powerplay_table->usVddcLookupTableOffset));
1123         result = get_vddc_lookup_table(hwmgr,
1124                 &pp_table_info->vddc_lookup_table, vddc_table, 8);
1125     }
1126 
1127     if (powerplay_table->usVddmemLookupTableOffset) {
1128         const ATOM_Vega10_Voltage_Lookup_Table *vdd_mem_table =
1129                 (ATOM_Vega10_Voltage_Lookup_Table *)
1130                 (((unsigned long)powerplay_table) +
1131                 le16_to_cpu(powerplay_table->usVddmemLookupTableOffset));
1132         result = get_vddc_lookup_table(hwmgr,
1133                 &pp_table_info->vddmem_lookup_table, vdd_mem_table, 4);
1134     }
1135 
1136     if (powerplay_table->usVddciLookupTableOffset) {
1137         const ATOM_Vega10_Voltage_Lookup_Table *vddci_table =
1138                 (ATOM_Vega10_Voltage_Lookup_Table *)
1139                 (((unsigned long)powerplay_table) +
1140                 le16_to_cpu(powerplay_table->usVddciLookupTableOffset));
1141         result = get_vddc_lookup_table(hwmgr,
1142                 &pp_table_info->vddci_lookup_table, vddci_table, 4);
1143     }
1144 
1145     return result;
1146 }
1147 
1148 static int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
1149 {
1150     int result = 0;
1151     const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1152 
1153     hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
1154 
1155     PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
1156                 "Failed to allocate hwmgr->pptable!", return -ENOMEM);
1157 
1158     powerplay_table = get_powerplay_table(hwmgr);
1159 
1160     PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1161         "Missing PowerPlay Table!", return -1);
1162 
1163     result = check_powerplay_tables(hwmgr, powerplay_table);
1164 
1165     PP_ASSERT_WITH_CODE((result == 0),
1166                 "check_powerplay_tables failed", return result);
1167 
1168     result = set_platform_caps(hwmgr,
1169                    le32_to_cpu(powerplay_table->ulPlatformCaps));
1170 
1171     PP_ASSERT_WITH_CODE((result == 0),
1172                 "set_platform_caps failed", return result);
1173 
1174     result = init_thermal_controller(hwmgr, powerplay_table);
1175 
1176     PP_ASSERT_WITH_CODE((result == 0),
1177                 "init_thermal_controller failed", return result);
1178 
1179     result = init_over_drive_limits(hwmgr, powerplay_table);
1180 
1181     PP_ASSERT_WITH_CODE((result == 0),
1182                 "init_over_drive_limits failed", return result);
1183 
1184     result = init_powerplay_extended_tables(hwmgr, powerplay_table);
1185 
1186     PP_ASSERT_WITH_CODE((result == 0),
1187                 "init_powerplay_extended_tables failed", return result);
1188 
1189     result = init_dpm_2_parameters(hwmgr, powerplay_table);
1190 
1191     PP_ASSERT_WITH_CODE((result == 0),
1192                 "init_dpm_2_parameters failed", return result);
1193 
1194     return result;
1195 }
1196 
1197 static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
1198 {
1199     struct phm_ppt_v2_information *pp_table_info =
1200             (struct phm_ppt_v2_information *)(hwmgr->pptable);
1201 
1202     kfree(pp_table_info->vdd_dep_on_sclk);
1203     pp_table_info->vdd_dep_on_sclk = NULL;
1204 
1205     kfree(pp_table_info->vdd_dep_on_mclk);
1206     pp_table_info->vdd_dep_on_mclk = NULL;
1207 
1208     kfree(pp_table_info->valid_mclk_values);
1209     pp_table_info->valid_mclk_values = NULL;
1210 
1211     kfree(pp_table_info->valid_sclk_values);
1212     pp_table_info->valid_sclk_values = NULL;
1213 
1214     kfree(pp_table_info->vddc_lookup_table);
1215     pp_table_info->vddc_lookup_table = NULL;
1216 
1217     kfree(pp_table_info->vddmem_lookup_table);
1218     pp_table_info->vddmem_lookup_table = NULL;
1219 
1220     kfree(pp_table_info->vddci_lookup_table);
1221     pp_table_info->vddci_lookup_table = NULL;
1222 
1223     kfree(pp_table_info->ppm_parameter_table);
1224     pp_table_info->ppm_parameter_table = NULL;
1225 
1226     kfree(pp_table_info->mm_dep_table);
1227     pp_table_info->mm_dep_table = NULL;
1228 
1229     kfree(pp_table_info->cac_dtp_table);
1230     pp_table_info->cac_dtp_table = NULL;
1231 
1232     kfree(hwmgr->dyn_state.cac_dtp_table);
1233     hwmgr->dyn_state.cac_dtp_table = NULL;
1234 
1235     kfree(pp_table_info->tdp_table);
1236     pp_table_info->tdp_table = NULL;
1237 
1238     kfree(hwmgr->pptable);
1239     hwmgr->pptable = NULL;
1240 
1241     return 0;
1242 }
1243 
1244 const struct pp_table_func vega10_pptable_funcs = {
1245     .pptable_init = vega10_pp_tables_initialize,
1246     .pptable_fini = vega10_pp_tables_uninitialize,
1247 };
1248 
1249 int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
1250 {
1251     const ATOM_Vega10_State_Array *state_arrays;
1252     const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
1253 
1254     PP_ASSERT_WITH_CODE((pp_table != NULL),
1255             "Missing PowerPlay Table!", return -1);
1256     PP_ASSERT_WITH_CODE((pp_table->sHeader.format_revision >=
1257             ATOM_Vega10_TABLE_REVISION_VEGA10),
1258             "Incorrect PowerPlay table revision!", return -1);
1259 
1260     state_arrays = (ATOM_Vega10_State_Array *)(((unsigned long)pp_table) +
1261             le16_to_cpu(pp_table->usStateArrayOffset));
1262 
1263     return (uint32_t)(state_arrays->ucNumEntries);
1264 }
1265 
1266 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
1267         uint16_t classification, uint16_t classification2)
1268 {
1269     uint32_t result = 0;
1270 
1271     if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT)
1272         result |= PP_StateClassificationFlag_Boot;
1273 
1274     if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1275         result |= PP_StateClassificationFlag_Thermal;
1276 
1277     if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE)
1278         result |= PP_StateClassificationFlag_LimitedPowerSource;
1279 
1280     if (classification & ATOM_PPLIB_CLASSIFICATION_REST)
1281         result |= PP_StateClassificationFlag_Rest;
1282 
1283     if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED)
1284         result |= PP_StateClassificationFlag_Forced;
1285 
1286     if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI)
1287         result |= PP_StateClassificationFlag_ACPI;
1288 
1289     if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2)
1290         result |= PP_StateClassificationFlag_LimitedPowerSource_2;
1291 
1292     return result;
1293 }
1294 
1295 int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
1296         uint32_t entry_index, struct pp_power_state *power_state,
1297         int (*call_back_func)(struct pp_hwmgr *, void *,
1298                 struct pp_power_state *, void *, uint32_t))
1299 {
1300     int result = 0;
1301     const ATOM_Vega10_State_Array *state_arrays;
1302     const ATOM_Vega10_State *state_entry;
1303     const ATOM_Vega10_POWERPLAYTABLE *pp_table =
1304             get_powerplay_table(hwmgr);
1305 
1306     PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
1307             return -1;);
1308     power_state->classification.bios_index = entry_index;
1309 
1310     if (pp_table->sHeader.format_revision >=
1311             ATOM_Vega10_TABLE_REVISION_VEGA10) {
1312         state_arrays = (ATOM_Vega10_State_Array *)
1313                 (((unsigned long)pp_table) +
1314                 le16_to_cpu(pp_table->usStateArrayOffset));
1315 
1316         PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0,
1317                 "Invalid PowerPlay Table State Array Offset.",
1318                 return -1);
1319         PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
1320                 "Invalid PowerPlay Table State Array.",
1321                 return -1);
1322         PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries),
1323                 "Invalid PowerPlay Table State Array Entry.",
1324                 return -1);
1325 
1326         state_entry = &(state_arrays->states[entry_index]);
1327 
1328         result = call_back_func(hwmgr, (void *)state_entry, power_state,
1329                 (void *)pp_table,
1330                 make_classification_flags(hwmgr,
1331                     le16_to_cpu(state_entry->usClassification),
1332                     le16_to_cpu(state_entry->usClassification2)));
1333     }
1334 
1335     if (!result && (power_state->classification.flags &
1336             PP_StateClassificationFlag_Boot))
1337         result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
1338 
1339     return result;
1340 }
1341 
1342 int vega10_baco_set_cap(struct pp_hwmgr *hwmgr)
1343 {
1344     int result = 0;
1345 
1346     const ATOM_Vega10_POWERPLAYTABLE *powerplay_table;
1347 
1348     powerplay_table = get_powerplay_table(hwmgr);
1349 
1350     PP_ASSERT_WITH_CODE((powerplay_table != NULL),
1351         "Missing PowerPlay Table!", return -1);
1352 
1353     result = check_powerplay_tables(hwmgr, powerplay_table);
1354 
1355     PP_ASSERT_WITH_CODE((result == 0),
1356                 "check_powerplay_tables failed", return result);
1357 
1358     set_hw_cap(
1359             hwmgr,
1360             0 != (le32_to_cpu(powerplay_table->ulPlatformCaps) & ATOM_VEGA10_PP_PLATFORM_CAP_BACO),
1361             PHM_PlatformCaps_BACO);
1362     return result;
1363 }
1364
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