powerplay/hwmgr/vega10_powertune.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef _VEGA10_POWERTUNE_H_
0024 #define _VEGA10_POWERTUNE_H_
0025
0026 enum vega10_pt_config_reg_type {
0027     VEGA10_CONFIGREG_MMR = 0,
0028     VEGA10_CONFIGREG_SMC_IND,
0029     VEGA10_CONFIGREG_DIDT_IND,
0030     VEGA10_CONFIGREG_CACHE,
0031     VEGA10_CONFIGREG_MAX
0032 };
0033
0034 enum vega10_didt_config_reg_type {
0035     VEGA10_CONFIGREG_DIDT = 0,
0036     VEGA10_CONFIGREG_GCCAC,
0037     VEGA10_CONFIGREG_SECAC
0038 };
0039
0040 /* PowerContainment Features */
0041 #define POWERCONTAINMENT_FEATURE_DTE             0x00000001
0042 #define POWERCONTAINMENT_FEATURE_TDCLimit        0x00000002
0043 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit     0x00000004
0044
0045 struct vega10_pt_config_reg {
0046     uint32_t                           offset;
0047     uint32_t                           mask;
0048     uint32_t                           shift;
0049     uint32_t                           value;
0050     enum vega10_pt_config_reg_type       type;
0051 };
0052
0053 struct vega10_didt_config_reg {
0054     uint32_t        offset;
0055     uint32_t        mask;
0056     uint32_t        shift;
0057     uint32_t        value;
0058 };
0059
0060 struct vega10_pt_defaults {
0061     uint8_t   SviLoadLineEn;
0062     uint8_t   SviLoadLineVddC;
0063     uint8_t   TDC_VDDC_ThrottleReleaseLimitPerc;
0064     uint8_t   TDC_MAWt;
0065     uint8_t   TdcWaterfallCtl;
0066     uint8_t   DTEAmbientTempBase;
0067 };
0068
0069 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
0070 int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
0071 int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
0072 int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr);
0073 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr);
0074 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
0075 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
0076 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr);
0077
0078 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr);
0079 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr);
0080
0081 #endif  /* _VEGA10_POWERTUNE_H_ */
0082