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0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "hwmgr.h"
0025 #include "vega10_hwmgr.h"
0026 #include "vega10_smumgr.h"
0027 #include "vega10_powertune.h"
0028 #include "vega10_ppsmc.h"
0029 #include "vega10_inc.h"
0030 #include "pp_debug.h"
0031 #include "soc15_common.h"
0032 
0033 static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] =
0034 {
0035 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0036  *      Offset                             Mask                                                 Shift                                                  Value
0037  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0038  */
0039     /* DIDT_SQ */
0040     {   ixDIDT_SQ_TUNING_CTRL,             DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x3853 },
0041     {   ixDIDT_SQ_TUNING_CTRL,             DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x3153 },
0042 
0043     /* DIDT_TD */
0044     {   ixDIDT_TD_TUNING_CTRL,             DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x0dde },
0045     {   ixDIDT_TD_TUNING_CTRL,             DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x0dde },
0046 
0047     /* DIDT_TCP */
0048     {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,       DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,       0x3dde },
0049     {   ixDIDT_TCP_TUNING_CTRL,            DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,       DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,       0x3dde },
0050 
0051     /* DIDT_DB */
0052     {   ixDIDT_DB_TUNING_CTRL,             DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK,        DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT,        0x3dde },
0053     {   ixDIDT_DB_TUNING_CTRL,             DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK,        DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT,        0x3dde },
0054 
0055     {   0xFFFFFFFF  }  /* End of list */
0056 };
0057 
0058 static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] =
0059 {
0060 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0061  *      Offset               Mask                                                     Shift                                                            Value
0062  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0063  */
0064     /*DIDT_SQ_CTRL3 */
0065     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
0066     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
0067     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK,       DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
0068     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
0069     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
0070     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
0071     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
0072     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
0073     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
0074     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
0075     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
0076     {   ixDIDT_SQ_CTRL3,     DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
0077 
0078     /*DIDT_TCP_CTRL3 */
0079     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK,      DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT,            0x0000 },
0080     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,      DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,            0x0000 },
0081     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK,      DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT,            0x0003 },
0082     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,      DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,            0x0000 },
0083     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,      DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,            0x0000 },
0084     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,            0x0003 },
0085     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,      DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,            0x0000 },
0086     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,      DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,            0x0000 },
0087     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK,      DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT,            0x0000 },
0088     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT,            0x0000 },
0089     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK,      DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT,            0x0000 },
0090     {   ixDIDT_TCP_CTRL3,    DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK,      DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,            0x0000 },
0091 
0092     /*DIDT_TD_CTRL3 */
0093     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
0094     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
0095     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__THROTTLE_POLICY_MASK,       DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
0096     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
0097     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
0098     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
0099     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
0100     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
0101     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
0102     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
0103     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
0104     {   ixDIDT_TD_CTRL3,     DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
0105 
0106     /*DIDT_DB_CTRL3 */
0107     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK,       DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT,             0x0000 },
0108     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK,       DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT,             0x0000 },
0109     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__THROTTLE_POLICY_MASK,       DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT,             0x0003 },
0110     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,       DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,             0x0000 },
0111     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK,       DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT,             0x0000 },
0112     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK,       DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT,             0x0003 },
0113     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK,       DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
0114     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK,       DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT,             0x0000 },
0115     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK,       DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT,             0x0000 },
0116     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK,       DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT,             0x0000 },
0117     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK,       DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT,             0x0000 },
0118     {   ixDIDT_DB_CTRL3,     DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK,       DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT,             0x0000 },
0119 
0120     {   0xFFFFFFFF  }  /* End of list */
0121 };
0122 
0123 static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] =
0124 {
0125 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0126  *      Offset                            Mask                                                 Shift                                                  Value
0127  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0128  */
0129     /* DIDT_SQ */
0130     {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3853 },
0131     {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
0132     {   ixDIDT_SQ_CTRL2,                  DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0000 },
0133 
0134     /* DIDT_TD */
0135     {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3fff },
0136     {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
0137     {   ixDIDT_TD_CTRL2,                  DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0001 },
0138 
0139     /* DIDT_TCP */
0140     {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK,                DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT,                0x3dde },
0141     {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,       DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,       0x00c0 },
0142     {   ixDIDT_TCP_CTRL2,                 DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,       DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,       0x0001 },
0143 
0144     /* DIDT_DB */
0145     {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK,                 DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT,                 0x3dde },
0146     {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK,        DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT,        0x00c0 },
0147     {   ixDIDT_DB_CTRL2,                  DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK,        DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT,        0x0001 },
0148 
0149     {   0xFFFFFFFF  }  /* End of list */
0150 };
0151 
0152 static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] =
0153 {
0154 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0155  *      Offset                             Mask                                                 Shift                                                  Value
0156  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0157  */
0158     /* DIDT_SQ */
0159     {   ixDIDT_SQ_CTRL1,                   DIDT_SQ_CTRL1__MIN_POWER_MASK,                       DIDT_SQ_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
0160     {   ixDIDT_SQ_CTRL1,                   DIDT_SQ_CTRL1__MAX_POWER_MASK,                       DIDT_SQ_CTRL1__MAX_POWER__SHIFT,                       0xffff },
0161     /* DIDT_TD */
0162     {   ixDIDT_TD_CTRL1,                   DIDT_TD_CTRL1__MIN_POWER_MASK,                       DIDT_TD_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
0163     {   ixDIDT_TD_CTRL1,                   DIDT_TD_CTRL1__MAX_POWER_MASK,                       DIDT_TD_CTRL1__MAX_POWER__SHIFT,                       0xffff },
0164     /* DIDT_TCP */
0165     {   ixDIDT_TCP_CTRL1,                  DIDT_TCP_CTRL1__MIN_POWER_MASK,                      DIDT_TCP_CTRL1__MIN_POWER__SHIFT,                      0x0000 },
0166     {   ixDIDT_TCP_CTRL1,                  DIDT_TCP_CTRL1__MAX_POWER_MASK,                      DIDT_TCP_CTRL1__MAX_POWER__SHIFT,                      0xffff },
0167     /* DIDT_DB */
0168     {   ixDIDT_DB_CTRL1,                   DIDT_DB_CTRL1__MIN_POWER_MASK,                       DIDT_DB_CTRL1__MIN_POWER__SHIFT,                       0x0000 },
0169     {   ixDIDT_DB_CTRL1,                   DIDT_DB_CTRL1__MAX_POWER_MASK,                       DIDT_DB_CTRL1__MAX_POWER__SHIFT,                       0xffff },
0170 
0171     {   0xFFFFFFFF  }  /* End of list */
0172 };
0173 
0174 
0175 static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] =
0176 {
0177 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0178  *      Offset                             Mask                                                  Shift                                                 Value
0179  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0180  */
0181     /* DIDT_SQ */
0182     {   ixDIDT_SQ_WEIGHT0_3,               0xFFFFFFFF,                                           0,                                                    0x2B363B1A },
0183     {   ixDIDT_SQ_WEIGHT4_7,               0xFFFFFFFF,                                           0,                                                    0x270B2432 },
0184     {   ixDIDT_SQ_WEIGHT8_11,              0xFFFFFFFF,                                           0,                                                    0x00000018 },
0185 
0186     /* DIDT_TD */
0187     {   ixDIDT_TD_WEIGHT0_3,               0xFFFFFFFF,                                           0,                                                    0x2B1D220F },
0188     {   ixDIDT_TD_WEIGHT4_7,               0xFFFFFFFF,                                           0,                                                    0x00007558 },
0189     {   ixDIDT_TD_WEIGHT8_11,              0xFFFFFFFF,                                           0,                                                    0x00000000 },
0190 
0191     /* DIDT_TCP */
0192     {   ixDIDT_TCP_WEIGHT0_3,               0xFFFFFFFF,                                          0,                                                    0x5ACE160D },
0193     {   ixDIDT_TCP_WEIGHT4_7,               0xFFFFFFFF,                                          0,                                                    0x00000000 },
0194     {   ixDIDT_TCP_WEIGHT8_11,              0xFFFFFFFF,                                          0,                                                    0x00000000 },
0195 
0196     /* DIDT_DB */
0197     {   ixDIDT_DB_WEIGHT0_3,                0xFFFFFFFF,                                          0,                                                    0x0E152A0F },
0198     {   ixDIDT_DB_WEIGHT4_7,                0xFFFFFFFF,                                          0,                                                    0x09061813 },
0199     {   ixDIDT_DB_WEIGHT8_11,               0xFFFFFFFF,                                          0,                                                    0x00000013 },
0200 
0201     {   0xFFFFFFFF  }  /* End of list */
0202 };
0203 
0204 static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] =
0205 {
0206 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0207  *      Offset                             Mask                                                 Shift                                                  Value
0208  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0209  */
0210     /* DIDT_SQ */
0211     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
0212     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__PHASE_OFFSET_MASK,   DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
0213     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
0214     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
0215     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
0216     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
0217     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
0218     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
0219     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
0220     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
0221     {  ixDIDT_SQ_CTRL0,                   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
0222     /* DIDT_TD */
0223     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
0224     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__PHASE_OFFSET_MASK,   DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
0225     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
0226     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
0227     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
0228     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
0229     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
0230     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
0231     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
0232     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
0233     {  ixDIDT_TD_CTRL0,                   DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
0234     /* DIDT_TCP */
0235     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
0236     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__PHASE_OFFSET_MASK,  DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
0237     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK,  DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
0238     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,  DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
0239     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
0240     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK,  DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
0241     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
0242     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,  DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
0243     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK,  DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
0244     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
0245     {  ixDIDT_TCP_CTRL0,                  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,  DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
0246     /* DIDT_DB */
0247     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
0248     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__PHASE_OFFSET_MASK,   DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
0249     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK,   DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT,  0x0000 },
0250     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
0251     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT,  0x0001 },
0252     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK,   DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT,  0x0001 },
0253     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT,  0x0001 },
0254     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK,   DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT,  0xffff },
0255     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK,   DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT,  0x0000 },
0256     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK,   DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT,  0x0000 },
0257     {  ixDIDT_DB_CTRL0,                   DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK,   DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT,  0x0000 },
0258 
0259     {   0xFFFFFFFF  }  /* End of list */
0260 };
0261 
0262 
0263 static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] =
0264 {
0265 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0266  *      Offset                   Mask                                                     Shift                                                      Value
0267  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0268  */
0269     /* DIDT_SQ */
0270     {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0004 },
0271     {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0004 },
0272     {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
0273     {   ixDIDT_SQ_STALL_CTRL,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
0274 
0275     /* DIDT_TD */
0276     {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0001 },
0277     {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0001 },
0278     {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
0279     {   ixDIDT_TD_STALL_CTRL,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
0280 
0281     /* DIDT_TCP */
0282     {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,    0x0001 },
0283     {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,   DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,    0x0001 },
0284     {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,    0x000a },
0285     {   ixDIDT_TCP_STALL_CTRL,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,   DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,    0x000a },
0286 
0287     /* DIDT_DB */
0288     {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT,     0x0004 },
0289     {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK,    DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT,     0x0004 },
0290     {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT,     0x000a },
0291     {   ixDIDT_DB_STALL_CTRL,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK,    DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT,     0x000a },
0292 
0293     {   0xFFFFFFFF  }  /* End of list */
0294 };
0295 
0296 static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] =
0297 {
0298 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0299  *      Offset                        Mask                                                      Shift                                                    Value
0300  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0301  */
0302     /* DIDT_SQ_STALL_PATTERN_1_2 */
0303     {   ixDIDT_SQ_STALL_PATTERN_1_2,  DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
0304     {   ixDIDT_SQ_STALL_PATTERN_1_2,  DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
0305 
0306     /* DIDT_SQ_STALL_PATTERN_3_4 */
0307     {   ixDIDT_SQ_STALL_PATTERN_3_4,  DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
0308     {   ixDIDT_SQ_STALL_PATTERN_3_4,  DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
0309 
0310     /* DIDT_SQ_STALL_PATTERN_5_6 */
0311     {   ixDIDT_SQ_STALL_PATTERN_5_6,  DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
0312     {   ixDIDT_SQ_STALL_PATTERN_5_6,  DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
0313 
0314     /* DIDT_SQ_STALL_PATTERN_7 */
0315     {   ixDIDT_SQ_STALL_PATTERN_7,    DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
0316 
0317     /* DIDT_TCP_STALL_PATTERN_1_2 */
0318     {   ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,   DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
0319     {   ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,   DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
0320 
0321     /* DIDT_TCP_STALL_PATTERN_3_4 */
0322     {   ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,   DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
0323     {   ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,   DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
0324 
0325     /* DIDT_TCP_STALL_PATTERN_5_6 */
0326     {   ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,   DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
0327     {   ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,   DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
0328 
0329     /* DIDT_TCP_STALL_PATTERN_7 */
0330     {   ixDIDT_TCP_STALL_PATTERN_7,   DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,     DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,   0x0000 },
0331 
0332     /* DIDT_TD_STALL_PATTERN_1_2 */
0333     {   ixDIDT_TD_STALL_PATTERN_1_2,  DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
0334     {   ixDIDT_TD_STALL_PATTERN_1_2,  DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
0335 
0336     /* DIDT_TD_STALL_PATTERN_3_4 */
0337     {   ixDIDT_TD_STALL_PATTERN_3_4,  DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
0338     {   ixDIDT_TD_STALL_PATTERN_3_4,  DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
0339 
0340     /* DIDT_TD_STALL_PATTERN_5_6 */
0341     {   ixDIDT_TD_STALL_PATTERN_5_6,  DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
0342     {   ixDIDT_TD_STALL_PATTERN_5_6,  DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
0343 
0344     /* DIDT_TD_STALL_PATTERN_7 */
0345     {   ixDIDT_TD_STALL_PATTERN_7,    DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
0346 
0347     /* DIDT_DB_STALL_PATTERN_1_2 */
0348     {   ixDIDT_DB_STALL_PATTERN_1_2,  DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK,    DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT,  0x0001 },
0349     {   ixDIDT_DB_STALL_PATTERN_1_2,  DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK,    DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT,  0x0001 },
0350 
0351     /* DIDT_DB_STALL_PATTERN_3_4 */
0352     {   ixDIDT_DB_STALL_PATTERN_3_4,  DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK,    DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT,  0x0001 },
0353     {   ixDIDT_DB_STALL_PATTERN_3_4,  DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK,    DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT,  0x0001 },
0354 
0355     /* DIDT_DB_STALL_PATTERN_5_6 */
0356     {   ixDIDT_DB_STALL_PATTERN_5_6,  DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK,    DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT,  0x0000 },
0357     {   ixDIDT_DB_STALL_PATTERN_5_6,  DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK,    DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT,  0x0000 },
0358 
0359     /* DIDT_DB_STALL_PATTERN_7 */
0360     {   ixDIDT_DB_STALL_PATTERN_7,    DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK,      DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT,    0x0000 },
0361 
0362     {   0xFFFFFFFF  }  /* End of list */
0363 };
0364 
0365 static const struct vega10_didt_config_reg SELCacConfig_Vega10[] =
0366 {
0367 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0368  *      Offset                             Mask                                                 Shift                                                  Value
0369  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0370  */
0371     /* SQ */
0372     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00060021 },
0373     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00860021 },
0374     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01060021 },
0375     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01860021 },
0376     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x02060021 },
0377     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x02860021 },
0378     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x03060021 },
0379     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x03860021 },
0380     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x04060021 },
0381     /* TD */
0382     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x000E0020 },
0383     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x008E0020 },
0384     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x010E0020 },
0385     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x018E0020 },
0386     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x020E0020 },
0387     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x028E0020 },
0388     /* TCP */
0389     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x001c0020 },
0390     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x009c0020 },
0391     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x011c0020 },
0392     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x019c0020 },
0393     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x021c0020 },
0394     /* DB */
0395     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00200008 },
0396     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x00820008 },
0397     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01020008 },
0398     {   ixSE_CAC_CNTL,                     0xFFFFFFFF,                                          0,                                                     0x01820008 },
0399 
0400     {   0xFFFFFFFF  }  /* End of list */
0401 };
0402 
0403 
0404 static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] =
0405 {
0406 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0407  *      Offset                             Mask                                                 Shift                                                  Value
0408  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0409  */
0410     /* SQ */
0411     {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00030001 },
0412     {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x000F0007 },
0413     {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x003F001F },
0414     {   ixDIDT_SQ_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x0000007F },
0415     /* TD */
0416     {   ixDIDT_TD_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0417     {   ixDIDT_TD_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0418     {   ixDIDT_TD_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0419     {   ixDIDT_TD_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
0420     /* TCP */
0421     {   ixDIDT_TCP_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
0422     {   ixDIDT_TCP_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
0423     {   ixDIDT_TCP_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                         0,                                                     0x00000000 },
0424     {   ixDIDT_TCP_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                         0,                                                     0x00000000 },
0425     /* DB */
0426     {   ixDIDT_DB_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0427     {   ixDIDT_DB_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0428     {   ixDIDT_DB_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0429     {   ixDIDT_DB_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
0430 
0431     {   0xFFFFFFFF  }  /* End of list */
0432 };
0433 
0434 static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] =
0435 {
0436 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0437  *      Offset                             Mask                                                 Shift                                                  Value
0438  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0439  */
0440     /* SQ */
0441     {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000015 },
0442     {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0443     {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0444     {   ixDIDT_SQ_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
0445     /* TD */
0446     {   ixDIDT_TD_EDC_STALL_PATTERN_1_2,   0xFFFFFFFF,                                          0,                                                     0x00000015 },
0447     {   ixDIDT_TD_EDC_STALL_PATTERN_3_4,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0448     {   ixDIDT_TD_EDC_STALL_PATTERN_5_6,   0xFFFFFFFF,                                          0,                                                     0x00000000 },
0449     {   ixDIDT_TD_EDC_STALL_PATTERN_7,     0xFFFFFFFF,                                          0,                                                     0x00000000 },
0450 
0451     {   0xFFFFFFFF  }  /* End of list */
0452 };
0453 
0454 static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] =
0455 {
0456 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0457  *      Offset                             Mask                                                 Shift                                                  Value
0458  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0459  */
0460     /* SQ */
0461     {   ixDIDT_SQ_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0462     {   ixDIDT_SQ_EDC_STALL_DELAY_2,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0463     {   ixDIDT_SQ_EDC_STALL_DELAY_3,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0464     {   ixDIDT_SQ_EDC_STALL_DELAY_4,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0465     /* TD */
0466     {   ixDIDT_TD_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0467     {   ixDIDT_TD_EDC_STALL_DELAY_2,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0468     {   ixDIDT_TD_EDC_STALL_DELAY_3,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0469     {   ixDIDT_TD_EDC_STALL_DELAY_4,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0470     /* TCP */
0471     {   ixDIDT_TCP_EDC_STALL_DELAY_1,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
0472     {   ixDIDT_TCP_EDC_STALL_DELAY_2,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
0473     {   ixDIDT_TCP_EDC_STALL_DELAY_3,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
0474     {   ixDIDT_TCP_EDC_STALL_DELAY_4,      0xFFFFFFFF,                                          0,                                                     0x00000000 },
0475     /* DB */
0476     {   ixDIDT_DB_EDC_STALL_DELAY_1,       0xFFFFFFFF,                                          0,                                                     0x00000000 },
0477 
0478     {   0xFFFFFFFF  }  /* End of list */
0479 };
0480 
0481 static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] =
0482 {
0483 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0484  *      Offset                             Mask                                                 Shift                                                  Value
0485  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0486  */
0487     {   ixDIDT_SQ_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0x0000010E },
0488     {   ixDIDT_TD_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
0489     {   ixDIDT_TCP_EDC_THRESHOLD,          0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
0490     {   ixDIDT_DB_EDC_THRESHOLD,           0xFFFFFFFF,                                          0,                                                     0xFFFFFFFF },
0491 
0492     {   0xFFFFFFFF  }  /* End of list */
0493 };
0494 
0495 static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] =
0496 {
0497 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0498  *      Offset                             Mask                                                 Shift                                                  Value
0499  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0500  */
0501     /* SQ */
0502     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
0503     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0001 },
0504     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
0505     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
0506     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
0507     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0000 },
0508     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
0509     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
0510     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
0511     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0512     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0513 
0514     {   0xFFFFFFFF  }  /* End of list */
0515 };
0516 
0517 static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] =
0518 {
0519 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0520  *      Offset                             Mask                                                 Shift                                                  Value
0521  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0522  */
0523     /* SQ */
0524     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0001 },
0525     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
0526     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
0527     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
0528     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0004 },
0529     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0006 },
0530     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
0531     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
0532     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
0533     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
0534     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0535 
0536     {   0xFFFFFFFF  }  /* End of list */
0537 };
0538 
0539 static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] =
0540 {
0541 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0542  *      Offset                             Mask                                                 Shift                                                  Value
0543  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0544  */
0545     /* SQ */
0546     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
0547     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
0548     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
0549     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0001 },
0550     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0001 },
0551     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000C },
0552     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
0553     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
0554     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
0555     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0556     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
0557 
0558     /* TD */
0559     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_EN_MASK,                       DIDT_TD_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
0560     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
0561     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
0562     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0001 },
0563     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0001 },
0564     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000E },
0565     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
0566     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
0567     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
0568     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0569     {   ixDIDT_TD_EDC_CTRL,                DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
0570 
0571     {   0xFFFFFFFF  }  /* End of list */
0572 };
0573 
0574 static const struct vega10_didt_config_reg    GCDiDtDroopCtrlConfig_vega10[] =
0575 {
0576 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0577  *      Offset                             Mask                                                 Shift                                                  Value
0578  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0579  */
0580     {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT,  0x0000 },
0581     {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT,  0x0000 },
0582     {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT,  0x0000 },
0583     {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK,   GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT,  0x0000 },
0584     {   mmGC_DIDT_DROOP_CTRL,             GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK,   GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT,  0x0000 },
0585 
0586     {   0xFFFFFFFF  }  /* End of list */
0587 };
0588 
0589 static const struct vega10_didt_config_reg    GCDiDtCtrl0Config_vega10[] =
0590 {
0591 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0592  *      Offset                             Mask                                                 Shift                                                  Value
0593  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0594  */
0595     {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK,   GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT,  0x0000 },
0596     {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__PHASE_OFFSET_MASK,   GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT,  0x0000 },
0597     {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_SW_RST_MASK,   GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT,  0x0000 },
0598     {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK,   GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT,  0x0000 },
0599     {   mmGC_DIDT_CTRL0,                  GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK,   GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT,  0x0000 },
0600     {   0xFFFFFFFF  }  /* End of list */
0601 };
0602 
0603 
0604 static const struct vega10_didt_config_reg   PSMSEEDCStallPatternConfig_Vega10[] =
0605 {
0606 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0607  *      Offset                             Mask                                                 Shift                                                  Value
0608  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0609  */
0610     /* SQ EDC STALL PATTERNs */
0611     {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,  DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK,   DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT,   0x0101 },
0612     {   ixDIDT_SQ_EDC_STALL_PATTERN_1_2,  DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK,   DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT,   0x0101 },
0613     {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,  DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK,   DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT,   0x1111 },
0614     {   ixDIDT_SQ_EDC_STALL_PATTERN_3_4,  DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK,   DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT,   0x1111 },
0615 
0616     {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,  DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK,   DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT,   0x1515 },
0617     {   ixDIDT_SQ_EDC_STALL_PATTERN_5_6,  DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK,   DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT,   0x1515 },
0618 
0619     {   ixDIDT_SQ_EDC_STALL_PATTERN_7,  DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK,   DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT,     0x5555 },
0620 
0621     {   0xFFFFFFFF  }  /* End of list */
0622 };
0623 
0624 static const struct vega10_didt_config_reg   PSMSEEDCStallDelayConfig_Vega10[] =
0625 {
0626 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0627  *      Offset                             Mask                                                 Shift                                                  Value
0628  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0629  */
0630     /* SQ EDC STALL DELAYs */
0631     {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT,  0x0000 },
0632     {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT,  0x0000 },
0633     {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT,  0x0000 },
0634     {   ixDIDT_SQ_EDC_STALL_DELAY_1,      DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK,  DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT,  0x0000 },
0635 
0636     {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT,  0x0000 },
0637     {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT,  0x0000 },
0638     {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT,  0x0000 },
0639     {   ixDIDT_SQ_EDC_STALL_DELAY_2,      DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK,  DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT,  0x0000 },
0640 
0641     {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK,  DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT,  0x0000 },
0642     {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK,  DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT,  0x0000 },
0643     {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 },
0644     {   ixDIDT_SQ_EDC_STALL_DELAY_3,      DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 },
0645 
0646     {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 },
0647     {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 },
0648     {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 },
0649     {   ixDIDT_SQ_EDC_STALL_DELAY_4,      DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 },
0650 
0651     {   0xFFFFFFFF  }  /* End of list */
0652 };
0653 
0654 static const struct vega10_didt_config_reg   PSMSEEDCCtrlResetConfig_Vega10[] =
0655 {
0656 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0657  *      Offset                             Mask                                                 Shift                                                  Value
0658  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0659  */
0660     /* SQ EDC CTRL */
0661     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0000 },
0662     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0001 },
0663     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
0664     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
0665     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
0666     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x0000 },
0667     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
0668     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0000 },
0669     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0000 },
0670     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0671     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0672 
0673     {   0xFFFFFFFF  }  /* End of list */
0674 };
0675 
0676 static const struct vega10_didt_config_reg   PSMSEEDCCtrlConfig_Vega10[] =
0677 {
0678 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0679  *      Offset                             Mask                                                 Shift                                                  Value
0680  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0681  */
0682     /* SQ EDC CTRL */
0683     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_EN_MASK,                       DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT,                        0x0001 },
0684     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK,                   DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT,                    0x0000 },
0685     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,          DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,           0x0000 },
0686     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK,              DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT,               0x0000 },
0687     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,  DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,   0x0000 },
0688     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK,   DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT,    0x000E },
0689     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,     DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,      0x0000 },
0690     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK,                    DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT,                     0x0001 },
0691     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK,          DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT,           0x0003 },
0692     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT,          0x0001 },
0693     {   ixDIDT_SQ_EDC_CTRL,                DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK,         DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT,          0x0000 },
0694 
0695     {   0xFFFFFFFF  }  /* End of list */
0696 };
0697 
0698 static const struct vega10_didt_config_reg   PSMGCEDCDroopCtrlConfig_vega10[] =
0699 {
0700 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0701  *      Offset                             Mask                                                 Shift                                                  Value
0702  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0703  */
0704     {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK,          GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT,           0x0001 },
0705     {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK,         GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT,          0x0384 },
0706     {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK,       GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT,        0x0001 },
0707     {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK,                 GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT,                  0x0001 },
0708     {   mmGC_EDC_DROOP_CTRL,               GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK,               GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT,                0x0001 },
0709 
0710     {   0xFFFFFFFF  }  /* End of list */
0711 };
0712 
0713 static const struct vega10_didt_config_reg   PSMGCEDCCtrlResetConfig_vega10[] =
0714 {
0715 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0716  *      Offset                             Mask                                                 Shift                                                  Value
0717  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0718  */
0719     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_EN_MASK,                            GC_EDC_CTRL__EDC_EN__SHIFT,                             0x0000 },
0720     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_SW_RST_MASK,                        GC_EDC_CTRL__EDC_SW_RST__SHIFT,                         0x0001 },
0721     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,               GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,                0x0000 },
0722     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_FORCE_STALL_MASK,                   GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT,                    0x0000 },
0723     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,       GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,        0x0000 },
0724     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,          GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,           0x0000 },
0725 
0726     {   0xFFFFFFFF  }  /* End of list */
0727 };
0728 
0729 static const struct vega10_didt_config_reg   PSMGCEDCCtrlConfig_vega10[] =
0730 {
0731 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0732  *      Offset                             Mask                                                 Shift                                                  Value
0733  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0734  */
0735     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_EN_MASK,                            GC_EDC_CTRL__EDC_EN__SHIFT,                             0x0001 },
0736     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_SW_RST_MASK,                        GC_EDC_CTRL__EDC_SW_RST__SHIFT,                         0x0000 },
0737     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK,               GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT,                0x0000 },
0738     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_FORCE_STALL_MASK,                   GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT,                    0x0000 },
0739     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK,       GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT,        0x0000 },
0740     {   mmGC_EDC_CTRL,                     GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK,          GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT,           0x0000 },
0741 
0742     {   0xFFFFFFFF  }  /* End of list */
0743 };
0744 
0745 static const struct vega10_didt_config_reg    AvfsPSMResetConfig_vega10[]=
0746 {
0747 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0748  *      Offset                             Mask                                                 Shift                                                  Value
0749  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0750  */
0751     {   0x16A02,                         0xFFFFFFFF,                                            0x0,                                                    0x0000005F },
0752     {   0x16A05,                         0xFFFFFFFF,                                            0x0,                                                    0x00000001 },
0753     {   0x16A06,                         0x00000001,                                            0x0,                                                    0x02000000 },
0754     {   0x16A01,                         0xFFFFFFFF,                                            0x0,                                                    0x00003027 },
0755 
0756     {   0xFFFFFFFF  }  /* End of list */
0757 };
0758 
0759 static const struct vega10_didt_config_reg    AvfsPSMInitConfig_vega10[] =
0760 {
0761 /* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0762  *      Offset                             Mask                                                 Shift                                                  Value
0763  * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0764  */
0765     {   0x16A05,                         0xFFFFFFFF,                                            0x18,                                                    0x00000001 },
0766     {   0x16A05,                         0xFFFFFFFF,                                            0x8,                                                     0x00000003 },
0767     {   0x16A05,                         0xFFFFFFFF,                                            0xa,                                                     0x00000006 },
0768     {   0x16A05,                         0xFFFFFFFF,                                            0x7,                                                     0x00000000 },
0769     {   0x16A06,                         0xFFFFFFFF,                                            0x18,                                                    0x00000001 },
0770     {   0x16A06,                         0xFFFFFFFF,                                            0x19,                                                    0x00000001 },
0771     {   0x16A01,                         0xFFFFFFFF,                                            0x0,                                                     0x00003027 },
0772 
0773     {   0xFFFFFFFF  }  /* End of list */
0774 };
0775 
0776 static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
0777 {
0778     uint32_t data;
0779 
0780     PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
0781 
0782     while (config_regs->offset != 0xFFFFFFFF) {
0783         switch (reg_type) {
0784         case VEGA10_CONFIGREG_DIDT:
0785             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
0786             data &= ~config_regs->mask;
0787             data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
0788             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
0789             break;
0790         case VEGA10_CONFIGREG_GCCAC:
0791             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
0792             data &= ~config_regs->mask;
0793             data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
0794             cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
0795             break;
0796         case VEGA10_CONFIGREG_SECAC:
0797             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
0798             data &= ~config_regs->mask;
0799             data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
0800             cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
0801             break;
0802         default:
0803             return -EINVAL;
0804         }
0805 
0806         config_regs++;
0807     }
0808 
0809     return 0;
0810 }
0811 
0812 static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
0813 {
0814     uint32_t data;
0815 
0816     while (config_regs->offset != 0xFFFFFFFF) {
0817         data = cgs_read_register(hwmgr->device, config_regs->offset);
0818         data &= ~config_regs->mask;
0819         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
0820         cgs_write_register(hwmgr->device, config_regs->offset, data);
0821         config_regs++;
0822     }
0823 
0824     return 0;
0825 }
0826 
0827 static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
0828 {
0829     uint32_t data;
0830     uint32_t en = (enable ? 1 : 0);
0831     uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
0832 
0833     if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
0834         CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
0835                      DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
0836         didt_block_info &= ~SQ_Enable_MASK;
0837         didt_block_info |= en << SQ_Enable_SHIFT;
0838     }
0839 
0840     if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
0841         CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
0842                      DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
0843         didt_block_info &= ~DB_Enable_MASK;
0844         didt_block_info |= en << DB_Enable_SHIFT;
0845     }
0846 
0847     if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
0848         CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
0849                      DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
0850         didt_block_info &= ~TD_Enable_MASK;
0851         didt_block_info |= en << TD_Enable_SHIFT;
0852     }
0853 
0854     if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
0855         CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
0856                      DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
0857         didt_block_info &= ~TCP_Enable_MASK;
0858         didt_block_info |= en << TCP_Enable_SHIFT;
0859     }
0860 
0861     if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
0862         CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
0863                      DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
0864     }
0865 
0866     if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
0867         if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
0868             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
0869             data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
0870             data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
0871             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
0872         }
0873 
0874         if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
0875             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
0876             data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
0877             data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
0878             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
0879         }
0880 
0881         if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
0882             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
0883             data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
0884             data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
0885             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
0886         }
0887 
0888         if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
0889             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
0890             data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
0891             data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
0892             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
0893         }
0894 
0895         if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
0896             data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
0897             data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
0898             data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
0899             cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
0900         }
0901     }
0902 
0903     /* For Vega10, SMC does not support any mask yet. */
0904     if (enable)
0905         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info,
0906                         NULL);
0907 
0908 }
0909 
0910 static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
0911 {
0912     struct amdgpu_device *adev = hwmgr->adev;
0913     int result;
0914     uint32_t num_se = 0, count, data;
0915 
0916     num_se = adev->gfx.config.max_shader_engines;
0917 
0918     amdgpu_gfx_rlc_enter_safe_mode(adev);
0919 
0920     mutex_lock(&adev->grbm_idx_mutex);
0921     for (count = 0; count < num_se; count++) {
0922         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
0923         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
0924 
0925         result =  vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
0926         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
0927         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
0928         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
0929         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
0930         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
0931         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
0932         result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
0933         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
0934 
0935         if (0 != result)
0936             break;
0937     }
0938     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
0939     mutex_unlock(&adev->grbm_idx_mutex);
0940 
0941     vega10_didt_set_mask(hwmgr, true);
0942 
0943     amdgpu_gfx_rlc_exit_safe_mode(adev);
0944 
0945     return 0;
0946 }
0947 
0948 static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
0949 {
0950     struct amdgpu_device *adev = hwmgr->adev;
0951 
0952     amdgpu_gfx_rlc_enter_safe_mode(adev);
0953 
0954     vega10_didt_set_mask(hwmgr, false);
0955 
0956     amdgpu_gfx_rlc_exit_safe_mode(adev);
0957 
0958     return 0;
0959 }
0960 
0961 static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
0962 {
0963     struct amdgpu_device *adev = hwmgr->adev;
0964     int result;
0965     uint32_t num_se = 0, count, data;
0966 
0967     num_se = adev->gfx.config.max_shader_engines;
0968 
0969     amdgpu_gfx_rlc_enter_safe_mode(adev);
0970 
0971     mutex_lock(&adev->grbm_idx_mutex);
0972     for (count = 0; count < num_se; count++) {
0973         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
0974         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
0975 
0976         result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
0977         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
0978         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
0979         result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
0980         if (0 != result)
0981             break;
0982     }
0983     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
0984     mutex_unlock(&adev->grbm_idx_mutex);
0985 
0986     vega10_didt_set_mask(hwmgr, true);
0987 
0988     amdgpu_gfx_rlc_exit_safe_mode(adev);
0989 
0990     vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
0991     if (PP_CAP(PHM_PlatformCaps_GCEDC))
0992         vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
0993 
0994     if (PP_CAP(PHM_PlatformCaps_PSM))
0995         vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
0996 
0997     return 0;
0998 }
0999 
1000 static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
1001 {
1002     struct amdgpu_device *adev = hwmgr->adev;
1003     uint32_t data;
1004 
1005     amdgpu_gfx_rlc_enter_safe_mode(adev);
1006 
1007     vega10_didt_set_mask(hwmgr, false);
1008 
1009     amdgpu_gfx_rlc_exit_safe_mode(adev);
1010 
1011     if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1012         data = 0x00000000;
1013         cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
1014     }
1015 
1016     if (PP_CAP(PHM_PlatformCaps_PSM))
1017         vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
1018 
1019     return 0;
1020 }
1021 
1022 static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
1023 {
1024     struct amdgpu_device *adev = hwmgr->adev;
1025     int result;
1026     uint32_t num_se = 0, count, data;
1027 
1028     num_se = adev->gfx.config.max_shader_engines;
1029 
1030     amdgpu_gfx_rlc_enter_safe_mode(adev);
1031 
1032     mutex_lock(&adev->grbm_idx_mutex);
1033     for (count = 0; count < num_se; count++) {
1034         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1035         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1036         result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1037         result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1038         result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1039         result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1040         result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1041         result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1042 
1043         if (0 != result)
1044             break;
1045     }
1046     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1047     mutex_unlock(&adev->grbm_idx_mutex);
1048 
1049     vega10_didt_set_mask(hwmgr, true);
1050 
1051     amdgpu_gfx_rlc_exit_safe_mode(adev);
1052 
1053     return 0;
1054 }
1055 
1056 static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
1057 {
1058     struct amdgpu_device *adev = hwmgr->adev;
1059 
1060     amdgpu_gfx_rlc_enter_safe_mode(adev);
1061 
1062     vega10_didt_set_mask(hwmgr, false);
1063 
1064     amdgpu_gfx_rlc_exit_safe_mode(adev);
1065 
1066     return 0;
1067 }
1068 
1069 static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1070 {
1071     struct amdgpu_device *adev = hwmgr->adev;
1072     int result = 0;
1073     uint32_t num_se = 0;
1074     uint32_t count, data;
1075 
1076     num_se = adev->gfx.config.max_shader_engines;
1077 
1078     amdgpu_gfx_rlc_enter_safe_mode(adev);
1079 
1080     vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1081 
1082     mutex_lock(&adev->grbm_idx_mutex);
1083     for (count = 0; count < num_se; count++) {
1084         data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1085         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1086         result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1087         result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1088         result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1089         result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1090 
1091         if (0 != result)
1092             break;
1093     }
1094     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1095     mutex_unlock(&adev->grbm_idx_mutex);
1096 
1097     vega10_didt_set_mask(hwmgr, true);
1098 
1099     amdgpu_gfx_rlc_exit_safe_mode(adev);
1100 
1101     vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
1102 
1103     if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1104         vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
1105         vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
1106     }
1107 
1108     if (PP_CAP(PHM_PlatformCaps_PSM))
1109         vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
1110 
1111     return 0;
1112 }
1113 
1114 static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1115 {
1116     struct amdgpu_device *adev = hwmgr->adev;
1117     uint32_t data;
1118 
1119     amdgpu_gfx_rlc_enter_safe_mode(adev);
1120 
1121     vega10_didt_set_mask(hwmgr, false);
1122 
1123     amdgpu_gfx_rlc_exit_safe_mode(adev);
1124 
1125     if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1126         data = 0x00000000;
1127         cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
1128     }
1129 
1130     if (PP_CAP(PHM_PlatformCaps_PSM))
1131         vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
1132 
1133     return 0;
1134 }
1135 
1136 static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1137 {
1138     struct amdgpu_device *adev = hwmgr->adev;
1139     int result;
1140 
1141     amdgpu_gfx_rlc_enter_safe_mode(adev);
1142 
1143     mutex_lock(&adev->grbm_idx_mutex);
1144     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1145     mutex_unlock(&adev->grbm_idx_mutex);
1146 
1147     result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1148     result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1149     if (0 != result)
1150         return result;
1151 
1152     vega10_didt_set_mask(hwmgr, false);
1153 
1154     amdgpu_gfx_rlc_exit_safe_mode(adev);
1155 
1156     return 0;
1157 }
1158 
1159 static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1160 {
1161     int result;
1162 
1163     result = vega10_disable_se_edc_config(hwmgr);
1164     PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1165 
1166     return 0;
1167 }
1168 
1169 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1170 {
1171     int result = 0;
1172     struct vega10_hwmgr *data = hwmgr->backend;
1173 
1174     if (data->smu_features[GNLD_DIDT].supported) {
1175         if (data->smu_features[GNLD_DIDT].enabled)
1176             PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
1177 
1178         switch (data->registry_data.didt_mode) {
1179         case 0:
1180             result = vega10_enable_cac_driving_se_didt_config(hwmgr);
1181             PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1182             break;
1183         case 2:
1184             result = vega10_enable_psm_gc_didt_config(hwmgr);
1185             PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1186             break;
1187         case 3:
1188             result = vega10_enable_se_edc_config(hwmgr);
1189             PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1190             break;
1191         case 1:
1192         case 4:
1193         case 5:
1194             result = vega10_enable_psm_gc_edc_config(hwmgr);
1195             PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1196             break;
1197         case 6:
1198             result = vega10_enable_se_edc_force_stall_config(hwmgr);
1199             PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1200             break;
1201         default:
1202             result = -EINVAL;
1203             break;
1204         }
1205 
1206         if (0 == result) {
1207             result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1208             PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1209             data->smu_features[GNLD_DIDT].enabled = true;
1210         }
1211     }
1212 
1213     return result;
1214 }
1215 
1216 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1217 {
1218     int result = 0;
1219     struct vega10_hwmgr *data = hwmgr->backend;
1220 
1221     if (data->smu_features[GNLD_DIDT].supported) {
1222         if (!data->smu_features[GNLD_DIDT].enabled)
1223             PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
1224 
1225         switch (data->registry_data.didt_mode) {
1226         case 0:
1227             result = vega10_disable_cac_driving_se_didt_config(hwmgr);
1228             PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1229             break;
1230         case 2:
1231             result = vega10_disable_psm_gc_didt_config(hwmgr);
1232             PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
1233             break;
1234         case 3:
1235             result = vega10_disable_se_edc_config(hwmgr);
1236             PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
1237             break;
1238         case 1:
1239         case 4:
1240         case 5:
1241             result = vega10_disable_psm_gc_edc_config(hwmgr);
1242             PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
1243             break;
1244         case 6:
1245             result = vega10_disable_se_edc_force_stall_config(hwmgr);
1246             PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
1247             break;
1248         default:
1249             result = -EINVAL;
1250             break;
1251         }
1252 
1253         if (0 == result) {
1254             result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1255             PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1256             data->smu_features[GNLD_DIDT].enabled = false;
1257         }
1258     }
1259 
1260     return result;
1261 }
1262 
1263 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1264 {
1265     struct vega10_hwmgr *data = hwmgr->backend;
1266     struct phm_ppt_v2_information *table_info =
1267             (struct phm_ppt_v2_information *)(hwmgr->pptable);
1268     struct phm_tdp_table *tdp_table = table_info->tdp_table;
1269     PPTable_t *table = &(data->smc_state_table.pp_table);
1270 
1271     table->SocketPowerLimit = cpu_to_le16(
1272             tdp_table->usMaximumPowerDeliveryLimit);
1273     table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
1274     table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
1275     table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
1276     table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
1277     table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
1278     table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
1279     table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
1280     table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
1281     table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
1282     table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
1283     table->LoadLineResistance =
1284             hwmgr->platform_descriptor.LoadLineSlope * 256;
1285     table->FitLimit = 0; /* Not used for Vega10 */
1286 
1287     table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
1288     table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
1289     table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
1290     table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
1291 
1292     table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
1293     table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
1294 
1295     table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
1296     table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
1297 
1298     table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
1299     table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
1300 }
1301 
1302 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1303 {
1304     struct vega10_hwmgr *data = hwmgr->backend;
1305 
1306     if (data->registry_data.enable_pkg_pwr_tracking_feature)
1307         smum_send_msg_to_smc_with_parameter(hwmgr,
1308                 PPSMC_MSG_SetPptLimit, n,
1309                 NULL);
1310 
1311     return 0;
1312 }
1313 
1314 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1315 {
1316     struct vega10_hwmgr *data = hwmgr->backend;
1317     struct phm_ppt_v2_information *table_info =
1318             (struct phm_ppt_v2_information *)(hwmgr->pptable);
1319     struct phm_tdp_table *tdp_table = table_info->tdp_table;
1320     int result = 0;
1321 
1322     hwmgr->default_power_limit = hwmgr->power_limit =
1323             (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
1324 
1325     if (!hwmgr->not_vf)
1326         return 0;
1327 
1328     if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1329         if (data->smu_features[GNLD_PPT].supported)
1330             PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1331                     true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1332                     "Attempt to enable PPT feature Failed!",
1333                     data->smu_features[GNLD_PPT].supported = false);
1334 
1335         if (data->smu_features[GNLD_TDC].supported)
1336             PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1337                     true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1338                     "Attempt to enable PPT feature Failed!",
1339                     data->smu_features[GNLD_TDC].supported = false);
1340 
1341         result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
1342         PP_ASSERT_WITH_CODE(!result,
1343                 "Failed to set Default Power Limit in SMC!",
1344                 return result);
1345     }
1346 
1347     return result;
1348 }
1349 
1350 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1351 {
1352     struct vega10_hwmgr *data = hwmgr->backend;
1353 
1354     if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1355         if (data->smu_features[GNLD_PPT].supported)
1356             PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1357                     false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1358                     "Attempt to disable PPT feature Failed!",
1359                     data->smu_features[GNLD_PPT].supported = false);
1360 
1361         if (data->smu_features[GNLD_TDC].supported)
1362             PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1363                     false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1364                     "Attempt to disable PPT feature Failed!",
1365                     data->smu_features[GNLD_TDC].supported = false);
1366     }
1367 
1368     return 0;
1369 }
1370 
1371 static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1372         uint32_t adjust_percent)
1373 {
1374     smum_send_msg_to_smc_with_parameter(hwmgr,
1375             PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
1376             NULL);
1377 }
1378 
1379 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
1380 {
1381     int adjust_percent;
1382 
1383     if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1384         adjust_percent =
1385                 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1386                 hwmgr->platform_descriptor.TDPAdjustment :
1387                 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1388         vega10_set_overdrive_target_percentage(hwmgr,
1389                 (uint32_t)adjust_percent);
1390     }
1391     return 0;
1392 }
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