powerplay/hwmgr/vega10_hwmgr.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _VEGA10_HWMGR_H_
0025 #define _VEGA10_HWMGR_H_
0026
0027 #include "hwmgr.h"
0028 #include "smu9_driver_if.h"
0029 #include "ppatomctrl.h"
0030 #include "ppatomfwctrl.h"
0031 #include "vega10_ppsmc.h"
0032 #include "vega10_powertune.h"
0033
0034 #define VEGA10_MAX_HARDWARE_POWERLEVELS 2
0035
0036 #define WaterMarksExist  1
0037 #define WaterMarksLoaded 2
0038
0039 enum {
0040     GNLD_DPM_PREFETCHER = 0,
0041     GNLD_DPM_GFXCLK,
0042     GNLD_DPM_UCLK,
0043     GNLD_DPM_SOCCLK,
0044     GNLD_DPM_UVD,
0045     GNLD_DPM_VCE,
0046     GNLD_ULV,
0047     GNLD_DPM_MP0CLK,
0048     GNLD_DPM_LINK,
0049     GNLD_DPM_DCEFCLK,
0050     GNLD_AVFS,
0051     GNLD_DS_GFXCLK,
0052     GNLD_DS_SOCCLK,
0053     GNLD_DS_LCLK,
0054     GNLD_PPT,
0055     GNLD_TDC,
0056     GNLD_THERMAL,
0057     GNLD_GFX_PER_CU_CG,
0058     GNLD_RM,
0059     GNLD_DS_DCEFCLK,
0060     GNLD_ACDC,
0061     GNLD_VR0HOT,
0062     GNLD_VR1HOT,
0063     GNLD_FW_CTF,
0064     GNLD_LED_DISPLAY,
0065     GNLD_FAN_CONTROL,
0066     GNLD_FEATURE_FAST_PPT_BIT,
0067     GNLD_DIDT,
0068     GNLD_ACG,
0069     GNLD_PCC_LIMIT,
0070     GNLD_FEATURES_MAX
0071 };
0072
0073 #define GNLD_DPM_MAX    (GNLD_DPM_DCEFCLK + 1)
0074
0075 #define SMC_DPM_FEATURES    0x30F
0076
0077 struct smu_features {
0078     bool supported;
0079     bool enabled;
0080     uint32_t smu_feature_id;
0081     uint32_t smu_feature_bitmap;
0082 };
0083
0084 struct vega10_performance_level {
0085     uint32_t  soc_clock;
0086     uint32_t  gfx_clock;
0087     uint32_t  mem_clock;
0088 };
0089
0090 struct vega10_bacos {
0091     uint32_t                       baco_flags;
0092     /* struct vega10_performance_level  performance_level; */
0093 };
0094
0095 struct vega10_uvd_clocks {
0096     uint32_t  vclk;
0097     uint32_t  dclk;
0098 };
0099
0100 struct vega10_vce_clocks {
0101     uint32_t  evclk;
0102     uint32_t  ecclk;
0103 };
0104
0105 struct vega10_power_state {
0106     uint32_t                  magic;
0107     struct vega10_uvd_clocks    uvd_clks;
0108     struct vega10_vce_clocks    vce_clks;
0109     uint16_t                  performance_level_count;
0110     bool                      dc_compatible;
0111     uint32_t                  sclk_threshold;
0112     struct vega10_performance_level  performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS];
0113 };
0114
0115 struct vega10_dpm_level {
0116     bool    enabled;
0117     uint32_t    value;
0118     uint32_t    param1;
0119 };
0120
0121 #define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5
0122 #define MAX_REGULAR_DPM_NUMBER 8
0123 #define MAX_PCIE_CONF 2
0124 #define VEGA10_MINIMUM_ENGINE_CLOCK 2500
0125
0126 struct vega10_dpm_state {
0127     uint32_t  soft_min_level;
0128     uint32_t  soft_max_level;
0129     uint32_t  hard_min_level;
0130     uint32_t  hard_max_level;
0131 };
0132
0133 struct vega10_single_dpm_table {
0134     uint32_t        count;
0135     struct vega10_dpm_state dpm_state;
0136     struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
0137 };
0138
0139 struct vega10_pcie_table {
0140     uint16_t count;
0141     uint8_t  pcie_gen[MAX_PCIE_CONF];
0142     uint8_t  pcie_lane[MAX_PCIE_CONF];
0143     uint32_t lclk[MAX_PCIE_CONF];
0144 };
0145
0146 struct vega10_dpm_table {
0147     struct vega10_single_dpm_table  soc_table;
0148     struct vega10_single_dpm_table  gfx_table;
0149     struct vega10_single_dpm_table  mem_table;
0150     struct vega10_single_dpm_table  eclk_table;
0151     struct vega10_single_dpm_table  vclk_table;
0152     struct vega10_single_dpm_table  dclk_table;
0153     struct vega10_single_dpm_table  dcef_table;
0154     struct vega10_single_dpm_table  pixel_table;
0155     struct vega10_single_dpm_table  display_table;
0156     struct vega10_single_dpm_table  phy_table;
0157     struct vega10_pcie_table        pcie_table;
0158 };
0159
0160 #define VEGA10_MAX_LEAKAGE_COUNT  8
0161 struct vega10_leakage_voltage {
0162     uint16_t  count;
0163     uint16_t  leakage_id[VEGA10_MAX_LEAKAGE_COUNT];
0164     uint16_t  actual_voltage[VEGA10_MAX_LEAKAGE_COUNT];
0165 };
0166
0167 struct vega10_display_timing {
0168     uint32_t  min_clock_in_sr;
0169     uint32_t  num_existing_displays;
0170 };
0171
0172 struct vega10_dpmlevel_enable_mask {
0173     uint32_t  uvd_dpm_enable_mask;
0174     uint32_t  vce_dpm_enable_mask;
0175     uint32_t  acp_dpm_enable_mask;
0176     uint32_t  samu_dpm_enable_mask;
0177     uint32_t  sclk_dpm_enable_mask;
0178     uint32_t  mclk_dpm_enable_mask;
0179 };
0180
0181 struct vega10_vbios_boot_state {
0182     bool        bsoc_vddc_lock;
0183     uint16_t    vddc;
0184     uint16_t    vddci;
0185     uint16_t    mvddc;
0186     uint16_t    vdd_gfx;
0187     uint32_t    gfx_clock;
0188     uint32_t    mem_clock;
0189     uint32_t    soc_clock;
0190     uint32_t    dcef_clock;
0191 };
0192
0193 struct vega10_smc_state_table {
0194     uint32_t        soc_boot_level;
0195     uint32_t        gfx_boot_level;
0196     uint32_t        dcef_boot_level;
0197     uint32_t        mem_boot_level;
0198     uint32_t        uvd_boot_level;
0199     uint32_t        vce_boot_level;
0200     uint32_t        gfx_max_level;
0201     uint32_t        mem_max_level;
0202     uint32_t        soc_max_level;
0203     uint8_t         vr_hot_gpio;
0204     uint8_t         ac_dc_gpio;
0205     uint8_t         therm_out_gpio;
0206     uint8_t         therm_out_polarity;
0207     uint8_t         therm_out_mode;
0208     PPTable_t       pp_table;
0209     Watermarks_t    water_marks_table;
0210     AvfsTable_t     avfs_table;
0211     AvfsFuseOverride_t avfs_fuse_override_table;
0212 };
0213
0214 struct vega10_mclk_latency_entries {
0215     uint32_t  frequency;
0216     uint32_t  latency;
0217 };
0218
0219 struct vega10_mclk_latency_table {
0220     uint32_t  count;
0221     struct vega10_mclk_latency_entries  entries[MAX_REGULAR_DPM_NUMBER];
0222 };
0223
0224 struct vega10_registry_data {
0225     uint8_t   ac_dc_switch_gpio_support;
0226     uint8_t   avfs_support;
0227     uint8_t   cac_support;
0228     uint8_t   clock_stretcher_support;
0229     uint8_t   db_ramping_support;
0230     uint8_t   didt_mode;
0231     uint8_t   didt_support;
0232     uint8_t   edc_didt_support;
0233     uint8_t   dynamic_state_patching_support;
0234     uint8_t   enable_pkg_pwr_tracking_feature;
0235     uint8_t   enable_tdc_limit_feature;
0236     uint32_t  fast_watermark_threshold;
0237     uint8_t   force_dpm_high;
0238     uint8_t   fuzzy_fan_control_support;
0239     uint8_t   long_idle_baco_support;
0240     uint8_t   mclk_dpm_key_disabled;
0241     uint8_t   od_state_in_dc_support;
0242     uint8_t   pcieLaneOverride;
0243     uint8_t   pcieSpeedOverride;
0244     uint32_t  pcieClockOverride;
0245     uint8_t   pcie_dpm_key_disabled;
0246     uint8_t   dcefclk_dpm_key_disabled;
0247     uint8_t   power_containment_support;
0248     uint8_t   ppt_support;
0249     uint8_t   prefetcher_dpm_key_disabled;
0250     uint8_t   quick_transition_support;
0251     uint8_t   regulator_hot_gpio_support;
0252     uint8_t   sclk_deep_sleep_support;
0253     uint8_t   sclk_dpm_key_disabled;
0254     uint8_t   sclk_from_vbios;
0255     uint8_t   sclk_throttle_low_notification;
0256     uint8_t   show_baco_dbg_info;
0257     uint8_t   skip_baco_hardware;
0258     uint8_t   socclk_dpm_key_disabled;
0259     uint8_t   spll_shutdown_support;
0260     uint8_t   sq_ramping_support;
0261     uint32_t  stable_pstate_sclk_dpm_percentage;
0262     uint8_t   tcp_ramping_support;
0263     uint8_t   tdc_support;
0264     uint8_t   td_ramping_support;
0265     uint8_t   dbr_ramping_support;
0266     uint8_t   gc_didt_support;
0267     uint8_t   psm_didt_support;
0268     uint8_t   thermal_out_gpio_support;
0269     uint8_t   thermal_support;
0270     uint8_t   fw_ctf_enabled;
0271     uint8_t   fan_control_support;
0272     uint8_t   ulps_support;
0273     uint8_t   ulv_support;
0274     uint32_t  vddc_vddci_delta;
0275     uint8_t   odn_feature_enable;
0276     uint8_t   disable_water_mark;
0277     uint8_t   zrpm_stop_temp;
0278     uint8_t   zrpm_start_temp;
0279     uint8_t   led_dpm_enabled;
0280     uint8_t   vr0hot_enabled;
0281     uint8_t   vr1hot_enabled;
0282 };
0283
0284 struct vega10_odn_clock_voltage_dependency_table {
0285     uint32_t count;
0286     struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
0287 };
0288
0289 struct vega10_odn_vddc_lookup_table {
0290     uint32_t count;
0291     struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER];
0292 };
0293
0294 struct vega10_odn_dpm_table {
0295     struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_sclk;
0296     struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_mclk;
0297     struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_socclk;
0298     struct vega10_odn_vddc_lookup_table vddc_lookup_table;
0299     uint32_t max_vddc;
0300     uint32_t min_vddc;
0301 };
0302
0303 struct vega10_odn_fan_table {
0304     uint32_t    target_fan_speed;
0305     uint32_t    target_temperature;
0306     uint32_t    min_performance_clock;
0307     uint32_t    min_fan_limit;
0308 };
0309
0310 struct vega10_hwmgr {
0311     struct vega10_dpm_table          dpm_table;
0312     struct vega10_dpm_table          golden_dpm_table;
0313     struct vega10_registry_data      registry_data;
0314     struct vega10_vbios_boot_state   vbios_boot_state;
0315     struct vega10_mclk_latency_table mclk_latency_table;
0316
0317     struct vega10_leakage_voltage    vddc_leakage;
0318
0319     uint32_t                           vddc_control;
0320     struct pp_atomfwctrl_voltage_table vddc_voltage_table;
0321     uint32_t                           mvdd_control;
0322     struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
0323     uint32_t                           vddci_control;
0324     struct pp_atomfwctrl_voltage_table vddci_voltage_table;
0325
0326     uint32_t                           active_auto_throttle_sources;
0327     uint32_t                           water_marks_bitmap;
0328     struct vega10_bacos                bacos;
0329
0330     struct vega10_odn_dpm_table       odn_dpm_table;
0331     struct vega10_odn_fan_table       odn_fan_table;
0332
0333     /* ---- General data ---- */
0334     uint8_t                           need_update_dpm_table;
0335
0336     bool                           cac_enabled;
0337     bool                           battery_state;
0338     bool                           is_tlu_enabled;
0339
0340     uint32_t                       low_sclk_interrupt_threshold;
0341
0342     uint32_t                       total_active_cus;
0343
0344     struct vega10_display_timing display_timing;
0345
0346     /* ---- Vega10 Dyn Register Settings ---- */
0347
0348     uint32_t                       debug_settings;
0349     uint32_t                       lowest_uclk_reserved_for_ulv;
0350     uint32_t                       gfxclk_average_alpha;
0351     uint32_t                       socclk_average_alpha;
0352     uint32_t                       uclk_average_alpha;
0353     uint32_t                       gfx_activity_average_alpha;
0354     uint32_t                       display_voltage_mode;
0355     uint32_t                       dcef_clk_quad_eqn_a;
0356     uint32_t                       dcef_clk_quad_eqn_b;
0357     uint32_t                       dcef_clk_quad_eqn_c;
0358     uint32_t                       disp_clk_quad_eqn_a;
0359     uint32_t                       disp_clk_quad_eqn_b;
0360     uint32_t                       disp_clk_quad_eqn_c;
0361     uint32_t                       pixel_clk_quad_eqn_a;
0362     uint32_t                       pixel_clk_quad_eqn_b;
0363     uint32_t                       pixel_clk_quad_eqn_c;
0364     uint32_t                       phy_clk_quad_eqn_a;
0365     uint32_t                       phy_clk_quad_eqn_b;
0366     uint32_t                       phy_clk_quad_eqn_c;
0367
0368     /* ---- Thermal Temperature Setting ---- */
0369     struct vega10_dpmlevel_enable_mask     dpm_level_enable_mask;
0370
0371     /* ---- Power Gating States ---- */
0372     bool                           uvd_power_gated;
0373     bool                           vce_power_gated;
0374     bool                           need_long_memory_training;
0375
0376     /* Internal settings to apply the application power optimization parameters */
0377     uint32_t                       disable_dpm_mask;
0378
0379     /* ---- SMU9 ---- */
0380     struct smu_features            smu_features[GNLD_FEATURES_MAX];
0381     struct vega10_smc_state_table  smc_state_table;
0382
0383     uint32_t                       config_telemetry;
0384     uint32_t                       acg_loop_state;
0385     uint32_t                       mem_channels;
0386     uint8_t                       custom_profile_mode[4];
0387 };
0388
0389 #define VEGA10_DPM2_NEAR_TDP_DEC                      10
0390 #define VEGA10_DPM2_ABOVE_SAFE_INC                    5
0391 #define VEGA10_DPM2_BELOW_SAFE_INC                    20
0392
0393 #define VEGA10_DPM2_LTA_WINDOW_SIZE                   7
0394
0395 #define VEGA10_DPM2_LTS_TRUNCATE                      0
0396
0397 #define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT            80
0398
0399 #define VEGA10_DPM2_MAXPS_PERCENT_M                   90
0400 #define VEGA10_DPM2_MAXPS_PERCENT_H                   90
0401
0402 #define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN         50
0403
0404 #define VEGA10_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
0405 #define VEGA10_DPM2_SQ_RAMP_MIN_POWER                 0x12
0406 #define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
0407 #define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
0408 #define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
0409
0410 #define VEGA10_VOLTAGE_CONTROL_NONE                   0x0
0411 #define VEGA10_VOLTAGE_CONTROL_BY_GPIO                0x1
0412 #define VEGA10_VOLTAGE_CONTROL_BY_SVID2               0x2
0413 #define VEGA10_VOLTAGE_CONTROL_MERGED                 0x3
0414 /* To convert to Q8.8 format for firmware */
0415 #define VEGA10_Q88_FORMAT_CONVERSION_UNIT             256
0416
0417 #define VEGA10_UNUSED_GPIO_PIN       0x7F
0418
0419 #define VEGA10_THERM_OUT_MODE_DISABLE       0x0
0420 #define VEGA10_THERM_OUT_MODE_THERM_ONLY    0x1
0421 #define VEGA10_THERM_OUT_MODE_THERM_VRHOT   0x2
0422
0423 #define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT   0xffffffff
0424 #define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT    0xffffffff
0425
0426 #define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
0427 #define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT       25 /* 10% * 255 = 25 */
0428 #define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT      25 /* 10% * 255 = 25 */
0429 #define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT  25 /* 10% * 255 = 25 */
0430
0431 #define VEGA10_UMD_PSTATE_GFXCLK_LEVEL         0x3
0432 #define VEGA10_UMD_PSTATE_SOCCLK_LEVEL         0x3
0433 #define VEGA10_UMD_PSTATE_MCLK_LEVEL           0x2
0434
0435 extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
0436 extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
0437 extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
0438 extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
0439 extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
0440 int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
0441 int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
0442 int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
0443 int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
0444 int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
0445 int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
0446
0447 #endif /* _VEGA10_HWMGR_H_ */