powerplay/hwmgr/smu9_baco.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "soc15.h"
0025 #include "soc15_hw_ip.h"
0026 #include "vega10_ip_offset.h"
0027 #include "soc15_common.h"
0028 #include "vega10_inc.h"
0029 #include "smu9_baco.h"
0030
0031 int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
0032 {
0033     struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
0034     uint32_t reg, data;
0035
0036     *cap = false;
0037     if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
0038         return 0;
0039
0040     WREG32(0x12074, 0xFFF0003B);
0041     data = RREG32(0x12075);
0042
0043     if (data == 0x1) {
0044         reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);
0045
0046         if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)
0047             *cap = true;
0048     }
0049
0050     return 0;
0051 }
0052
0053 int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
0054 {
0055     struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
0056     uint32_t reg;
0057
0058     reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);
0059
0060     if (reg & BACO_CNTL__BACO_MODE_MASK)
0061         /* gfx has already entered BACO state */
0062         *state = BACO_STATE_IN;
0063     else
0064         *state = BACO_STATE_OUT;
0065     return 0;
0066 }