powerplay/hwmgr/smu8_hwmgr.h

0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef _SMU8_HWMGR_H_
0025 #define _SMU8_HWMGR_H_
0026
0027 #include "cgs_common.h"
0028 #include "ppatomctrl.h"
0029
0030 #define SMU8_NUM_NBPSTATES               4
0031 #define SMU8_NUM_NBPMEMORYCLOCK          2
0032 #define MAX_DISPLAY_CLOCK_LEVEL        8
0033 #define SMU8_MAX_HARDWARE_POWERLEVELS    8
0034 #define SMU8_VOTINGRIGHTSCLIENTS_DFLT0   0x3FFFC102
0035 #define SMU8_MIN_DEEP_SLEEP_SCLK         800
0036
0037 /* Carrizo device IDs */
0038 #define DEVICE_ID_CZ_9870             0x9870
0039 #define DEVICE_ID_CZ_9874             0x9874
0040 #define DEVICE_ID_CZ_9875             0x9875
0041 #define DEVICE_ID_CZ_9876             0x9876
0042 #define DEVICE_ID_CZ_9877             0x9877
0043
0044 struct smu8_dpm_entry {
0045     uint32_t soft_min_clk;
0046     uint32_t hard_min_clk;
0047     uint32_t soft_max_clk;
0048     uint32_t hard_max_clk;
0049 };
0050
0051 struct smu8_sys_info {
0052     uint32_t bootup_uma_clock;
0053     uint32_t bootup_engine_clock;
0054     uint32_t dentist_vco_freq;
0055     uint32_t nb_dpm_enable;
0056     uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK];
0057     uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES];
0058     uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES];
0059     uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL];
0060     uint16_t bootup_nb_voltage_index;
0061     uint8_t htc_tmp_lmt;
0062     uint8_t htc_hyst_lmt;
0063     uint32_t system_config;
0064     uint32_t uma_channel_number;
0065 };
0066
0067 #define MAX_DISPLAYPHY_IDS          0x8
0068 #define DISPLAYPHY_LANEMASK         0xF
0069 #define UNKNOWN_TRANSMITTER_PHY_ID      (-1)
0070
0071 #define DISPLAYPHY_PHYID_SHIFT          24
0072 #define DISPLAYPHY_LANESELECT_SHIFT     16
0073
0074 #define DISPLAYPHY_RX_SELECT            0x1
0075 #define DISPLAYPHY_TX_SELECT            0x2
0076 #define DISPLAYPHY_CORE_SELECT          0x4
0077
0078 #define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \
0079         (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \
0080         ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \
0081         ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \
0082         ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \
0083         ((core) ? DISPLAYPHY_CORE_SELECT : 0))
0084
0085 struct smu8_display_phy_info_entry {
0086     uint8_t phy_present;
0087     uint8_t active_lane_mapping;
0088     uint8_t display_config_type;
0089     uint8_t active_number_of_lanes;
0090 };
0091
0092 #define SMU8_MAX_DISPLAYPHY_IDS         10
0093
0094 struct smu8_display_phy_info {
0095     bool display_phy_access_initialized;
0096     struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS];
0097 };
0098
0099 struct smu8_power_level {
0100     uint32_t engineClock;
0101     uint8_t vddcIndex;
0102     uint8_t dsDividerIndex;
0103     uint8_t ssDividerIndex;
0104     uint8_t allowGnbSlow;
0105     uint8_t forceNBPstate;
0106     uint8_t display_wm;
0107     uint8_t vce_wm;
0108     uint8_t numSIMDToPowerDown;
0109     uint8_t hysteresis_up;
0110     uint8_t rsv[3];
0111 };
0112
0113 struct smu8_uvd_clocks {
0114     uint32_t vclk;
0115     uint32_t dclk;
0116     uint32_t vclk_low_divider;
0117     uint32_t vclk_high_divider;
0118     uint32_t dclk_low_divider;
0119     uint32_t dclk_high_divider;
0120 };
0121
0122 enum smu8_pstate_previous_action {
0123     DO_NOTHING = 1,
0124     FORCE_HIGH,
0125     CANCEL_FORCE_HIGH
0126 };
0127
0128 struct pp_disable_nb_ps_flags {
0129     union {
0130         struct {
0131             uint32_t entry : 1;
0132             uint32_t display : 1;
0133             uint32_t driver: 1;
0134             uint32_t vce : 1;
0135             uint32_t uvd : 1;
0136             uint32_t acp : 1;
0137             uint32_t reserved: 26;
0138         } bits;
0139         uint32_t u32All;
0140     };
0141 };
0142
0143 struct smu8_power_state {
0144     unsigned int magic;
0145     uint32_t level;
0146     struct smu8_uvd_clocks uvd_clocks;
0147     uint32_t evclk;
0148     uint32_t ecclk;
0149     uint32_t samclk;
0150     uint32_t acpclk;
0151     bool need_dfs_bypass;
0152     uint32_t nbps_flags;
0153     uint32_t bapm_flags;
0154     uint8_t dpm_0_pg_nb_ps_low;
0155     uint8_t dpm_0_pg_nb_ps_high;
0156     uint8_t dpm_x_nb_ps_low;
0157     uint8_t dpm_x_nb_ps_high;
0158     enum smu8_pstate_previous_action action;
0159     struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS];
0160     struct pp_disable_nb_ps_flags disable_nb_ps_flag;
0161 };
0162
0163 #define DPMFlags_SCLK_Enabled           0x00000001
0164 #define DPMFlags_UVD_Enabled            0x00000002
0165 #define DPMFlags_VCE_Enabled            0x00000004
0166 #define DPMFlags_ACP_Enabled            0x00000008
0167 #define DPMFlags_ForceHighestValid      0x40000000
0168 #define DPMFlags_Debug              0x80000000
0169
0170 #define SMU_EnabledFeatureScoreboard_AcpDpmOn   0x00000001 /* bit 0 */
0171 #define SMU_EnabledFeatureScoreboard_UvdDpmOn   0x00800000 /* bit 23 */
0172 #define SMU_EnabledFeatureScoreboard_VceDpmOn   0x01000000 /* bit 24 */
0173
0174 struct cc6_settings {
0175     bool cc6_setting_changed;
0176     bool nb_pstate_switch_disable;/* controls NB PState switch */
0177     bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
0178     bool cpu_pstate_disable;
0179     uint32_t cpu_pstate_separation_time;
0180 };
0181
0182 struct smu8_hwmgr {
0183     uint32_t dpm_interval;
0184
0185     uint32_t voltage_drop_threshold;
0186
0187     uint32_t voting_rights_clients;
0188
0189     uint32_t disable_driver_thermal_policy;
0190
0191     uint32_t static_screen_threshold;
0192
0193     uint32_t gfx_power_gating_threshold;
0194
0195     uint32_t activity_hysteresis;
0196     uint32_t bootup_sclk_divider;
0197     uint32_t gfx_ramp_step;
0198     uint32_t gfx_ramp_delay; /* in micro-seconds */
0199
0200     uint32_t thermal_auto_throttling_treshold;
0201
0202     struct smu8_sys_info sys_info;
0203
0204     struct smu8_power_level boot_power_level;
0205     struct smu8_power_state *smu8_current_ps;
0206     struct smu8_power_state *smu8_requested_ps;
0207
0208     uint32_t mgcg_cgtt_local0;
0209     uint32_t mgcg_cgtt_local1;
0210
0211     uint32_t tdr_clock; /* in 10khz unit */
0212
0213     uint32_t ddi_power_gating_disabled;
0214     uint32_t disable_gfx_power_gating_in_uvd;
0215     uint32_t disable_nb_ps3_in_battery;
0216
0217     uint32_t lock_nb_ps_in_uvd_play_back;
0218
0219     struct smu8_display_phy_info display_phy_info;
0220     uint32_t vce_slow_sclk_threshold; /* default 200mhz */
0221     uint32_t dce_slow_sclk_threshold; /* default 300mhz */
0222     uint32_t min_sclk_did;  /* minimum sclk divider */
0223
0224     bool disp_clk_bypass;
0225     bool disp_clk_bypass_pending;
0226     uint32_t bapm_enabled;
0227     uint32_t clock_slow_down_freq;
0228     uint32_t skip_clock_slow_down;
0229     uint32_t enable_nb_ps_policy;
0230     uint32_t voltage_drop_in_dce_power_gating;
0231     uint32_t uvd_dpm_interval;
0232     uint32_t override_dynamic_mgpg;
0233     uint32_t lclk_deep_enabled;
0234
0235     uint32_t uvd_performance;
0236
0237     bool video_start;
0238     bool battery_state;
0239     uint32_t lowest_valid;
0240     uint32_t highest_valid;
0241     uint32_t high_voltage_threshold;
0242     uint32_t is_nb_dpm_enabled;
0243     struct cc6_settings cc6_settings;
0244     uint32_t is_voltage_island_enabled;
0245
0246     bool pgacpinit;
0247
0248     uint8_t disp_config;
0249
0250     /* PowerTune */
0251     uint32_t power_containment_features;
0252     bool cac_enabled;
0253     bool disable_uvd_power_tune_feature;
0254     bool enable_ba_pm_feature;
0255     bool enable_tdc_limit_feature;
0256
0257     uint32_t sram_end;
0258     uint32_t dpm_table_start;
0259     uint32_t soft_regs_start;
0260
0261     uint8_t uvd_level_count;
0262     uint8_t vce_level_count;
0263
0264     uint8_t acp_level_count;
0265     uint8_t samu_level_count;
0266     uint32_t fps_high_threshold;
0267     uint32_t fps_low_threshold;
0268
0269     uint32_t dpm_flags;
0270     struct smu8_dpm_entry sclk_dpm;
0271     struct smu8_dpm_entry uvd_dpm;
0272     struct smu8_dpm_entry vce_dpm;
0273     struct smu8_dpm_entry acp_dpm;
0274
0275     uint8_t uvd_boot_level;
0276     uint8_t vce_boot_level;
0277     uint8_t acp_boot_level;
0278     uint8_t samu_boot_level;
0279     uint8_t uvd_interval;
0280     uint8_t vce_interval;
0281     uint8_t acp_interval;
0282     uint8_t samu_interval;
0283
0284     uint8_t graphics_interval;
0285     uint8_t graphics_therm_throttle_enable;
0286     uint8_t graphics_voltage_change_enable;
0287
0288     uint8_t graphics_clk_slow_enable;
0289     uint8_t graphics_clk_slow_divider;
0290
0291     uint32_t display_cac;
0292     uint32_t low_sclk_interrupt_threshold;
0293
0294     uint32_t dram_log_addr_h;
0295     uint32_t dram_log_addr_l;
0296     uint32_t dram_log_phy_addr_h;
0297     uint32_t dram_log_phy_addr_l;
0298     uint32_t dram_log_buff_size;
0299
0300     bool uvd_power_gated;
0301     bool vce_power_gated;
0302     bool samu_power_gated;
0303     bool acp_power_gated;
0304     bool acp_power_up_no_dsp;
0305     uint32_t active_process_mask;
0306
0307     uint32_t max_sclk_level;
0308     uint32_t num_of_clk_entries;
0309 };
0310
0311 #endif /* _SMU8_HWMGR_H_ */